mirror of
https://github.com/DaedalusX64/daedalus.git
synced 2025-04-02 10:21:48 -04:00
127 lines
3.4 KiB
C++
127 lines
3.4 KiB
C++
#define TEST_DISABLE_REG_FUNCS DAEDALUS_PROFILE(__FUNCTION__);
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch___osDisableInt_Mario()
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{
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TEST_DISABLE_REG_FUNCS
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u32 CurrSR = gCPUState.CPUControl[C0_SR]._u32;
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gCPUState.CPUControl[C0_SR]._u32 = CurrSR & ~SR_IE;
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gGPR[REG_v0]._s64 = (s64)(CurrSR & SR_IE);
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch___osDisableInt_Zelda()
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{
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TEST_DISABLE_REG_FUNCS
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// Same as the above
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u32 CurrSR = gCPUState.CPUControl[C0_SR]._u32;
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gCPUState.CPUControl[C0_SR]._u32 = CurrSR & ~SR_IE;
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gGPR[REG_v0]._s64 = (s64)(CurrSR & SR_IE);
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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// This patch gives alot of speed!
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u32 Patch___osRestoreInt()
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{
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TEST_DISABLE_REG_FUNCS
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gCPUState.CPUControl[C0_SR]._u32 |= gGPR[REG_a0]._u32_0;
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// Check if interrupts are pending, fixes Doom 64
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// ToDo, check if interrupts are enabled? ERL/EXL, or call R4300_SetSR?
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if (gCPUState.CPUControl[C0_SR]._u32 & gCPUState.CPUControl[C0_CAUSE]._u32 & CAUSE_IPMASK)
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{
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gCPUState.AddJob( CPU_CHECK_INTERRUPTS );
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}
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch_osGetCount()
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{
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TEST_DISABLE_REG_FUNCS
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gGPR[REG_v0]._s64 = (s64)gCPUState.CPUControl[C0_COUNT]._u32;
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch___osGetCause()
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{
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TEST_DISABLE_REG_FUNCS
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gGPR[REG_v0]._s64 = (s64)gCPUState.CPUControl[C0_CAUSE]._u32;
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch___osSetCompare()
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{
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TEST_DISABLE_REG_FUNCS
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CPU_SetCompare( gGPR[REG_a0]._u32_0 );
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch___osSetSR()
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{
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TEST_DISABLE_REG_FUNCS
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R4300_SetSR(gGPR[REG_a0]._u32_0);
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//DBGConsole_Msg(0, "__osSetSR()");
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch___osGetSR()
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{
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TEST_DISABLE_REG_FUNCS
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gGPR[REG_v0]._s64 = (s64)gCPUState.CPUControl[C0_SR]._u32;
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//DBGConsole_Msg(0, "__osGetSR()");
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return PATCH_RET_JR_RA;
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}
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//*****************************************************************************
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//
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//*****************************************************************************
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u32 Patch___osSetFpcCsr()
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{
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TEST_DISABLE_REG_FUNCS
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gGPR[REG_v0]._s64 = (s64)gCPUState.FPUControl[31]._u32;
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gCPUState.FPUControl[31]._u32 = gGPR[REG_a0]._u32_0;
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DBGConsole_Msg(0, "__osSetFpcCsr()");
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#endif
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return PATCH_RET_JR_RA;
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}
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