mirror of
https://github.com/DaedalusX64/daedalus.git
synced 2025-04-02 10:21:48 -04:00
247 lines
No EOL
13 KiB
C++
247 lines
No EOL
13 KiB
C++
/*
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Copyright (C) 2020 MasterFeizz
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#pragma once
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#include "DynaRec/CodeGenerator.h"
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#include "AssemblyWriterARM.h"
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#include "DynarecTargetARM.h"
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#include "DynaRec/TraceRecorder.h"
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#include "N64RegisterCacheARM.h"
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#include <stack>
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// XXXX For GenerateCompare_S/D
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#define FLAG_SWAP 0x100
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#define FLAG_C_LT (0x41) // jne- le
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#define FLAG_C_LE (FLAG_SWAP|0x41) // je - ! gt
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#define FLAG_C_EQ (FLAG_SWAP|0x40) // je - ! eq
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typedef u32 (*ReadMemoryFunction)( u32 address );
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class CCodeGeneratorARM : public CCodeGenerator, public CAssemblyWriterARM
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{
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public:
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CCodeGeneratorARM( CAssemblyBuffer * p_primary, CAssemblyBuffer * p_secondary );
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virtual void Initialise( u32 entry_address, u32 exit_address, u32 * hit_counter, const void * p_base, const SRegisterUsageInfo & register_usage );
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void SetRegisterSpanList(const SRegisterUsageInfo& register_usage, bool loops_to_self);
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virtual void Finalise( ExceptionHandlerFn p_exception_handler_fn, const std::vector< CJumpLocation > & exception_handler_jumps, const std::vector< RegisterSnapshotHandle>& exception_handler_snapshots );
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virtual void UpdateRegisterCaching( u32 instruction_idx );
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virtual RegisterSnapshotHandle GetRegisterSnapshot();
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virtual CCodeLabel GetEntryPoint() const;
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virtual CCodeLabel GetCurrentLocation() const;
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virtual u32 GetCompiledCodeSize() const;
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virtual CJumpLocation GenerateExitCode( u32 exit_address, u32 jump_address, u32 num_instructions, CCodeLabel next_fragment );
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virtual void GenerateEretExitCode( u32 num_instructions, CIndirectExitMap * p_map );
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virtual void GenerateIndirectExitCode( u32 num_instructions, CIndirectExitMap * p_map );
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virtual void GenerateBranchHandler( CJumpLocation branch_handler_jump, RegisterSnapshotHandle snapshot );
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virtual CJumpLocation GenerateOpCode( const STraceEntry& ti, bool branch_delay_slot, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump);
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virtual CJumpLocation ExecuteNativeFunction( CCodeLabel speed_hack, bool check_return );
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private:
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void ExpireOldIntervals(u32 instruction_idx);
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void SpillAtInterval(const SRegisterSpan& live_span);
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void GetVar(EArmReg arm_reg, const u32* p_var);
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void SetVar( const u32 * p_var, u32 value );
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void SetVar(const u32* p_var, EArmReg reg);
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void SetFloatVar(const f32* p_var, EArmVfpReg reg);
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void GetFloatVar( EArmVfpReg dst_reg, const f32 * p_var );
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void SetDoubleVar(const f64* p_var, EArmVfpReg reg);
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void GetDoubleVar( EArmVfpReg dst_reg, const f64 * p_var );
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EArmReg GetRegisterNoLoad( EN64Reg n64_reg, u32 lo_hi_idx, EArmReg scratch_reg );
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EArmReg GetRegisterNoLoadLo( EN64Reg n64_reg, EArmReg scratch_reg ) { return GetRegisterNoLoad( n64_reg, 0, scratch_reg ); }
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EArmReg GetRegisterNoLoadHi( EN64Reg n64_reg, EArmReg scratch_reg ) { return GetRegisterNoLoad( n64_reg, 1, scratch_reg ); }
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EArmReg GetRegisterAndLoad( EN64Reg n64_reg, u32 lo_hi_idx, EArmReg scratch_reg );
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EArmReg GetRegisterAndLoadLo( EN64Reg n64_reg, EArmReg scratch_reg ) { return GetRegisterAndLoad( n64_reg, 0, scratch_reg ); }
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EArmReg GetRegisterAndLoadHi( EN64Reg n64_reg, EArmReg scratch_reg ) { return GetRegisterAndLoad( n64_reg, 1, scratch_reg ); }
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void GetRegisterValue(EArmReg arm_reg, EN64Reg n64_reg, u32 lo_hi_idx);
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void LoadRegister( EArmReg arm_reg, EN64Reg n64_reg, u32 lo_hi_idx );
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void LoadRegisterLo( EArmReg arm_reg, EN64Reg n64_reg ) { LoadRegister(arm_reg, n64_reg, 0); }
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void LoadRegisterHi( EArmReg arm_reg, EN64Reg n64_reg ) { LoadRegister(arm_reg, n64_reg, 1); }
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void PrepareCachedRegister(EN64Reg n64_reg, u32 lo_hi_idx);
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void PrepareCachedRegisterLo(EN64Reg n64_reg) { PrepareCachedRegister(n64_reg, 0); }
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void PrepareCachedRegisterHi(EN64Reg n64_reg) { PrepareCachedRegister(n64_reg, 1); }
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void FlushRegister(CN64RegisterCacheARM& cache, EN64Reg n64_reg, u32 lo_hi_idx, bool invalidate);
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void FlushAllRegisters(CN64RegisterCacheARM& cache, bool invalidate);
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void FlushAllFloatingPointRegisters( CN64RegisterCacheARM & cache, bool invalidate );
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void RestoreAllRegisters(CN64RegisterCacheARM& current_cache, CN64RegisterCacheARM& new_cache);
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void UpdateRegister(EN64Reg n64_reg, EArmReg arm_reg, bool options);
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EArmVfpReg GetFloatRegisterAndLoad( EN64FloatReg n64_reg );
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EArmVfpReg GetDoubleRegisterAndLoad( EN64FloatReg n64_reg );
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void UpdateFloatRegister( EN64FloatReg n64_reg );
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void UpdateDoubleRegister( EN64FloatReg n64_reg );
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const CN64RegisterCacheARM& GetRegisterCacheFromHandle(RegisterSnapshotHandle snapshot) const;
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void StoreRegister(EN64Reg n64_reg, u32 lo_hi_idx, EArmReg arm_reg);
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void StoreRegisterLo(EN64Reg n64_reg, EArmReg arm_reg) { StoreRegister(n64_reg, 0, arm_reg); }
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void StoreRegisterHi(EN64Reg n64_reg, EArmReg arm_reg) { StoreRegister(n64_reg, 1, arm_reg); }
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void SetRegister64(EN64Reg n64_reg, s32 lo_value, s32 hi_value);
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void SetRegister32s(EN64Reg n64_reg, s32 value);
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void SetRegister(EN64Reg n64_reg, u32 lo_hi_idx, u32 value);
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CJumpLocation GenerateBranchAlways( CCodeLabel target );
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CJumpLocation GenerateBranchIfSet( const u32 * p_var, CCodeLabel target );
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CJumpLocation GenerateBranchIfNotSet( const u32 * p_var, CCodeLabel target );
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CJumpLocation GenerateBranchIfEqual( const u32 * p_var, u32 value, CCodeLabel target );
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CJumpLocation GenerateBranchIfNotEqual( const u32 * p_var, u32 value, CCodeLabel target );
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CJumpLocation GenerateBranchIfNotEqual( EArmReg reg_a, u32 value, CCodeLabel target );
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void GenerateGenericR4300( OpCode op_code, CPU_Instruction p_instruction );
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void GenerateExceptionHander( ExceptionHandlerFn p_exception_handler_fn, const std::vector< CJumpLocation > & exception_handler_jumps, const std::vector< RegisterSnapshotHandle>& exception_handler_snapshots );
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bool mSpCachedInESI; // Is sp cached in ESI?
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u32 mSetSpPostUpdate; // Set Sp base counter after this update
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u32 mEntryAddress;
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CAssemblyBuffer * mpPrimary;
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CAssemblyBuffer * mpSecondary;
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RegisterSpanList mRegisterSpanList;
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// For register allocation
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RegisterSpanList mActiveIntervals;
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std::stack<EArmReg> mAvailableRegisters;
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CCodeLabel mLoopTop;
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bool mUseFixedRegisterAllocation;
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std::vector< CN64RegisterCacheARM > mRegisterSnapshots;
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CN64RegisterCacheARM mRegisterCache;
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bool mQuickLoad;
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bool mFloatCMPIsValid;
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bool mMultIsValid;
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private:
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bool GenerateCACHE( EN64Reg base, s16 offset, u32 cache_op );
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typedef u32 (*ReadMemoryFunction)( u32 address, u32 current_pc );
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typedef void (*WriteMemoryFunction)( u32 address, u32 value, u32 current_pc );
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void GenerateStore( u32 address, EArmReg arm_src, EN64Reg base, s16 offset, u8 twiddle, u8 bits, WriteMemoryFunction p_write_memory );
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bool GenerateSW(u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateSWC1( u32 address, bool branch_delay_slot, u32 ft, EN64Reg base, s16 offset );
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bool GenerateSDC1( u32 address, bool branch_delay_slot, u32 ft, EN64Reg base, s16 offset );
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bool GenerateSH( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateSD( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateSB( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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void GenerateLoad( u32 address, EArmReg arm_dest, EN64Reg base, s16 offset, u8 twiddle, u8 bits, bool is_signed, ReadMemoryFunction p_read_memory );
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bool GenerateLW( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateLD( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateLB( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateLBU( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateLH( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateLHU( u32 address, bool branch_delay_slot, EN64Reg rt, EN64Reg base, s16 offset );
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bool GenerateLWC1( u32 address, bool branch_delay_slot, u32 ft, EN64Reg base, s16 offset );
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bool GenerateLDC1( u32 address, bool branch_delay_slot, u32 ft, EN64Reg base, s16 offset );
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void GenerateLUI( EN64Reg rt, s16 immediate );
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void GenerateADDIU( EN64Reg rt, EN64Reg rs, s16 immediate );
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void GenerateANDI( EN64Reg rt, EN64Reg rs, u16 immediate );
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void GenerateORI( EN64Reg rt, EN64Reg rs, u16 immediate );
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void GenerateXORI( EN64Reg rt, EN64Reg rs, u16 immediate );
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void GenerateSLTI( EN64Reg rt, EN64Reg rs, s16 immediate, bool is_unsigned );
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void GenerateDADDIU( EN64Reg rt, EN64Reg rs, s16 immediate );
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void GenerateDADDU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateDSUBU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateJAL( u32 address );
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void GenerateJALR( EN64Reg rs, EN64Reg rd, u32 address, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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//Special Op
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void GenerateMFC0( EN64Reg rt, u32 fs );
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void GenerateMFC1( EN64Reg rt, u32 fs );
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void GenerateMTC1( u32 fs, EN64Reg rt );
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void GenerateCFC1( EN64Reg rt, u32 fs );
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void GenerateCTC1( u32 fs, EN64Reg rt );
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void GenerateSLL( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateSRL( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateSRA( EN64Reg rd, EN64Reg rt, u32 sa );
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void GenerateSLLV( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSRLV( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSRAV( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateOR( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateAND( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateXOR( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateNOR( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateJR( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateADDU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateSUBU( EN64Reg rd, EN64Reg rs, EN64Reg rt );
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void GenerateMULT( EN64Reg rs, EN64Reg rt, bool is_unsigned );
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void GenerateDIV( EN64Reg rs, EN64Reg rt );
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void GenerateDIVU( EN64Reg rs, EN64Reg rt );
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void GenerateMFLO( EN64Reg rd );
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void GenerateMFHI( EN64Reg rd );
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void GenerateMTLO( EN64Reg rs );
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void GenerateMTHI( EN64Reg rs );
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void GenerateSLT( EN64Reg rd, EN64Reg rs, EN64Reg rt , bool is_unsigned );
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//Branch
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void GenerateBEQ( EN64Reg rs, EN64Reg rt, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBNE( EN64Reg rs, EN64Reg rt, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBLEZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBGEZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBLTZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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void GenerateBGTZ( EN64Reg rs, const SBranchDetails * p_branch, CJumpLocation * p_branch_jump );
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// CoPro1
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void GenerateADD_S( u32 fd, u32 fs, u32 ft );
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void GenerateSUB_S( u32 fd, u32 fs, u32 ft );
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void GenerateMUL_S( u32 fd, u32 fs, u32 ft );
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void GenerateDIV_S( u32 fd, u32 fs, u32 ft );
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void GenerateSQRT_S( u32 fd, u32 fs );
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void GenerateABS_S( u32 fd, u32 fs );
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void GenerateMOV_S( u32 fd, u32 fs );
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void GenerateNEG_S( u32 fd, u32 fs );
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void GenerateTRUNC_W_S( u32 fd, u32 fs );
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void GenerateCVT_D_S( u32 fd, u32 fs );
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void GenerateCMP_S( u32 fs, u32 ft, EArmCond cond, u8 E );
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void GenerateADD_D( u32 fd, u32 fs, u32 ft );
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void GenerateSUB_D( u32 fd, u32 fs, u32 ft );
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void GenerateMUL_D( u32 fd, u32 fs, u32 ft );
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void GenerateDIV_D( u32 fd, u32 fs, u32 ft );
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void GenerateSQRT_D( u32 fd, u32 fs );
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void GenerateABS_D( u32 fd, u32 fs );
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void GenerateMOV_D( u32 fd, u32 fs );
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void GenerateNEG_D( u32 fd, u32 fs );
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void GenerateTRUNC_W_D( u32 fd, u32 fs );
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void GenerateCVT_S_D( u32 fd, u32 fs );
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void GenerateCMP_D( u32 fs, u32 ft, EArmCond cond, u8 E );
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}; |