mirror of
https://github.com/DaedalusX64/daedalus.git
synced 2025-04-02 10:21:48 -04:00
274 lines
6.7 KiB
C
274 lines
6.7 KiB
C
/*
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Copyright (C) 2001 StrmnNrmn
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef OSHLE_ULTRA_R4300_H_
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#define OSHLE_ULTRA_R4300_H_
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#define KUBASE 0
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#define KUSIZE 0x80000000
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#define K0BASE 0x80000000
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#define K0SIZE 0x20000000
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#define K1BASE 0xA0000000
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#define K1SIZE 0x20000000
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#define K2BASE 0xC0000000
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#define K2SIZE 0x20000000
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#define SIZE_EXCVEC 0x80
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#define UT_VEC K0BASE
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#define R_VEC (K1BASE+0x1fc00000)
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#define XUT_VEC (K0BASE+0x80)
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#define ECC_VEC (K0BASE+0x100)
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#define E_VEC 0x80000180
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#define K0_TO_K1(x) ((u32)(x)|0xA0000000)
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#define K1_TO_K0(x) ((u32)(x)&0x9FFFFFFF)
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#define K0_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF)
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#define K1_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF)
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#define KDM_TO_PHYS(x) ((u32)(x)&0x1FFFFFFF)
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#define PHYS_TO_K0(x) ((u32)(x)|0x80000000)
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#define PHYS_TO_K1(x) ((u32)(x)|0xA0000000)
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// Optimized version of IS_KSEG0/1
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#define IS_K0K1(x) (((x ^ K0BASE) & K2BASE) == 0)
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#define IS_KSEG0(x) ((u32)(x) >= K0BASE && (u32)(x) < K1BASE)
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#define IS_KSEG1(x) ((u32)(x) >= K1BASE && (u32)(x) < K2BASE)
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#define IS_KSEGDM(x) ((u32)(x) >= K0BASE && (u32)(x) < K2BASE)
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#define IS_KSEG2(x) ((u32)(x) >= K2BASE && (u32)(x) < KPTE_SHDUBASE)
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#define IS_KPTESEG(x) ((u32)(x) >= KPTE_SHDUBASE)
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#define IS_KUSEG(x) ((u32)(x) < K0BASE)
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#define NTLBENTRIES 31
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#define TLBHI_VPN2MASK 0xffffe000
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#define TLBHI_VPN2SHIFT 13
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#define TLBHI_PIDMASK 0xff
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#define TLBHI_PIDSHIFT 0
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#define TLBHI_NPID 255
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#define TLBLO_PFNMASK 0x3fffffc0
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#define TLBLO_PFNSHIFT 6
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#define TLBLO_CACHMASK 0x38
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#define TLBLO_CACHSHIFT 3
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#define TLBLO_UNCACHED 0x10
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#define TLBLO_NONCOHRNT 0x18
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#define TLBLO_EXLWR 0x28
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#define TLBLO_D 0x4
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#define TLBLO_V 0x2
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#define TLBLO_G 0x1
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#define TLBINX_PROBE 0x80000000
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#define TLBINX_INXMASK 0x3f
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#define TLBINX_INXSHIFT 0
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#define TLBRAND_RANDMASK 0x3f
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#define TLBRAND_RANDSHIFT 0
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#define TLBWIRED_WIREDMASK 0x3f
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#define TLBCTXT_BASEMASK 0xff800000
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#define TLBCTXT_BASESHIFT 23
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#define TLBCTXT_BASEBITS 9
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#define TLBCTXT_VPNMASK 0x7ffff0
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#define TLBCTXT_VPNSHIFT 4
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#define TLBPGMASK_4K 0x0
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#define TLBPGMASK_16K 0x6000
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#define TLBPGMASK_64K 0x1e000
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#define TLBPGMASK_256K 0x0007e000
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#define TLBPGMASK_1M 0x001fe000
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#define TLBPGMASK_4M 0x007fe000
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#define TLBPGMASK_16M 0x01ffe000
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#define SR_CUMASK 0xf0000000
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#define SR_CU3 0x80000000
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#define SR_CU2 0x40000000
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#define SR_CU1 0x20000000
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#define SR_CU0 0x10000000
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#define SR_RP 0x08000000
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#define SR_FR 0x04000000
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#define SR_RE 0x02000000
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#define SR_ITS 0x01000000
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#define SR_BEV 0x00400000
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#define SR_TS 0x00200000
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#define SR_SR 0x00100000
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#define SR_CH 0x00040000
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#define SR_CE 0x00020000
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#define SR_DE 0x00010000
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#define SR_IMASK 0x0000ff00
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#define SR_IMASK8 0x00000000
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#define SR_IMASK7 0x00008000
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#define SR_IMASK6 0x0000c000
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#define SR_IMASK5 0x0000e000
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#define SR_IMASK4 0x0000f000
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#define SR_IMASK3 0x0000f800
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#define SR_IMASK2 0x0000fc00
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#define SR_IMASK1 0x0000fe00
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#define SR_IMASK0 0x0000ff00
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#define SR_IBIT8 0x00008000
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#define SR_IBIT7 0x00004000
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#define SR_IBIT6 0x00002000
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#define SR_IBIT5 0x00001000
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#define SR_IBIT4 0x00000800
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#define SR_IBIT3 0x00000400
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#define SR_IBIT2 0x00000200
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#define SR_IBIT1 0x00000100
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#define SR_IMASKSHIFT 8
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#define SR_KX 0x00000080
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#define SR_SX 0x00000040
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#define SR_UX 0x00000020
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#define SR_KSU_MASK 0x00000018
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#define SR_KSU_USR 0x00000010
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#define SR_KSU_SUP 0x00000008
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#define SR_KSU_KER 0x00000000
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#define SR_ERL 0x00000004
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#define SR_EXL 0x00000002
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#define SR_IE 0x00000001
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#define CAUSE_BD 0x80000000
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#define CAUSE_CEMASK 0x30000000
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#define CAUSE_CESHIFT 28
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#define CAUSE_IP8 0x00008000
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#define CAUSE_IP7 0x00004000
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#define CAUSE_IP6 0x00002000
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#define CAUSE_IP5 0x00001000
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#define CAUSE_IP4 0x00000800
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#define CAUSE_IP3 0x00000400
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#define CAUSE_SW2 0x00000200
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#define CAUSE_SW1 0x00000100
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#define CAUSE_IPMASK 0x0000FF00
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#define CAUSE_IPSHIFT 8
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#define NOT_CAUSE_EXCMASK 0xFFFFFF83
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#define CAUSE_EXCMASK 0x0000007C
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#define CAUSE_EXCSHIFT 2
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#define EXC_INT 0
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#define EXC_MOD 4
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#define EXC_RMISS 8
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#define EXC_WMISS 12
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#define EXC_RADE 16
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#define EXC_WADE 20
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#define EXC_IBE 24
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#define EXC_DBE 28
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#define EXC_SYSCALL 32
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#define EXC_BREAK 36
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#define EXC_II 40
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#define EXC_CPU 44
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#define EXC_OV 48
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#define EXC_TRAP 52
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#define EXC_VCEI 56
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#define EXC_FPE 60
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#define EXC_WATCH 92
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#define EXC_VCED 124
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#define REG_r0 0x00
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#define REG_at 0x01
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#define REG_v0 0x02
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#define REG_v1 0x03
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#define REG_a0 0x04
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#define REG_a1 0x05
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#define REG_a2 0x06
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#define REG_a3 0x07
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#define REG_t0 0x08
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#define REG_t1 0x09
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#define REG_t2 0x0a
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#define REG_t3 0x0b
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#define REG_t4 0x0c
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#define REG_t5 0x0d
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#define REG_t6 0x0e
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#define REG_t7 0x0f
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#define REG_s0 0x10
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#define REG_s1 0x11
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#define REG_s2 0x12
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#define REG_s3 0x13
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#define REG_s4 0x14
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#define REG_s5 0x15
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#define REG_s6 0x16
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#define REG_s7 0x17
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#define REG_t8 0x18
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#define REG_t9 0x19
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#define REG_k0 0x1a
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#define REG_k1 0x1b
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#define REG_gp 0x1c
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#define REG_sp 0x1d
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#define REG_s8 0x1e
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#define REG_ra 0x1f
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#define C0_INX 0
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#define C0_RAND 1
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#define C0_ENTRYLO0 2
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#define C0_ENTRYLO1 3
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#define C0_CONTEXT 4
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#define C0_PAGEMASK 5
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#define C0_WIRED 6
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#define C0_BADVADDR 8
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#define C0_COUNT 9
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#define C0_ENTRYHI 10
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#define C0_SR 12
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#define C0_CAUSE 13
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#define C0_EPC 14
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#define C0_PRID 15
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#define C0_COMPARE 11
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#define C0_CONFIG 16
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#define C0_LLADDR 17
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#define C0_WATCHLO 18
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#define C0_WATCHHI 19
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#define C0_ECC 26
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#define C0_CACHE_ERR 27
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#define C0_TAGLO 28
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#define C0_TAGHI 29
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#define C0_ERROR_EPC 30
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#define FPCSR_FS 0x01000000
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#define FPCSR_C 0x00800000
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#define FPCSR_CE 0x00020000
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#define FPCSR_CV 0x00010000
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#define FPCSR_CZ 0x00008000
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#define FPCSR_CO 0x00004000
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#define FPCSR_CU 0x00002000
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#define FPCSR_CI 0x00001000
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#define FPCSR_EV 0x00000800
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#define FPCSR_EZ 0x00000400
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#define FPCSR_EO 0x00000200
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#define FPCSR_EU 0x00000100
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#define FPCSR_EI 0x00000080
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#define FPCSR_FV 0x00000040
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#define FPCSR_FZ 0x00000020
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#define FPCSR_FO 0x00000010
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#define FPCSR_FU 0x00000008
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#define FPCSR_FI 0x00000004
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#define FPCSR_RM_MASK 0x00000003
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#define FPCSR_RM_RN 0x00000000
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#define FPCSR_RM_RZ 0x00000001
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#define FPCSR_RM_RP 0x00000002
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#define FPCSR_RM_RM 0x00000003
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#endif // OSHLE_ULTRA_R4300_H_
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