mirror of
https://github.com/DaedalusX64/daedalus.git
synced 2025-04-02 10:21:48 -04:00
229 lines
6.6 KiB
C++
229 lines
6.6 KiB
C++
/*
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Copyright (C) 2001 StrmnNrmn
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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static const void * ReadInvalid( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY, "Illegal Memory Access - Tried to Read From 0x%08x (PC: 0x%08x)", address, gCPUState.CurrentPC );
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DBGConsole_Msg(0, "Illegal Memory Access - Tried to Read From 0x%08x (PC: 0x%08x)", address, gCPUState.CurrentPC);
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#endif
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u8* temp = (u8 *)g_pMemoryBuffers[MEM_UNUSED];
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// 0xa5000508 is 64DD region.. set -1 fixes F-Zero U
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*(u32*)(temp) = (address == 0xa5000508) ? ~0 : 0;
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return temp;
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}
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static const void * ReadMapped( u32 address )
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{
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bool missing;
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#ifdef DAEDALUS_PROFILE_EXECUTION
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gTLBReadHit++;
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#endif
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u32 physical_addr = TLBEntry::Translate(address, missing);
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if (physical_addr != 0)
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{
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return g_pu8RamBase + (physical_addr & 0x007FFFFF);
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}
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else
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{
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R4300_Exception_TLB(address, EXC_RMISS, missing ? UT_VEC : E_VEC);
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return g_pMemoryBuffers[MEM_UNUSED];
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}
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}
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static const void * Read_8000_807F( u32 address )
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{
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// Note: Mask is slighty different when EPAK isn't used 0x003FFFFF
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return (u8 *)g_pMemoryBuffers[MEM_RD_RAM] + (address & 0x007FFFFF);
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}
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// 0x83F0 0000 to 0x83FF FFFF RDRAM registers
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static const void * Read_83F0_83F0( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_RDRAM_REG, "Reading from MEM_RD_REG: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_RD_REG0] + (address & 0xFF);
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}
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// 0x0400 0000 to 0x0400 FFFF SP registers
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static const void * Read_8400_8400( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_SP_IMEM, "Reading from SP_MEM: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_SP_MEM] + (address & 0x1FFF);
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}
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static const void * Read_8404_8404( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_SP_REG, "Reading from SP_REG: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_SP_REG] + (address & 0xFF);
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}
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static const void * Read_8408_8408( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_SP_REG, "Reading from SP_PC_REG: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_SP_PC_REG] + (address & 0xFF);
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}
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// 0x0410 0000 to 0x041F FFFF DP Command Registers
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static const void * Read_8410_841F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_DP, "Reading from DP_COMMAND_REG: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_DPC_REG] + (address & 0xFF);
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}
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// 0x0420 0000 to 0x042F FFFF DP Span Registers
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static const void * Read_8420_842F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DBGConsole_Msg( 0, "Read from DP Span Registers is unhandled (0x%08x, PC: 0x%08x)", address, gCPUState.CurrentPC );
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#endif
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return ReadInvalid(address);
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}
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// 0x0430 0000 to 0x043F FFFF MIPS Interface (MI) Registers
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static const void * Read_8430_843F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_MI, "Reading from MI Registers: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_MI_REG] + (address & 0xFF);
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}
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// 0x0440 0000 to 0x044F FFFF Video Interface (VI) Registers
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static const void * Read_8440_844F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_VI, "Reading from MEM_VI_REG: 0x%08x", address );
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#endif
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u32 offset = address & 0xFF;
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u8* temp = (u8 *)g_pMemoryBuffers[MEM_VI_REG] + offset;
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if (offset == 0x10) // VI_CURRENT_REG
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{
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//u64 count_to_vbl = (VID_CLOCK-1) - (g_qwNextVBL - gCPUState.CPUControl[C0_COUNT]);
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//vi_pos = (u32)((count_to_vbl*512)/VID_CLOCK);
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u32 vi_pos = Memory_VI_GetRegister(VI_CURRENT_REG);
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vi_pos = (vi_pos + 2) % 512;
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//DBGConsole_Msg(0, "Reading vi pos: %d", vi_pos);
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*(u32*)temp = vi_pos;
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}
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return temp;
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}
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// 0x0450 0000 to 0x045F FFFF Audio Interface (AI) Registers
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static const void * Read_8450_845F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_AI, "Reading from AI Registers: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_AI_REG] + (address & 0xFF);
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}
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// 0x0460 0000 to 0x046F FFFF Peripheral Interface (PI) Registers
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static const void * Read_8460_846F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_PI, "Reading from MEM_PI_REG: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_PI_REG] + (address & 0xFF);
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}
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// 0x0470 0000 to 0x047F FFFF RDRAM Interface (RI) Registers
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static const void * Read_8470_847F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_RI, "Reading from MEM_RI_REG: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_RI_REG] + (address & 0xFF);
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}
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// 0x0480 0000 to 0x048F FFFF Serial Interface (SI) Registers
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static const void * Read_8480_848F( u32 address )
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_SI, "Reading from MEM_SI_REG: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_SI_REG] + (address & 0xFF);
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}
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static const void * ReadFlashRam( u32 address )
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{
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if (g_ROM.settings.SaveType == SAVE_TYPE_FLASH)
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{
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if ((address&0x1FFFFFFF) == FLASHRAM_READ_ADDR)
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{
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return (u8 *)&FlashStatus[0];
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}
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}
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else
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{
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DAEDALUS_ERROR("ROM is accessing a Flashram region, but save type is not correct");
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}
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DBGConsole_Msg(0, "[GRead from FlashRam (0x%08x) is invalid", address);
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return g_pMemoryBuffers[MEM_UNUSED];
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}
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static const void * ReadROM( u32 address )
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{
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void * p_mem = RomBuffer::GetAddressRaw( address & 0x03FFFFFF );
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if (p_mem != nullptr)
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{
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return p_mem;
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}
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DBGConsole_Msg(0, "[GRead from Rom (0x%08x) is invalid", address);
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return g_pMemoryBuffers[MEM_UNUSED];
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}
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// 0x1FC0 0000 to 0x1FC0 07BF PIF Boot ROM (Ignored)
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// 0x1FC0 07C0 to 0x1FC0 07FF PIF RAM
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static const void * Read_9FC0_9FCF( u32 address )
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{
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u32 offset = address & 0x0FFF;
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u32 pif_ram_offset = address & 0x3F;
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// Reading PIF ROM or outside PIF RAM
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if ((offset < 0x7C0) || (offset > 0x7FF))
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{
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DBGConsole_Msg(0, "[GRead from PIF (0x%08x) is invalid", address);
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#endif
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return g_pMemoryBuffers[MEM_UNUSED];
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}
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#ifdef DAEDALUS_DEBUG_CONSOLE
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DPF( DEBUG_MEMORY_PIF, "Reading from MEM_PIF: 0x%08x", address );
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#endif
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return (u8 *)g_pMemoryBuffers[MEM_PIF_RAM] + pif_ram_offset;
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}
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