mirror of
https://github.com/DaedalusX64/daedalus.git
synced 2025-04-02 10:21:48 -04:00
329 lines
11 KiB
C++
329 lines
11 KiB
C++
/*
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Copyright (C) 2001 StrmnNrmn
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#pragma once
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#ifndef CORE_MEMORY_H_
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#define CORE_MEMORY_H_
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#include "Ultra/ultra_rcp.h"
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#include "System/AtomicPrimitives.h"
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#include "System/Endian.h"
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#include <array>
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enum MEMBANKTYPE
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{
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MEM_UNUSED = 0, // Simplifies code so that we don't have to check for illegal memory accesses
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MEM_RD_RAM, // 8 or 4 Mb (4/8*1024*1024)
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MEM_SP_MEM, // 0x2000
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MEM_PIF_RAM, // 0x40
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MEM_RD_REG0, // 0x30 // This has changed - used to be 1Mb
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MEM_SP_REG, // 0x20
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MEM_SP_PC_REG, // 0x10 // SP_PC_REG + SP_IBITS_REG
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MEM_DPC_REG, // 0x20
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MEM_MI_REG, // 0x10
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MEM_VI_REG, // 0x38
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MEM_AI_REG, // 0x18
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MEM_PI_REG, // 0x34
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MEM_RI_REG, // 0x20
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MEM_SI_REG, // 0x1C
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MEM_SAVE, // 0x20000 128KBytes EEPROM (512 bytes), 4X EEPROM (2Kbytes), SRAM (32Kbytes), FlashRAM (128Kbytes)
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MEM_MEMPACK, // 0x20000 MEMPack 32Kbytes * 4 = 128KBytes
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NUM_MEM_BUFFERS
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};
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static const u32 MEMORY_4_MEG( 4*1024*1024 );
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static const u32 MEMORY_8_MEG( 8*1024*1024 );
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#define MAX_RAM_ADDRESS MEMORY_8_MEG
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using mReadFunction = const void * (*)(u32 address);
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using mWriteFunction = void(*)(u32 address, u32 value);
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struct MemFuncWrite
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{
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u8 *pWrite;
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mWriteFunction WriteFunc;
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};
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struct MemFuncRead
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{
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u8 *pRead;
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mReadFunction ReadFunc;
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};
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extern u32 gRamSize;
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#ifdef DAEDALUS_PROFILE_EXECUTION
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extern u32 gTLBReadHit;
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extern u32 gTLBWriteHit;
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#endif
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extern void * g_pMemoryBuffers[NUM_MEM_BUFFERS];
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extern const u32 MemoryRegionSizes[NUM_MEM_BUFFERS];
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bool Memory_Init();
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void Memory_Fini();
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bool Memory_Reset();
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void Memory_Cleanup();
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using MemFastFunction = void * (*)(u32 address);
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using MemWriteValueFunction = void (*)(u32 address, u32 value);
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#ifndef DAEDALUS_SILENT
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using InternalMemFastFunction = bool (*)(u32 address, void ** p_translated);
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#endif
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extern MemFuncRead g_MemoryLookupTableRead[0x4000];
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extern MemFuncWrite g_MemoryLookupTableWrite[0x4000];
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// Fast memory access
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inline const void* ReadAddress( u32 address )
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{
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const MemFuncRead & m( g_MemoryLookupTableRead[ address >> 18 ] );
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// Access through pointer with no function calls at all (Fast)
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if( m.pRead )
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return (void*)( m.pRead + address );
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// Need to go through the HW access handlers or TLB (Slow)
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return m.ReadFunc( address );
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}
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inline void WriteAddress( u32 address, u32 value )
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{
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const MemFuncWrite & m( g_MemoryLookupTableWrite[ address >> 18 ] );
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// Access through pointer with no function calls at all (Fast)
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if( m.pWrite )
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{
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*(u32*)( m.pWrite + address ) = value;
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return;
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}
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// Need to go through the HW access handlers or TLB (Slow)
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m.WriteFunc( address, value );
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}
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#ifndef DAEDALUS_SILENT
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bool Memory_GetInternalReadAddress(u32 address, void ** p_translated);
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#endif
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//////////////////////////////////////////////////////////////
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// Quick Read/Write methods that require a base returned by
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// ReadAddress or Memory_GetInternalReadAddress etc
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inline u64 QuickRead64Bits( u8 *p_base, u32 offset )
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{
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u64 data = *(u64 *)(p_base + offset);
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return (data>>32) + (data<<32);
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}
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inline u32 QuickRead32Bits( u8 *p_base, u32 offset )
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{
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return *(u32 *)(p_base + offset);
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}
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inline u16 QuickRead16Bits( u8 *p_base, u32 offset )
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{
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return *(u16 *)((uintptr_t)(p_base + offset) ^ U16_TWIDDLE);
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}
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inline void QuickWrite16Bits( u8 *p_base, u32 offset, u16 value)
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{
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*(u16 *)((uintptr_t)(p_base + offset) ^ U16_TWIDDLE) = value;
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}
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inline void QuickWrite64Bits( u8 *p_base, u32 offset, u64 value )
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{
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u64 data = (value>>32) + (value<<32);
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*(u64 *)(p_base + offset) = data;
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}
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inline void QuickWrite32Bits( u8 *p_base, u32 offset, u32 value )
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{
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*(u32 *)(p_base + offset) = value;
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}
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inline void QuickWrite32Bits( u8 *p_base, u32 value )
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{
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*(u32 *)(p_base) = value;
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}
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// Useful defines for making code look nicer:
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#define g_pu8RamBase ((u8*)g_pMemoryBuffers[MEM_RD_RAM])
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#define g_ps8RamBase ((s8*)g_pMemoryBuffers[MEM_RD_RAM])
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#define g_pu16RamBase ((u16*)g_pMemoryBuffers[MEM_RD_RAM])
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#define g_pu32RamBase ((u32*)g_pMemoryBuffers[MEM_RD_RAM])
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#define g_pu8SpMemBase ((u8*)g_pMemoryBuffers[MEM_SP_MEM])
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#define g_ps8SpMemBase ((s8*)g_pMemoryBuffers[MEM_SP_MEM])
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#define g_pu16SpMemBase ((u16*)g_pMemoryBuffers[MEM_SP_MEM])
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#define g_pu32SpMemBase ((u32*)g_pMemoryBuffers[MEM_SP_MEM])
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#define g_pu8SpDmemBase ((u8*)g_pMemoryBuffers[MEM_SP_MEM] + SP_DMA_DMEM)
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#define g_pu8SpImemBase ((u8*)g_pMemoryBuffers[MEM_SP_MEM] + SP_DMA_IMEM)
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#define MEMORY_SIZE_RDRAM 0x400000
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#define MEMORY_SIZE_EXRDRAM 0x400000
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#define MEMORY_SIZE_RDRAM_DEFAULT MEMORY_SIZE_RDRAM + MEMORY_SIZE_EXRDRAM
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#define MEMORY_SIZE_RAMREGS0 0x30
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#define MEMORY_SIZE_RAMREGS4 0x30
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#define MEMORY_SIZE_RAMREGS8 0x30
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#define MEMORY_SIZE_SPMEM 0x2000
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#define MEMORY_SIZE_SPREG_1 0x24
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#define MEMORY_SIZE_SPREG_2 0x8
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#define MEMORY_SIZE_DPC 0x20
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#define MEMORY_SIZE_DPS 0x10
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#define MEMORY_SIZE_MI 0x10
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#define MEMORY_SIZE_VI 0x50
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#define MEMORY_SIZE_AI 0x18
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#define MEMORY_SIZE_PI 0x4C
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#define MEMORY_SIZE_RI 0x20
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#define MEMORY_SIZE_SI 0x1C
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#define MEMORY_SIZE_C2A1 0x8000
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#define MEMORY_SIZE_C1A1 0x8000
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#define MEMORY_SIZE_C2A2 0x20000
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#define MEMORY_SIZE_GIO_REG 0x804
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#define MEMORY_SIZE_C1A3 0x8000
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#define MEMORY_SIZE_PIF 0x800
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#define MEMORY_SIZE_DUMMY 0x10000
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#define MEMORY_START_RDRAM 0x00000000
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#define MEMORY_START_EXRDRAM 0x00400000
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#define MEMORY_START_RAMREGS0 0x03F00000
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#define MEMORY_START_RAMREGS4 0x03F04000
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#define MEMORY_START_RAMREGS8 0x03F80000
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#define MEMORY_START_SPMEM 0x04000000
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#define MEMORY_START_SPREG_1 0x04040000
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#define MEMORY_START_SPREG_2 0x04080000
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#define MEMORY_START_DPC 0x04100000
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#define MEMORY_START_DPS 0x04200000
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#define MEMORY_START_MI 0x04300000
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#define MEMORY_START_VI 0x04400000
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#define MEMORY_START_AI 0x04500000
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#define MEMORY_START_PI 0x04600000
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#define MEMORY_START_RI 0x04700000
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#define MEMORY_START_SI 0x04800000
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#define MEMORY_START_C2A1 0x05000000
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#define MEMORY_START_C1A1 0x06000000
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#define MEMORY_START_C2A2 0x08000000
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#define MEMORY_START_ROM_IMAGE 0x10000000
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#define MEMORY_START_GIO 0x18000000
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#define MEMORY_START_PIF 0x1FC00000
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#define MEMORY_START_C1A3 0x1FD00000
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#define MEMORY_START_DUMMY 0x1FFF0000
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#define FLASHRAM_READ_ADDR 0x08000000
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#define FLASHRAM_WRITE_ADDR 0x08010000
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extern u8 * g_pu8RamBase_8000;
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//extern u8 * g_pu8RamBase_A000;
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#ifdef DAEDALUS_ENDIAN_BIG
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inline u64 Read64Bits( u32 address ) { return *(u64 *)ReadAddress( address ); }
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inline u32 Read32Bits( u32 address ) { return *(u32 *)ReadAddress( address ); }
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inline u16 Read16Bits( u32 address ) { return *(u16 *)ReadAddress( address ); }
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inline u8 Read8Bits( u32 address ) { return *(u8 *)ReadAddress( address ); }
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inline void Write64Bits( u32 address, u64 data ) { *(u64 *)ReadAddress( address ) = data; }
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inline void Write32Bits( u32 address, u32 data ) { WriteAddress(address, data); }
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inline void Write16Bits( u32 address, u16 data ) { *(u16 *)ReadAddress(address) = data; }
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inline void Write8Bits( u32 address, u8 data ) { *(u8 *)ReadAddress(address) = data;}
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#elif( DAEDALUS_ENDIAN_LITTLE)
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inline u64 Read64Bits( u32 address ) { u64 data = *(u64 *)ReadAddress( address ); data = (data>>32) + (data<<32); return data; }
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inline u32 Read32Bits( u32 address ) { return *(u32 *)ReadAddress( address ); }
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inline u16 Read16Bits( u32 address ) { return *(u16 *)ReadAddress( address ^ U16_TWIDDLE ); }
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inline u8 Read8Bits( u32 address ) { return *(u8 *)ReadAddress( address ^ U8_TWIDDLE ); }
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inline void Write64Bits( u32 address, u64 data ) { *(u64 *)ReadAddress( address ) = (data>>32) + (data<<32); }
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inline void Write32Bits( u32 address, u32 data ) { WriteAddress(address, data); }
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inline void Write16Bits( u32 address, u16 data ) { *(u16 *)ReadAddress(address ^ U16_TWIDDLE) = data; }
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inline void Write8Bits( u32 address, u8 data ) { *(u8 *)ReadAddress(address ^ U8_TWIDDLE) = data;}
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#else
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#error No DAEDALUS_ENDIAN_MODE specified
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#endif
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//inline void Write64Bits_NoSwizzle( u32 address, u64 data ){ *(u64 *)WriteAddress( address ) = (data>>32) + (data<<32); }
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inline void Write32Bits_NoSwizzle( u32 address, u32 data ) { WriteAddress(address, data); }
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inline void Write16Bits_NoSwizzle( u32 address, u16 data ) { *(u16 *)ReadAddress(address) = data; }
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inline void Write8Bits_NoSwizzle( u32 address, u8 data ) { *(u8 *)ReadAddress(address) = data;}
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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// Register Macros //
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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#define REGISTER_FUNCTIONS( set, base_reg, memory_buffer ) \
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inline void Memory_##set##_SetRegister( u32 reg, u32 value ) \
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{ \
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((u32 *)g_pMemoryBuffers[memory_buffer])[ (reg - base_reg) / 4 ] = value; \
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} \
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\
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inline u32 Memory_##set##_GetRegister( u32 reg ) \
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{ \
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return ((u32 *)g_pMemoryBuffers[memory_buffer])[ (reg - base_reg) / 4 ]; \
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} \
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\
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inline u32 Memory_##set##_SetRegisterBits( u32 reg, u32 and_bits, u32 or_bits ) \
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{ \
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u32 * p( &((u32 *)g_pMemoryBuffers[memory_buffer])[ (reg - base_reg) / 4 ] ); \
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return AtomicBitSet( p, and_bits, or_bits ); \
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} \
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\
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inline u32 Memory_##set##_SetRegisterBits( u32 reg, u32 value ) \
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{ \
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u32 * p( &((u32 *)g_pMemoryBuffers[memory_buffer])[ (reg - base_reg) / 4 ] ); \
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return AtomicBitSet( p, 0xffffffff, value ); \
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} \
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\
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inline u32 Memory_##set##_ClrRegisterBits( u32 reg, u32 value ) \
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{ \
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u32 * p( &((u32 *)g_pMemoryBuffers[memory_buffer])[ (reg - base_reg) / 4 ] ); \
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return AtomicBitSet( p, ~value, 0 ); \
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} \
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\
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inline u32 * set##_REG_ADDRESS( u32 reg ) \
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{ \
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return &((u32 *)g_pMemoryBuffers[memory_buffer])[(reg - base_reg) / 4]; \
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}
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REGISTER_FUNCTIONS( MI, MI_BASE_REG, MEM_MI_REG )
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REGISTER_FUNCTIONS( SP, SP_BASE_REG, MEM_SP_REG )
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REGISTER_FUNCTIONS( PC, SP_PC_REG, MEM_SP_PC_REG )
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REGISTER_FUNCTIONS( AI, AI_BASE_REG, MEM_AI_REG )
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REGISTER_FUNCTIONS( VI, VI_BASE_REG, MEM_VI_REG )
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REGISTER_FUNCTIONS( SI, SI_BASE_REG, MEM_SI_REG )
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REGISTER_FUNCTIONS( PI, PI_BASE_REG, MEM_PI_REG )
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REGISTER_FUNCTIONS( DPC, DPC_BASE_REG, MEM_DPC_REG )
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#undef REGISTER_FUNCTIONS
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#endif // CORE_MEMORY_H_
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