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174 commits

Author SHA1 Message Date
Corn
81cf7272a8 [!] reverted and corrected logic in previous rev 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@728 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-14 12:54:57 +00:00
salvy
42efe81f35 [!] Improved previous optimization when register is known and is zero (they are basically a NOP), also added another opt for AND 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@727 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-14 10:53:40 +00:00
salvy
d50d7c572c [!] Improve detection when hi reg isn't needed in GenerateOR 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@726 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-14 01:42:38 +00:00
Corn
2040fa0d98 [!] Optimizing AND/OR/XOR for when one of the hi regs are known and =0, small speedup 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@725 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-13 19:51:00 +00:00
Corn
1ea759305e [!] fix for CBFD using LWR op 
[!] fix for CBFD using AND op

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@723 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-13 09:57:10 +00:00
Corn
3630f80a4e [!] Removed redundant checks for operations on hi part of CPU regs in DynaRec 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@722 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-12 19:54:16 +00:00
Corn
220eda6b60 [!] Dynarec: reimplemented LWL & LWR OPs with much simpler code (faster) 
[!] Dynarec: implemented SWL & SWR OPs
[!] Framelimiter now averages with 4 frames (converge faster)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@721 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-12 10:16:32 +00:00
Corn
174c443405 [!] Made LoopOpt is more stable 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@719 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-10 22:53:35 +00:00
Corn
d5a8ab79e8 [!] Fixed bug that never enabled LoopOpt. (LoopOpt still only works in a few games like SM64) 
[!] Cleaned up BSOD text dump (shows when registers are pointing in RDRAM)
[+] added EXT & INS in disassembly and fixed MSB/LSB order

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@718 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-10 19:01:08 +00:00
Corn
6087b03842 [+] Added LWL and LWR OP codes to Dynarec 
[!] Only use real doubles in dynarec if forced from ROM hacks
[!] Some clean up and removal of Dynarec test code

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@717 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-10 13:40:15 +00:00
Corn
09fc9d323f [!] optimization of Patch_strchr() (OSHLE) 
[+] some comments

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@716 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-09 20:32:52 +00:00
salvy
192b71d8a2 [!] Rewrote logic to check if 32bit in dynarec 
[-] Removed checking if register was mapped as 32bit
[!] GenerateADDU : Sign extend when rt/rs is 0

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@715 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-09 20:07:35 +00:00
salvy
23d95254ed [-] Revert skipping sign extension when registers are mapped as 32bit 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@714 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-07-09 16:57:51 +00:00
salvy
850496599d [!] Skip sign extension in GenerateLW when base is mapped as 32bit (speed up, getting closer to fullspeed in Zelda, will enable this opt for more ops after some more testing) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@712 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-23 09:38:26 +00:00
salvy
47604559d0 [!] Skip sign extension for registers mapped as 32bit 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@710 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-22 06:35:04 +00:00
Corn
1d8e3bcc1b [!] Fix proper N64 to PSP scaling for large textures(see Worms, still don't work for 4:3 unscaled screen) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@709 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-21 19:16:26 +00:00
salvy
757cf58ae7 [+] Added compile flag to disable checking if logic is 32bit in dynarec 
[!] More aggressive checking if logic is 32bit

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@708 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-21 09:18:21 +00:00
salvy
4dc7789914 [-] Removed optimization in GenerateAND (Breaks SW - Racer) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@707 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-20 19:08:52 +00:00
salvy
899571ac6c [!] Simplify IgnoreHi, It'll only check if gate logic is non negative 
[!] Fixed Duck Dodgers not longer working with optimization in GenerateAND

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@706 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-20 18:09:55 +00:00
Corn
655b092461 [!] Additional fixes/optimizations to dynarec sim-doubles (SSV works now as well as most other games) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@704 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-14 19:21:38 +00:00
Corn
ba02be8004 [!] Small optimation in dynarec simdouble loading 
[!] rearrangement in Dynarec options 

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@703 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-13 12:53:59 +00:00
salvy
b163d14186 [!] Don't check hi part of known value when probing if high bits aren't needed (Fixes text being missing in OOT) 
[!] Check if register is mapped as 32bit, this will improve detection when high bits aren't needed (Experimental!)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@702 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-13 09:54:13 +00:00
salvy
308b5d6045 [!] Improved previous optimization in GenerateADDU 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@701 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-11 03:08:13 +00:00
salvy
42da530ddb [!] optimization in GenerateADD/U when rs/rt is R0 and register is known 
[!] optimization in GenerateAND when high bits aren't needed

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@700 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-11 00:53:30 +00:00
Corn
4f8db9c505 [!] Better compatibility using Doubles Opt. (fixes a few games) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@699 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-10 07:01:38 +00:00
salvy
673a287f0f [!] Made more robust optimizations in GenerateOR (we'll check more throughly if we need hi bits) (small speed up) 
[!] New optimization in GenerateOR when rs/rt is R0 and register is known

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@698 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-10 03:14:18 +00:00
Corn
b39e0b1c0b [!] Reverted MFC1 optimization, sign ext. is needed (broke DKR) 
[!] Various cleanup/bugfixes to SimDoubles

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@697 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-09 19:28:55 +00:00
Corn
cacf5b012f [+] Added more float/double conversion to dynarec doubles optimization 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@696 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-07 13:31:20 +00:00
Corn
a01b055016 [!] added dynarec simulated float caching in FPU and some clean up 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@693 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-05 20:41:02 +00:00
Corn
af43f1eace [+] New Speed up option: Dynarec Doubles Optimizations (advanced menu) when enabled dynarec compiles code to simulate doubles with floats 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@692 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-04 18:50:57 +00:00
salvy
4200ebdfc4 [!] Reverted optimization for ADDIU 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@691 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-03 22:58:30 +00:00
salvy
435aa824e4 [-] Removed optimization in ANDI (since we zero'd the hi reg regardless) 
[!] Optimization in OR

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@690 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-02 08:12:58 +00:00
salvy
8d98903504 [!} Opps typo! 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@689 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-01 02:46:20 +00:00
salvy
151441ba62 [!] Optimization in ADDIU & ANDI (Dynarec) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@688 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-01 02:42:19 +00:00
Corn
af5e1c9378 [!] Aerogauge fix 
[!] small optimization in floats branching when fast mode fails

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@687 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-31 19:18:36 +00:00
salvy
9842e2e7be [!] Fixed regression in Aerogauge 
[!] Optimization in XORI and ORI

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@686 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-31 00:58:46 +00:00
Corn
14e7a42018 [+] Dynarec: Added DADDI/DADDIU, DSRA32 and DSLL32 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@685 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-27 19:49:51 +00:00
Corn
3a0eed9c4a [+] Added INS/EXT and CFC1 OpCodes to AssemblyWriterPSP 
[!] Dynarec: Optimized float compare (no branch)
[!] Small fix/optimization to PIF swizzle 

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@684 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-27 12:50:06 +00:00
Corn
95b398565f [!] reverted ADDIU optimization (CBFD BSOD) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@681 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-25 20:40:39 +00:00
Corn
23fe749799 [!] Dynarec implemented LD/SD (load/store 64bit integer) 
[!] Dynarec partly implemented LDC1/SDC1 (load/store 64bit float)
[!] Dynarec if source reg is SP, ADDIU wont do sign extension.
[!] Dynarec Skip sign extending CFC1

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@680 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-23 16:54:56 +00:00
salvy
945d0c432e [+] Added known value optimizations to SLTx ops (32bit only!) in dynarec (they are disabled since I'm not sure is worth to handle them) 
[!] PIF Ram - swap while copying in one go and fuses 4 transfers in one (slight speed-up) (Salvy & Corn)


git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@679 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-22 09:08:52 +00:00
Corn
81439edd67 [!] Made BC1T/BC1F branching more robust (fixes RR64) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@678 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-21 20:12:16 +00:00
Corn
50c3f2efaf [!] Dynarec: Improved performance of float compare and branching (BC1F/BC1T) (speedup) 
[!] Dynarec: Removed exception check after interpreter calls from dynarec (speedup)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@676 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-18 20:14:57 +00:00
Corn
0bcbaae951 [!] reverted change that causes Yoshi to BSOD 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@672 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-15 17:20:42 +00:00
Corn
cb9f855f66 [!] Dynarec: Disabled divide by zero check for DIV/DIVU 
[!] Dynarec: Removed sign extension on MULT/MULTU & DIV/DIVU

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@667 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-13 13:03:23 +00:00
Corn
2becc08549 [!] minor cleanup in Codegenerator 
[!] Added K0 & K1 as non temp registers

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@666 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-12 19:47:51 +00:00
Corn
c1133f7877 [!] reverted HLE cache patch (while it does cause issues there are more HLE issues in Fzero) 
[-] removed redundant SP register update code in dynarec

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@661 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-07 20:02:37 +00:00
Corn
ece1c6efd2 [!] Dynarec: More improved in SLTx functions (32bit bit) 
[!] Fixed BlendExplorer to work with new blend functions

Note from Strmn that SLTI is buggy in 64bit mode


git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@658 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-03 18:58:00 +00:00
Corn
daf8cd66b4 [!] HLE: changed code for CPU/FPU register save (better for CPU cache) 
[!] HLE: Fixed annoying warnings
[!] DYNAREC: more optimizations for float load/stores (speedup)
[!] DYNAREC: Skip using full 64bit compare for SLT/SLTI/SLTU/SLTIU (speedup)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@652 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-30 12:21:07 +00:00
salvy
54bba54796 [!] Fixed build 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@650 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-22 19:46:48 +00:00