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143 commits

Author SHA1 Message Date
Corn
a01b055016 [!] added dynarec simulated float caching in FPU and some clean up 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@693 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-05 20:41:02 +00:00
Corn
af43f1eace [+] New Speed up option: Dynarec Doubles Optimizations (advanced menu) when enabled dynarec compiles code to simulate doubles with floats 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@692 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-04 18:50:57 +00:00
salvy
4200ebdfc4 [!] Reverted optimization for ADDIU 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@691 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-03 22:58:30 +00:00
salvy
435aa824e4 [-] Removed optimization in ANDI (since we zero'd the hi reg regardless) 
[!] Optimization in OR

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@690 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-02 08:12:58 +00:00
salvy
8d98903504 [!} Opps typo! 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@689 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-01 02:46:20 +00:00
salvy
151441ba62 [!] Optimization in ADDIU & ANDI (Dynarec) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@688 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-06-01 02:42:19 +00:00
Corn
af5e1c9378 [!] Aerogauge fix 
[!] small optimization in floats branching when fast mode fails

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@687 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-31 19:18:36 +00:00
salvy
9842e2e7be [!] Fixed regression in Aerogauge 
[!] Optimization in XORI and ORI

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@686 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-31 00:58:46 +00:00
Corn
14e7a42018 [+] Dynarec: Added DADDI/DADDIU, DSRA32 and DSLL32 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@685 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-27 19:49:51 +00:00
Corn
3a0eed9c4a [+] Added INS/EXT and CFC1 OpCodes to AssemblyWriterPSP 
[!] Dynarec: Optimized float compare (no branch)
[!] Small fix/optimization to PIF swizzle 

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@684 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-27 12:50:06 +00:00
Corn
95b398565f [!] reverted ADDIU optimization (CBFD BSOD) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@681 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-25 20:40:39 +00:00
Corn
23fe749799 [!] Dynarec implemented LD/SD (load/store 64bit integer) 
[!] Dynarec partly implemented LDC1/SDC1 (load/store 64bit float)
[!] Dynarec if source reg is SP, ADDIU wont do sign extension.
[!] Dynarec Skip sign extending CFC1

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@680 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-23 16:54:56 +00:00
salvy
945d0c432e [+] Added known value optimizations to SLTx ops (32bit only!) in dynarec (they are disabled since I'm not sure is worth to handle them) 
[!] PIF Ram - swap while copying in one go and fuses 4 transfers in one (slight speed-up) (Salvy & Corn)


git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@679 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-22 09:08:52 +00:00
Corn
81439edd67 [!] Made BC1T/BC1F branching more robust (fixes RR64) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@678 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-21 20:12:16 +00:00
Corn
50c3f2efaf [!] Dynarec: Improved performance of float compare and branching (BC1F/BC1T) (speedup) 
[!] Dynarec: Removed exception check after interpreter calls from dynarec (speedup)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@676 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-18 20:14:57 +00:00
Corn
0bcbaae951 [!] reverted change that causes Yoshi to BSOD 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@672 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-15 17:20:42 +00:00
Corn
cb9f855f66 [!] Dynarec: Disabled divide by zero check for DIV/DIVU 
[!] Dynarec: Removed sign extension on MULT/MULTU & DIV/DIVU

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@667 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-13 13:03:23 +00:00
Corn
2becc08549 [!] minor cleanup in Codegenerator 
[!] Added K0 & K1 as non temp registers

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@666 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-12 19:47:51 +00:00
Corn
c1133f7877 [!] reverted HLE cache patch (while it does cause issues there are more HLE issues in Fzero) 
[-] removed redundant SP register update code in dynarec

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@661 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-07 20:02:37 +00:00
Corn
ece1c6efd2 [!] Dynarec: More improved in SLTx functions (32bit bit) 
[!] Fixed BlendExplorer to work with new blend functions

Note from Strmn that SLTI is buggy in 64bit mode


git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@658 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-05-03 18:58:00 +00:00
Corn
daf8cd66b4 [!] HLE: changed code for CPU/FPU register save (better for CPU cache) 
[!] HLE: Fixed annoying warnings
[!] DYNAREC: more optimizations for float load/stores (speedup)
[!] DYNAREC: Skip using full 64bit compare for SLT/SLTI/SLTU/SLTIU (speedup)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@652 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-30 12:21:07 +00:00
salvy
54bba54796 [!] Fixed build 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@650 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-22 19:46:48 +00:00
Corn
9f409e389c [+] Optimized non swizzled loads and stores when MemOpt fails 
[!] Some cleanup in non handled OPs in dynarec

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@649 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-22 14:19:14 +00:00
salvy
bde08d245f [!] Some CodeGen logic optimizations 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@648 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-22 02:37:55 +00:00
Corn
e73ee9e5fc [+] Optimized MemOpt static analyzer 
[+] Implemented LWC1/SWC1 (Skipping MTC1/MFC1 for every access to or from FPU)
[+] Re-use old base register if possible for LW/LWC1 and SW/SWC1 (skipping address calculation for every load and store, most effective with MemOpt enabled)
[!] LoopOpt should be much more stable now 

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@646 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-19 20:12:00 +00:00
Corn
3f1e612b52 [-] Reverted LWC1/SWC1 FPU OPs (caused to many issues need more work) 
[!] Reorganized Build Config flags

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@643 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-13 13:12:34 +00:00
Corn
4e7d69e889 [+] Dynarec: Added K0 and K1 to available cashed regs 
[!] Dynarec: Skip sign extension on GP and SP regs on update
[!] Dynarec: Optimized ADDU when when source reg is R0
[!] Dynarec: Optimized ADDUI not to store sign extension on SP reg
[+] Dynarec: Implemented LWC1 and SWC1 to load and store directly to FPU
[!] Fixed some ASSERTs
[-] Removed automatic fragment dump on ROM exit

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@641 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-04-10 14:55:18 +00:00
Corn
c579df6db4 [!] Clean up and optimizations in Dynarec 
[!] Clean up and nicer looking tool tip
[!] Clean up in T1_HACK  


git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@631 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-03-27 19:37:42 +00:00
Corn
a6c58b4d9b [!] fixed missing function in previous rev 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@625 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-03-14 19:11:33 +00:00
salvy
bee8785d7f [!] Optimizations to CodeGen (small speed-up) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@624 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2012-03-13 22:24:13 +00:00
Corn
d7bbcab7df [!] Small optimization in Dynarec/fragments 
[!] Disabled Loop Opt for Donald Duck Going Quackers
[~] Reverted Loop Opt to old code (pre 618)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@541 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-12-17 19:42:49 +00:00
Salvy
c4d9f89e02 [!] Simplified memory access analyst (shoves off 3k+ ops in StaticAnalysis.cpp) 
[!] Simplified parameters in CodeGen

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@387 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-09-01 05:44:22 +00:00
Salvy
f98d6981d4 [!] Clean up options etc (Removed Stack Optimisation option, it works perfectly fine with all the games, there's no point to have an option for it) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@355 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-08-15 21:28:54 +00:00
Salvy
aa403ef24e [~] Corrected typo from previous commit which broke GenerateCACHE (Corn) 
[!] Enabled option to ignore memory bound checking in release mode (slight speed up)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@344 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-08-08 18:39:14 +00:00
Corn
efaf483618 [!] some small optimizations in code generator 
[-] removed non working fix for TV output

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@343 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-08-07 14:57:50 +00:00
Salvy
ef103db924 [!] Optimized GenerateCTC1 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@342 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-08-06 14:31:06 +00:00
Salvy
d79531585d [+] Implemented MFC0 in dynarec 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@341 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-08-06 06:58:04 +00:00
Salvy
aeaf90d317 [!] Trap r0 write in LW (fixes San Francisco 2049 crashing when race is about to start) 
[+] Added debug code to detect r0 writes

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@312 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-06-24 22:41:24 +00:00
Salvy
04329769c3 [-] Reverted changes from 64 -> 32bit in interrupts (slightly slower but safer) 
[-} Reverted change in GenerateCFC1 (it caused issues in the interpreter, it can be risky for the dynarec as well)

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@229 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-04-12 06:20:36 +00:00
Salvy
9bc291106b [-] More clean ups to dynarec 
[!] Forgot to enabled mem access opt for cache op

git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@78 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-01-13 07:32:55 +00:00
Salvy
04f8b89782 [~] Simplified a couple of parameters in dynarec codegen 
[~] Disabled mem opt for LW op (breaks Paper Mario)
[~] Do mem access opt for cache op (balances speed lost from LW)
[!] Made RDP_SetOtherMode debug only (we no longer use gRDPOtherMode._u64 anyways)
[+] Added locally a modified build.mak, also restored -MD flag and old makefile style) 


git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@77 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-01-13 06:33:20 +00:00
Salvy
de2b288b5b [!] Merge back Memory Access opt (Disabled by default, Mario 3D head is now 25+ fps) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@42 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2011-01-05 06:45:30 +00:00
Salvy
bdbd952c60 [+] Initial repo (based from r630 dx64 branch) 
git-svn-id: https://subversion.assembla.com/svn/Daedalusx64/trunk@3 42e9bfbe-799a-4a2d-bad1-236e862a387a
 2010-12-24 04:37:41 +00:00