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If we place larger, less commonly used structures after our frequently accessed state variables, the average size of x86 instructions will be reduced due to the smaller offsets off the base pointer.
112 lines
3.8 KiB
C
112 lines
3.8 KiB
C
//
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// vr4300/cpu.h: VR4300 processor container.
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//
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// CEN64: Cycle-Accurate Nintendo 64 Simulator.
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// Copyright (C) 2014, Tyler J. Stachecki.
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//
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// This file is subject to the terms and conditions defined in
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// 'LICENSE', which is part of this source code package.
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//
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#ifndef __vr4300_cpu_h__
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#define __vr4300_cpu_h__
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#include "common.h"
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#include "vr4300/cp0.h"
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#include "vr4300/cp1.h"
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#include "vr4300/dcache.h"
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#include "vr4300/icache.h"
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#include "vr4300/pipeline.h"
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struct bus_controller;
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enum vr4300_signals {
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VR4300_SIGNAL_FORCEEXIT = 0x000000001,
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VR4300_SIGNAL_COLDRESET = 0x000000002,
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};
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enum vr4300_register {
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VR4300_REGISTER_R0, VR4300_REGISTER_AT, VR4300_REGISTER_V0,
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VR4300_REGISTER_V1, VR4300_REGISTER_A0, VR4300_REGISTER_A1,
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VR4300_REGISTER_A2, VR4300_REGISTER_A3, VR4300_REGISTER_T0,
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VR4300_REGISTER_T1, VR4300_REGISTER_T2, VR4300_REGISTER_T3,
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VR4300_REGISTER_T4, VR4300_REGISTER_R5, VR4300_REGISTER_T6,
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VR4300_REGISTER_T7, VR4300_REGISTER_S0, VR4300_REGISTER_S1,
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VR4300_REGISTER_S2, VR4300_REGISTER_S3, VR4300_REGISTER_S4,
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VR4300_REGISTER_S5, VR4300_REGISTER_S6, VR4300_REGISTER_S7,
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VR4300_REGISTER_T8, VR4300_REGISTER_T9, VR4300_REGISTER_K0,
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VR4300_REGISTER_K1, VR4300_REGISTER_GP, VR4300_REGISTER_SP,
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VR4300_REGISTER_FP, VR4300_REGISTER_RA,
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// CP0 registers.
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VR4300_REGISTER_CP0_0, VR4300_REGISTER_CP0_1, VR4300_REGISTER_CP0_2,
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VR4300_REGISTER_CP0_3, VR4300_REGISTER_CP0_4, VR4300_REGISTER_CP0_5,
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VR4300_REGISTER_CP0_6, VR4300_REGISTER_CP0_7, VR4300_REGISTER_CP0_8,
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VR4300_REGISTER_CP0_9, VR4300_REGISTER_CP0_10, VR4300_REGISTER_CP0_11,
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VR4300_REGISTER_CP0_12, VR4300_REGISTER_CP0_13, VR4300_REGISTER_CP0_14,
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VR4300_REGISTER_CP0_15, VR4300_REGISTER_CP0_16, VR4300_REGISTER_CP0_17,
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VR4300_REGISTER_CP0_18, VR4300_REGISTER_CP0_19, VR4300_REGISTER_CP0_20,
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VR4300_REGISTER_CP0_21, VR4300_REGISTER_CP0_22, VR4300_REGISTER_CP0_23,
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VR4300_REGISTER_CP0_24, VR4300_REGISTER_CP0_25, VR4300_REGISTER_CP0_26,
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VR4300_REGISTER_CP0_27, VR4300_REGISTER_CP0_28, VR4300_REGISTER_CP0_29,
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VR4300_REGISTER_CP0_30, VR4300_REGISTER_CP0_31,
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// CP1 registers.
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VR4300_REGISTER_CP1_0, VR4300_REGISTER_CP1_1, VR4300_REGISTER_CP1_2,
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VR4300_REGISTER_CP1_3, VR4300_REGISTER_CP1_4, VR4300_REGISTER_CP1_5,
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VR4300_REGISTER_CP1_6, VR4300_REGISTER_CP1_7, VR4300_REGISTER_CP1_8,
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VR4300_REGISTER_CP1_9, VR4300_REGISTER_CP1_10, VR4300_REGISTER_CP1_11,
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VR4300_REGISTER_CP1_12, VR4300_REGISTER_CP1_13, VR4300_REGISTER_CP1_14,
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VR4300_REGISTER_CP1_15, VR4300_REGISTER_CP1_16, VR4300_REGISTER_CP1_17,
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VR4300_REGISTER_CP1_18, VR4300_REGISTER_CP1_19, VR4300_REGISTER_CP1_20,
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VR4300_REGISTER_CP1_21, VR4300_REGISTER_CP1_22, VR4300_REGISTER_CP1_23,
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VR4300_REGISTER_CP1_24, VR4300_REGISTER_CP1_25, VR4300_REGISTER_CP1_26,
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VR4300_REGISTER_CP1_27, VR4300_REGISTER_CP1_28, VR4300_REGISTER_CP1_29,
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VR4300_REGISTER_CP1_30, VR4300_REGISTER_CP1_31,
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// Miscellanious registers.
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VR4300_REGISTER_HI, VR4300_REGISTER_LO,
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VR4300_CP1_FCR0, VR4300_CP1_FCR31,
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// Pipeline cycle type flag.
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//
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// Putting these here along with the other registers allows us to
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// correctly (and cheaply) detect that a busy-wait loop instruction
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// is retiring.
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PIPELINE_CYCLE_TYPE,
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NUM_VR4300_REGISTERS
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};
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enum mi_register {
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#define X(reg) reg,
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#include "vr4300/registers.md"
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#undef X
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NUM_MI_REGISTERS,
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};
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#ifdef DEBUG_MMIO_REGISTER_ACCESS
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extern const char *mi_register_mnemonics[NUM_MI_REGISTERS];
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#endif
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struct vr4300 {
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struct vr4300_pipeline pipeline;
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struct vr4300_cp1 cp1;
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struct bus_controller *bus;
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unsigned long long cycles;
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unsigned signals;
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uint64_t regs[NUM_VR4300_REGISTERS];
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uint32_t mi_regs[NUM_MI_REGISTERS];
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struct vr4300_dcache dcache;
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struct vr4300_icache icache;
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};
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void vr4300_cycle(struct vr4300 *vr4300);
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int vr4300_init(struct vr4300 *vr4300, struct bus_controller *bus);
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#endif
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