mirror of
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225 lines
14 KiB
C
225 lines
14 KiB
C
//
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// vr4300/opcodes_priv.h: VR4300 opcode types and info.
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//
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// CEN64: Cycle-Accurate Nintendo 64 Emulator.
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// Copyright (C) 2015, Tyler J. Stachecki.
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//
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// This file is subject to the terms and conditions defined in
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// 'LICENSE', which is part of this source code package.
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//
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#ifndef __vr4300_opcodes_priv_h__
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#define __vr4300_opcodes_priv_h__
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#include "common.h"
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#include "vr4300/opcodes.h"
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#define INFO1(x) (OPCODE_INFO_##x)
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#define INFO2(x,y) (INFO1(x) | OPCODE_INFO_##y)
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#define INFO3(x,y,z) (INFO2(x,y) | OPCODE_INFO_##z)
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#define INFO4(x,y,z,a) (INFO3(x,y,z) | OPCODE_INFO_##a)
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#define INFO5(x,y,z,a,b) (INFO4(x,y,z,a) | OPCODE_INFO_##b)
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#define INVALID VR4300_BUILD_OP(INVALID, INVALID, INFO1(NONE))
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#ifdef VR4300_BUSY_WAIT_DETECTION
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#define BEQ VR4300_BUILD_OP(BEQ, BEQ_BEQL_BNE_BNEL_BWDETECT, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define BEQL VR4300_BUILD_OP(BEQL, BEQ_BEQL_BNE_BNEL_BWDETECT, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define BNE VR4300_BUILD_OP(BNE, BEQ_BEQL_BNE_BNEL_BWDETECT, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define BNEL VR4300_BUILD_OP(BNEL, BEQ_BEQL_BNE_BNEL_BWDETECT, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define J VR4300_BUILD_OP(J, J_JAL_BWDETECT, INFO1(BRANCH))
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#define JAL VR4300_BUILD_OP(JAL, J_JAL_BWDETECT, INFO1(BRANCH))
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#else
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#define BEQ VR4300_BUILD_OP(BEQ, BEQ_BEQL_BNE_BNEL, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define BEQL VR4300_BUILD_OP(BEQL, BEQ_BEQL_BNE_BNEL, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define BNE VR4300_BUILD_OP(BNE, BEQ_BEQL_BNE_BNEL, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define BNEL VR4300_BUILD_OP(BNEL, BEQ_BEQL_BNE_BNEL, INFO3(BRANCH, NEEDRS, NEEDRT))
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#define J VR4300_BUILD_OP(J, J_JAL, INFO1(BRANCH))
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#define JAL VR4300_BUILD_OP(JAL, J_JAL, INFO1(BRANCH))
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#endif
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#define ADD VR4300_BUILD_OP(ADD, ADD_SUB, INFO2(NEEDRS, NEEDRT))
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#define ADDI VR4300_BUILD_OP(ADDI, ADDI_SUBI, INFO1(NEEDRS))
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#define ADDIU VR4300_BUILD_OP(ADDIU, ADDIU_LUI_SUBIU, INFO1(NEEDRS))
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#define ADDU VR4300_BUILD_OP(ADDU, ADDU_SUBU, INFO2(NEEDRS, NEEDRT))
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#define AND VR4300_BUILD_OP(AND, AND_OR_XOR, INFO2(NEEDRS, NEEDRT))
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#define ANDI VR4300_BUILD_OP(ANDI, ANDI_ORI_XORI, INFO1(NEEDRS))
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#define BGEZ VR4300_BUILD_OP(BGEZ, BGEZ_BGEZL_BLTZ_BLTZL, INFO2(BRANCH, NEEDRS))
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#define BGEZAL VR4300_BUILD_OP(BGEZAL, BGEZAL_BGEZALL_BLTZAL_BLTZALL, INFO2(BRANCH, NEEDRS))
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#define BGEZALL VR4300_BUILD_OP(BGEZALL, BGEZAL_BGEZALL_BLTZAL_BLTZALL, INFO2(BRANCH, NEEDRS))
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#define BGEZL VR4300_BUILD_OP(BGEZL, BGEZ_BGEZL_BLTZ_BLTZL, INFO2(BRANCH, NEEDRS))
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#define BGTZ VR4300_BUILD_OP(BGTZ, BGTZ_BGTZL_BLEZ_BLEZL, INFO2(BRANCH, NEEDRS))
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#define BGTZL VR4300_BUILD_OP(BGTZL, BGTZ_BGTZL_BLEZ_BLEZL, INFO2(BRANCH, NEEDRS))
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#define BLEZ VR4300_BUILD_OP(BLEZ, BGTZ_BGTZL_BLEZ_BLEZL, INFO2(BRANCH, NEEDRS))
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#define BLEZL VR4300_BUILD_OP(BLEZL, BGTZ_BGTZL_BLEZ_BLEZL, INFO2(BRANCH, NEEDRS))
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#define BLTZ VR4300_BUILD_OP(BLTZ, BGEZ_BGEZL_BLTZ_BLTZL, INFO2(BRANCH, NEEDRS))
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#define BLTZAL VR4300_BUILD_OP(BLTZAL, BGEZAL_BGEZALL_BLTZAL_BLTZALL, INFO2(BRANCH, NEEDRS))
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#define BLTZALL VR4300_BUILD_OP(BLTZALL, BGEZAL_BGEZALL_BLTZAL_BLTZALL, INFO2(BRANCH, NEEDRS))
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#define BLTZL VR4300_BUILD_OP(BLTZL, BGEZ_BGEZL_BLTZ_BLTZL, INFO2(BRANCH, NEEDRS))
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#define BREAK VR4300_BUILD_OP(BREAK, BREAK, INFO1(NONE))
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#define DADD VR4300_BUILD_OP(DADD, DADD_DSUB, INFO2(NEEDRS, NEEDRT))
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#define DADDI VR4300_BUILD_OP(DADDI, DADDI_DSUBI, INFO1(NEEDRS))
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#define DADDIU VR4300_BUILD_OP(DADDIU, DADDIU_DSUBIU, INFO1(NEEDRS))
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#define DADDU VR4300_BUILD_OP(DADDU, DADDU_DSUBU, INFO2(NEEDRS, NEEDRT))
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#define DDIV VR4300_BUILD_OP(DDIV, DDIV, INFO2(NEEDRS, NEEDRT))
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#define DDIVU VR4300_BUILD_OP(DDIVU, DDIVU, INFO2(NEEDRS, NEEDRT))
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#define DIV VR4300_BUILD_OP(DIV, DIV_DIVU, INFO2(NEEDRS, NEEDRT))
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#define DIVU VR4300_BUILD_OP(DIVU, DIV_DIVU, INFO2(NEEDRS, NEEDRT))
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#define DMULT VR4300_BUILD_OP(DMULT, DMULT, INFO2(NEEDRS, NEEDRT))
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#define DMULTU VR4300_BUILD_OP(DMULTU, DMULTU, INFO2(NEEDRS, NEEDRT))
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#define DSLL VR4300_BUILD_OP(DSLL, DSLL_DSLL32, INFO1(NEEDRT))
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#define DSLLV VR4300_BUILD_OP(DSLLV, DSLLV, INFO2(NEEDRS, NEEDRT))
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#define DSLL32 VR4300_BUILD_OP(DSLL32, DSLL_DSLL32, INFO1(NEEDRT))
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#define DSRA VR4300_BUILD_OP(DSRA, DSRA_DSRA32, INFO1(NEEDRT))
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#define DSRAV VR4300_BUILD_OP(DSRAV, DSRAV, INFO2(NEEDRS, NEEDRT))
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#define DSRA32 VR4300_BUILD_OP(DSRA32, DSRA_DSRA32, INFO1(NEEDRT))
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#define DSRL VR4300_BUILD_OP(DSRL, DSRL_DSRL32, INFO1(NEEDRT))
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#define DSRLV VR4300_BUILD_OP(DSRLV, DSRLV, INFO2(NEEDRS, NEEDRT))
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#define DSRL32 VR4300_BUILD_OP(DSRL32, DSRL_DSRL32, INFO1(NEEDRT))
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#define DSUB VR4300_BUILD_OP(DSUB, DADD_DSUB, INFO2(NEEDRS, NEEDRT))
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#define DSUBU VR4300_BUILD_OP(DSUBU, DADDU_DSUBU, INFO2(NEEDRS, NEEDRT))
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#define JALR VR4300_BUILD_OP(JALR, JALR_JR, INFO2(BRANCH, NEEDRS))
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#define JR VR4300_BUILD_OP(JR, JALR_JR, INFO2(BRANCH, NEEDRS))
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#define LB VR4300_BUILD_OP(LB, LOAD_STORE, INFO2(NEEDRS, LOAD))
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#define LBU VR4300_BUILD_OP(LBU, LOAD_STORE, INFO2(NEEDRS, LOAD))
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#define LD VR4300_BUILD_OP(LD, LD_SD, INFO2(NEEDRS, LOAD))
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#define LDL VR4300_BUILD_OP(LDL, LDL_LDR, INFO3(NEEDRS, NEEDRT, LOAD))
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#define LDR VR4300_BUILD_OP(LDR, LDL_LDR, INFO3(NEEDRS, NEEDRT, LOAD))
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#define LH VR4300_BUILD_OP(LH, LOAD_STORE, INFO2(NEEDRS, LOAD))
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#define LHU VR4300_BUILD_OP(LHU, LOAD_STORE, INFO2(NEEDRS, LOAD))
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#define LL VR4300_BUILD_OP(LL, INVALID, INFO1(NONE))
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#define LLD VR4300_BUILD_OP(LLD, INVALID, INFO1(NONE))
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#define LUI VR4300_BUILD_OP(LUI, ADDIU_LUI_SUBIU, INFO1(NONE))
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#define LW VR4300_BUILD_OP(LW, LOAD_STORE, INFO2(NEEDRS, LOAD))
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#define LWL VR4300_BUILD_OP(LWL, LWL_LWR, INFO3(NEEDRS, NEEDRT, LOAD))
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#define LWR VR4300_BUILD_OP(LWR, LWL_LWR, INFO3(NEEDRS, NEEDRT, LOAD))
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#define LWU VR4300_BUILD_OP(LWU, LOAD_STORE, INFO2(NEEDRS, LOAD))
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#define MFHI VR4300_BUILD_OP(MFHI, MFHI_MFLO, INFO1(NONE))
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#define MFLO VR4300_BUILD_OP(MFLO, MFHI_MFLO, INFO1(NONE))
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#define MTHI VR4300_BUILD_OP(MTHI, MTHI_MTLO, INFO1(NEEDRS))
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#define MTLO VR4300_BUILD_OP(MTLO, MTHI_MTLO, INFO1(NEEDRS))
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#define MULT VR4300_BUILD_OP(MULT, MULT_MULTU, INFO2(NEEDRS, NEEDRT))
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#define MULTU VR4300_BUILD_OP(MULTU, MULT_MULTU, INFO2(NEEDRS, NEEDRT))
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#define NOR VR4300_BUILD_OP(NOR, NOR, INFO2(NEEDRS, NEEDRT))
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#define OR VR4300_BUILD_OP(OR, AND_OR_XOR, INFO2(NEEDRS, NEEDRT))
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#define ORI VR4300_BUILD_OP(ORI, ANDI_ORI_XORI, INFO1(NEEDRS))
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#define SB VR4300_BUILD_OP(SB, LOAD_STORE, INFO3(NEEDRS, NEEDRT, STORE))
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#define SC VR4300_BUILD_OP(SC, INVALID, INFO1(NONE))
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#define SCD VR4300_BUILD_OP(SCD, INVALID, INFO1(NONE))
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#define SD VR4300_BUILD_OP(SD, LD_SD, INFO3(NEEDRS, NEEDRT, STORE))
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#define SDL VR4300_BUILD_OP(SDL, SDL_SDR, INFO3(NEEDRS, NEEDRT, STORE))
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#define SDR VR4300_BUILD_OP(SDR, SDL_SDR, INFO3(NEEDRS, NEEDRT, STORE))
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#define SH VR4300_BUILD_OP(SH, LOAD_STORE, INFO3(NEEDRS, NEEDRT, STORE))
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#define SLL VR4300_BUILD_OP(SLL, SLL_SLLV, INFO1(NEEDRT))
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#define SLLV VR4300_BUILD_OP(SLLV, SLL_SLLV, INFO2(NEEDRS, NEEDRT))
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#define SLT VR4300_BUILD_OP(SLT, SLT, INFO2(NEEDRS, NEEDRT))
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#define SLTI VR4300_BUILD_OP(SLTI, SLTI, INFO1(NEEDRS))
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#define SLTIU VR4300_BUILD_OP(SLTIU, SLTIU, INFO1(NEEDRS))
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#define SLTU VR4300_BUILD_OP(SLTU, SLTU, INFO2(NEEDRS, NEEDRT))
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#define SRA VR4300_BUILD_OP(SRA, SRA, INFO1(NEEDRT))
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#define SRAV VR4300_BUILD_OP(SRAV, SRAV, INFO2(NEEDRS, NEEDRT))
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#define SRL VR4300_BUILD_OP(SRL, SRL, INFO1(NEEDRT))
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#define SRLV VR4300_BUILD_OP(SRLV, SRLV, INFO2(NEEDRS, NEEDRT))
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#define SUB VR4300_BUILD_OP(SUB, ADD_SUB, INFO2(NEEDRS, NEEDRT))
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#define SUBU VR4300_BUILD_OP(SUBU, ADDU_SUBU, INFO1(NEEDRS))
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#define SW VR4300_BUILD_OP(SW, LOAD_STORE, INFO3(NEEDRS, NEEDRT, STORE))
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#define SWL VR4300_BUILD_OP(SWL, SWL_SWR, INFO3(NEEDRS, NEEDRT, STORE))
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#define SWR VR4300_BUILD_OP(SWR, SWL_SWR, INFO3(NEEDRS, NEEDRT, STORE))
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#define SYNC VR4300_BUILD_OP(SYNC, SLL_SLLV, INFO1(NONE))
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#define SYSCALL VR4300_BUILD_OP(SYSCALL, SYSCALL, INFO1(NONE))
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#define TEQ VR4300_BUILD_OP(TEQ, TEQ_TNE, INFO2(NEEDRS, NEEDRT))
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#define TEQI VR4300_BUILD_OP(TEQI, TEQI_TNEI, INFO1(NEEDRS))
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#define TGE VR4300_BUILD_OP(TGE, TGE_TLT, INFO2(NEEDRS, NEEDRT))
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#define TGEI VR4300_BUILD_OP(TGEI, TGEI_TLTI, INFO1(NEEDRS))
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#define TGEIU VR4300_BUILD_OP(TGEIU, TGEIU_TLTIU, INFO1(NEEDRS))
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#define TGEU VR4300_BUILD_OP(TGEU, TGEU_TLTU, INFO2(NEEDRS, NEEDRT))
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#define TLT VR4300_BUILD_OP(TLT, TGE_TLT, INFO2(NEEDRS, NEEDRT))
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#define TLTI VR4300_BUILD_OP(TLTI, TGEI_TLTI, INFO1(NEEDRS))
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#define TLTIU VR4300_BUILD_OP(TLTIU, TGEIU_TLTIU, INFO1(NEEDRS))
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#define TLTU VR4300_BUILD_OP(TLTU, TGEU_TLTU, INFO2(NEEDRS, NEEDRT))
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#define TNE VR4300_BUILD_OP(TNE, TEQ_TNE, INFO2(NEEDRS, NEEDRT))
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#define TNEI VR4300_BUILD_OP(TNEI, TEQI_TNEI, INFO1(NEEDRS))
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#define XOR VR4300_BUILD_OP(XOR, AND_OR_XOR, INFO2(NEEDRS, NEEDRT))
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#define XORI VR4300_BUILD_OP(XORI, ANDI_ORI_XORI, INFO1(NEEDRS))
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#define BC0 VR4300_BUILD_OP(BC0, INVALID, INFO1(BRANCH))
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#define CFC0 VR4300_BUILD_OP(CFC0, INVALID, INFO1(NONE))
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#define CTC0 VR4300_BUILD_OP(CTC0, INVALID, INFO1(NONE))
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#define DMFC0 VR4300_BUILD_OP(DMFC0, DMFC0, INFO1(NONE))
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#define DMTC0 VR4300_BUILD_OP(DMTC0, DMTC0, INFO1(NEEDRT))
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#define LDC0 VR4300_BUILD_OP(LDC0, INVALID, INFO1(LOAD))
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#define LWC0 VR4300_BUILD_OP(LWC0, INVALID, INFO1(LOAD))
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#define MFC0 VR4300_BUILD_OP(MFC0, MFC0, INFO1(NONE))
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#define MTC0 VR4300_BUILD_OP(MTC0, MTC0, INFO1(NEEDRT))
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#define SDC0 VR4300_BUILD_OP(SDC0, INVALID, INFO1(STORE))
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#define SWC0 VR4300_BUILD_OP(SWC0, INVALID, INFO1(STORE))
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#define CACHE VR4300_BUILD_OP(CACHE, CACHE, INFO1(NEEDRS))
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#define ERET VR4300_BUILD_OP(ERET, ERET, INFO1(NONE))
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#define TLBP VR4300_BUILD_OP(TLBP, TLBP, INFO1(NONE))
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#define TLBR VR4300_BUILD_OP(TLBR, TLBR, INFO1(NONE))
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#define TLBWI VR4300_BUILD_OP(TLBWI, TLBWI, INFO1(NONE))
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#define TLBWR VR4300_BUILD_OP(TLBWR, TLBWR, INFO1(NONE))
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#define BC1 VR4300_BUILD_OP(BC1, BC1, INFO2(FPU, BRANCH))
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#define CFC1 VR4300_BUILD_OP(CFC1, CFC1, INFO2(FPU, NONE))
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#define CTC1 VR4300_BUILD_OP(CTC1, CTC1, INFO2(FPU, NONE))
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#define DMFC1 VR4300_BUILD_OP(DMFC1, DMFC1, INFO2(FPU, NEEDFS))
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#define DMTC1 VR4300_BUILD_OP(DMTC1, DMTC1, INFO2(FPU, NEEDRT))
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#define LDC1 VR4300_BUILD_OP(LDC1, LDC1, INFO3(FPU, NEEDRS, LOAD))
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#define LWC1 VR4300_BUILD_OP(LWC1, LWC1, INFO4(FPU, NEEDRS, NEEDFT, LOAD))
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#define MFC1 VR4300_BUILD_OP(MFC1, MFC1, INFO2(FPU, NEEDFS))
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#define MTC1 VR4300_BUILD_OP(MTC1, MTC1, INFO3(FPU, NEEDFS, NEEDRT))
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#define SDC1 VR4300_BUILD_OP(SDC1, SDC1, INFO4(FPU, NEEDRS, NEEDFT, STORE))
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#define SWC1 VR4300_BUILD_OP(SWC1, SWC1, INFO4(FPU, NEEDRS, NEEDFT, STORE))
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#define CP1_ABS VR4300_BUILD_OP(CP1_ABS, CP1_ABS, INFO3(FPU, FPU, NEEDFS))
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#define CP1_ADD VR4300_BUILD_OP(CP1_ADD, CP1_ADD, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_EQ VR4300_BUILD_OP(CP1_C_EQ, CP1_C_EQ_C_SEQ, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_F VR4300_BUILD_OP(CP1_C_F, CP1_C_F_C_SF, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_LE VR4300_BUILD_OP(CP1_C_LE, CP1_C_OLE_C_LE, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_LT VR4300_BUILD_OP(CP1_C_LT, CP1_C_OLT_C_LT, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_NGE VR4300_BUILD_OP(CP1_C_NGE, CP1_C_ULT_C_NGE, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_NGL VR4300_BUILD_OP(CP1_C_NGL, CP1_C_UEQ_C_NGL, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_NGLE VR4300_BUILD_OP(CP1_C_NGLE, CP1_C_UN_C_NGLE, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_NGT VR4300_BUILD_OP(CP1_C_NGT, CP1_C_ULE_C_NGT, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_OLE VR4300_BUILD_OP(CP1_C_OLE, CP1_C_OLE_C_LE, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_OLT VR4300_BUILD_OP(CP1_C_OLT, CP1_C_OLT_C_LT, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_SEQ VR4300_BUILD_OP(CP1_C_SEQ, CP1_C_EQ_C_SEQ, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_SF VR4300_BUILD_OP(CP1_C_SF, CP1_C_F_C_SF, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_UEQ VR4300_BUILD_OP(CP1_C_UEQ, CP1_C_UEQ_C_NGL, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_ULE VR4300_BUILD_OP(CP1_C_ULE, CP1_C_ULE_C_NGT, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_ULT VR4300_BUILD_OP(CP1_C_ULT, CP1_C_ULT_C_NGE, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_C_UN VR4300_BUILD_OP(CP1_C_UN, CP1_C_UN_C_NGLE, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_CEIL_L VR4300_BUILD_OP(CP1_CEIL_L, CP1_CEIL_L, INFO3(FPU, FPU, NEEDFS))
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#define CP1_CEIL_W VR4300_BUILD_OP(CP1_CEIL_W, CP1_CEIL_W, INFO3(FPU, FPU, NEEDFS))
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#define CP1_CVT_D VR4300_BUILD_OP(CP1_CVT_D, CP1_CVT_D, INFO3(FPU, FPU, NEEDFS))
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#define CP1_CVT_L VR4300_BUILD_OP(CP1_CVT_L, CP1_CVT_L, INFO3(FPU, FPU, NEEDFS))
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#define CP1_CVT_S VR4300_BUILD_OP(CP1_CVT_S, CP1_CVT_S, INFO3(FPU, FPU, NEEDFS))
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#define CP1_CVT_W VR4300_BUILD_OP(CP1_CVT_W, CP1_CVT_W, INFO3(FPU, FPU, NEEDFS))
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#define CP1_DIV VR4300_BUILD_OP(CP1_DIV, CP1_DIV, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_FLOOR_L VR4300_BUILD_OP(CP1_FLOOR_L, CP1_FLOOR_L, INFO3(FPU, FPU, NEEDFS))
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#define CP1_FLOOR_W VR4300_BUILD_OP(CP1_FLOOR_W, CP1_FLOOR_W, INFO3(FPU, FPU, NEEDFS))
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#define CP1_MOV VR4300_BUILD_OP(CP1_MOV, CP1_MOV, INFO3(FPU, FPU, NEEDFS))
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#define CP1_MUL VR4300_BUILD_OP(CP1_MUL, CP1_MUL, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_NEG VR4300_BUILD_OP(CP1_NEG, CP1_NEG, INFO3(FPU, FPU, NEEDFS))
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#define CP1_ROUND_L VR4300_BUILD_OP(CP1_ROUND_L, CP1_ROUND_L, INFO3(FPU, FPU, NEEDFS))
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#define CP1_ROUND_W VR4300_BUILD_OP(CP1_ROUND_W, CP1_ROUND_W, INFO3(FPU, FPU, NEEDFS))
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#define CP1_SQRT VR4300_BUILD_OP(CP1_SQRT, CP1_SQRT, INFO3(FPU, FPU, NEEDFS))
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#define CP1_SUB VR4300_BUILD_OP(CP1_SUB, CP1_SUB, INFO3(FPU, NEEDFS, NEEDFT))
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#define CP1_TRUNC_L VR4300_BUILD_OP(CP1_TRUNC_L, CP1_TRUNC_L, INFO3(FPU, FPU, NEEDFS))
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#define CP1_TRUNC_W VR4300_BUILD_OP(CP1_TRUNC_W, CP1_TRUNC_W, INFO3(FPU, FPU, NEEDFS))
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#define BC2 VR4300_BUILD_OP(BC1, INVALID, INFO1(BRANCH))
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#define CFC2 VR4300_BUILD_OP(CFC2, INVALID, INFO1(NONE))
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#define CTC2 VR4300_BUILD_OP(CTC2, INVALID, INFO1(NONE))
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#define DMFC2 VR4300_BUILD_OP(DMFC2, INVALID, INFO1(NONE))
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#define DMTC2 VR4300_BUILD_OP(DMTC2, INVALID, INFO1(NONE))
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#define LDC2 VR4300_BUILD_OP(LDC2, INVALID, INFO1(NONE))
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#define LWC2 VR4300_BUILD_OP(LWC2, INVALID, INFO1(NONE))
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#define MFC2 VR4300_BUILD_OP(MFC2, INVALID, INFO1(NONE))
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#define MTC2 VR4300_BUILD_OP(MTC2, INVALID, INFO1(NONE))
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#define SDC2 VR4300_BUILD_OP(SDC2, INVALID, INFO1(NONE))
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#define SWC2 VR4300_BUILD_OP(SWC2, INVALID, INFO1(NONE))
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#endif
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