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8b89df2fdc
Replaced all references to simulation with emulation Updated copyright year Updated .gitignore to reduce chances of random files being uploaded to the repo Added .gitattributes to normalize all text files, and to ignore binary files (which includes the logo and the NEC PDF)
334 lines
15 KiB
C
334 lines
15 KiB
C
//
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// rsp/decoder.c: RSP decoder.
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//
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// CEN64: Cycle-Accurate Nintendo 64 Emulator.
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// Copyright (C) 2015, Tyler J. Stachecki.
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//
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// This file is subject to the terms and conditions defined in
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// 'LICENSE', which is part of this source code package.
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//
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#define RSP_BUILD_OP(op, func, flags) \
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(RSP_OPCODE_##op), (flags)
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#include "common.h"
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#include "rsp/decoder.h"
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#include "rsp/opcodes.h"
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#include "rsp/opcodes_priv.h"
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// ============================================================================
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// Escaped opcode table: Special.
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//
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// 31---------26-----------------------------------------5---------0
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// | SPECIAL/6 | | OPCODE/6|
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// ------6----------------------------------------------------6-----
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 000 | SLL | --- | SRL | SRA | SLLV | --- | SRLV | SRAV |
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// 001 | JR | JALR | --- | --- | --- | BREAK | --- | --- |
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// 010 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 011 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 100 | ADD | ADDU | SUB | SUBU | AND | OR | XOR | NOR |
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// 101 | --- | --- | SLT | SLTU | --- | --- | --- | --- |
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// 110 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 111 | --- | --- | --- | --- | --- | --- | --- | --- |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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//
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// ============================================================================
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cen64_align(static const struct rsp_opcode
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rsp_opcode_table[], CACHE_LINE_SIZE) = {
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{SLL}, {INVALID}, {SRL}, {SRA},
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{SLLV}, {INVALID}, {SRLV}, {SRAV},
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{JR}, {JALR}, {INVALID}, {INVALID},
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{INVALID}, {BREAK}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{ADDU}, {ADDU}, {SUBU}, {SUBU},
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{AND}, {OR}, {XOR}, {NOR},
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{INVALID}, {INVALID}, {SLT}, {SLTU},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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// ============================================================================
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// Escaped opcode table: RegImm.
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//
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// 31---------26----------20-------16------------------------------0
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// | REGIMM/6 | | FMT/5 | |
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// ------6---------------------5------------------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 00 | BLTZ | BGEZ | --- | --- | --- | --- | --- | --- |
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// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 10 |BLTZAL |BGEZAL | --- | --- | --- | --- | --- | --- |
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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//
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// ============================================================================
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{BLTZ}, {BGEZ}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{BLTZAL}, {BGEZAL}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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// ============================================================================
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// Escaped opcode table: COP0.
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//
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// 31--------26-25------21 ----------------------------------------0
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// | COP0/6 | FMT/5 | |
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// ------6----------5-----------------------------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 00 | MFC0 | --- | --- | --- | MTC0 | --- | --- | --- |
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// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 10 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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// ============================================================================
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{MFC0}, {INVALID}, {INVALID}, {INVALID},
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{MTC0}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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// ============================================================================
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// Escaped opcode table: COP2/1.
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//
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// 31--------26-25------21 ----------------------------------------0
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// | COP2/6 | FMT/5 | |
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// ------6----------5-----------------------------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 00 | MFC2 | --- | CFC2 | --- | MTC2 | --- | CTC2 | --- |
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// 01 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 10 | *VECT | *VECT | *VECT | *VECT | *VECT | *VECT | *VECT | *VECT |
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// 11 | *VECT | *VECT | *VECT | *VECT | *VECT | *VECT | *VECT | *VECT |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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//
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// ============================================================================
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{MFC2}, {INVALID}, {CFC2}, {INVALID},
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{MTC2}, {INVALID}, {CTC2}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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// ============================================================================
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// Escaped opcode table: COP2/2.
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//
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// 31---------26---25------------------------------------5---------0
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// | = COP2 | 1 | | FMT/6 |
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// ------6-------1--------------------------------------------6-----
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 000 | VMULF | VMULU | VRNDP | VMULQ | VMUDL | VMUDM | VMUDN | VMUDH |
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// 001 | VMACF | VMACU | VRNDN | VMACQ | VMADL | VMADM | VMADN | VMADH |
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// 010 | VADD | VSUB | --- | VABS | VADDC | VSUBC | --- | --- |
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// 011 | --- | --- | --- | --- | --- | VSAR | --- | --- |
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// 100 | VLT | VEQ | VNE | VGE | VCL | VCH | VCR | VMRG |
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// 101 | VAND | VNAND | VOR | VNOR | VXOR | VNXOR | --- | --- |
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// 110 | VRCP | VRCPL | VRCPH | VMOV | VRSQ | VRSQL | VRSQH | VNOP |
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// 111 | --- | --- | --- | --- | --- | --- | --- | VNULL |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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//
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// ============================================================================
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{VMULF}, {VMULU}, {VRNDP}, {VMULQ},
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{VMUDL}, {VMUDM}, {VMUDN}, {VMUDH},
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{VMACF}, {VMACU}, {VRNDN}, {VMACQ},
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{VMADL}, {VMADM}, {VMADN}, {VMADH},
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{VADD}, {VSUB}, {VINVALID}, {VABS},
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{VADDC}, {VSUBC}, {VINVALID}, {VINVALID},
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{VINVALID}, {VINVALID}, {VINVALID}, {VINVALID},
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{VINVALID}, {VSAR}, {VINVALID}, {VINVALID},
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{VLT}, {VEQ}, {VNE}, {VGE},
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{VCL}, {VCH}, {VCR}, {VMRG},
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{VAND}, {VNAND}, {VOR}, {VNOR},
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{VXOR}, {VNXOR}, {VINVALID}, {VINVALID},
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{VRCP}, {VRCPL}, {VRCPH}, {VMOV},
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{VRSQ}, {VRSQL}, {VRSQH}, {VNOP},
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{VINVALID}, {VINVALID}, {VINVALID}, {VINVALID},
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{VINVALID}, {VINVALID}, {VINVALID}, {VNULL},
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// ============================================================================
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// Escaped opcode table: LWC2.
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//
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// 31---------26-------------------15-------11---------------------0
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// | LWC2/6 | | FUNC/5 | |
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// ------6-----------------------------5----------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 00 | LBV | LSV | LLV | LDV | LQV | LRV | LPV | LUV |
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// 01 | LHV | LFV | --- | LTV | --- | --- | --- | --- |
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// 10 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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//
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// ============================================================================
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{LBV}, {LSV}, {LLV}, {LDV},
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{LQV}, {LRV}, {LPV}, {LUV},
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{LHV}, {LFV}, {INVALID}, {LTV},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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// ============================================================================
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// Escaped opcode table: SWC2.
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//
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// 31---------26-------------------15-------11---------------------0
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// | SWC2/6 | | FMT/5 | |
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// ------6-----------------------------5----------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 00 | SBV | SSV | SLV | SDV | SQV | SRV | SPV | SUV |
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// 01 | SHV | SFV | SWV | STV | --- | --- | --- | --- |
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// 10 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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//
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// ============================================================================
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{SBV}, {SSV}, {SLV}, {SDV},
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{SQV}, {SRV}, {SPV}, {SUV},
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{SHV}, {SFV}, {SWV}, {STV},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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// ============================================================================
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// First-order opcode table.
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//
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// 0b000000 => Lookup in 0.
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// 0b000001 => Lookup in 64.
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// 0b010000 => Lookup in 96.
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// 0b010001 => Lookup in rsp_cop2_opcode_table.
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// 0b110010 => Lookup in 208.
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// 0b111010 => Lookup in 240.
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//
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// 31---------26---------------------------------------------------0
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// | OPCODE/6 | |
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// ------6----------------------------------------------------------
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// |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--|
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// 000 | *SPEC | *RGIM | J | JAL | BEQ | BNE | BLEZ | BGTZ |
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// 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI |
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// 010 | *COP0 | --- | *COP2 | --- | --- | --- | --- | --- |
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// 011 | --- | --- | --- | --- | --- | --- | --- | --- |
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// 100 | LB | LH | --- | LW | LBU | LHU | --- | --- |
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// 101 | SB | SH | --- | SW | --- | --- | --- | --- |
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// 110 | --- | --- | *LWC2 | --- | --- | --- | --- | --- |
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// 111 | --- | --- | *SWC2 | --- | --- | --- | --- | --- |
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// |-------|-------|-------|-------|-------|-------|-------|-------|
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// ============================================================================
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{INVALID}, {INVALID}, {J}, {JAL},
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{BEQ}, {BNE}, {BLEZ}, {BGTZ},
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{ADDIU}, {ADDIU}, {SLTI}, {SLTIU},
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{ANDI}, {ORI}, {XORI}, {LUI},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{LB}, {LH}, {INVALID}, {LW},
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{LBU}, {LHU}, {INVALID}, {INVALID},
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{SB}, {SH}, {INVALID}, {SW},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID},
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{INVALID}, {INVALID}, {INVALID}, {INVALID}
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};
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struct rsp_opcode_escape {
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uint16_t offset;
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uint8_t shift, mask;
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};
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// Escaped table listings. Most of these will never
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// see a processor cache line, so not much waste here.
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cen64_align(static const struct rsp_opcode_escape
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rsp_escape_table[128], CACHE_LINE_SIZE) = {
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{0, 0, 0x3F}, {0, 0, 0x3F},
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{64, 16, 0x1F}, {64, 16, 0x1F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{96, 21, 0x1F}, {96, 21, 0x1F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{128, 21, 0x1F}, {144, 0, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{208, 11, 0x1F}, {208, 11, 0x1F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{240, 11, 0x1F}, {240, 11, 0x1F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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{272, 26, 0x3F}, {272, 26, 0x3F},
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};
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// Decodes an instruction word.
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const struct rsp_opcode* rsp_decode_instruction(uint32_t iw) {
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const struct rsp_opcode_escape *escape = rsp_escape_table + (iw >> 25);
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unsigned index = iw >> escape->shift & escape->mask;
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const struct rsp_opcode* group = rsp_opcode_table + escape->offset;
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return group + index;
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}
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