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Replaced all references to simulation with emulation Updated copyright year Updated .gitignore to reduce chances of random files being uploaded to the repo Added .gitattributes to normalize all text files, and to ignore binary files (which includes the logo and the NEC PDF)
256 lines
8.1 KiB
C
256 lines
8.1 KiB
C
//
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// vr4300/cp0.c: VR4300 system control coprocessor.
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//
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// CEN64: Cycle-Accurate Nintendo 64 Emulator.
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// Copyright (C) 2015, Tyler J. Stachecki.
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//
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// This file is subject to the terms and conditions defined in
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// 'LICENSE', which is part of this source code package.
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//
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#include "common.h"
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#include "tlb/tlb.h"
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#include "vr4300/cp0.h"
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#include "vr4300/cpu.h"
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static const uint64_t vr4300_cp0_reg_masks[32] = {
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0x000000008000003FULL, // 0: VR4300_CP0_REGISTER_INDEX
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0x000000000000003FULL, // 1: VR4300_CP0_REGISTER_RANDOM
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0x000000007FFFFFFFULL, // 2: VR4300_CP0_REGISTER_ENTRYLO0
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0x000000007FFFFFFFULL, // 3: VR4300_CP0_REGISTER_ENTRYLO1
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0xFFFFFFFFFFFFFFF0ULL, // 4: VR4300_CP0_REGISTER_CONTEXT
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0x0000000001FFE000ULL, // 5: VR4300_CP0_REGISTER_PAGEMASK
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0xFFFFFFFFFFFFFFFFULL, // 6: VR4300_CP0_REGISTER_WIRED
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0x000000000000003FULL, // 7:
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0xFFFFFFFFFFFFFFFFULL, // 8: VR4300_CP0_REGISTER_BADVADDR
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0x00000000FFFFFFFFULL, // 9: VR4300_CP0_REGISTER_COUNT
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0xC00000FFFFFFE0FFULL, // 10: VR4300_CP0_REGISTER_ENTRYHI
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0x00000000FFFFFFFFULL, // 11: VR4300_CP0_REGISTER_COMPARE
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0x00000000FFFFFFFFULL, // 12: VR4300_CP0_REGISTER_STATUS
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0x00000000B000FFFFULL, // 13: VR4300_CP0_REGISTER_CAUSE
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0xFFFFFFFFFFFFFFFFULL, // 14: VR4300_CP0_REGISTER_EPC
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0x000000000000FFFFULL, // 15; VR4300_CP0_REGISTER_PRID
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0x000000007FFFFFFFULL, // 16: VR4300_CP0_REGISTER_CONFIG
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0x00000000FFFFFFFFULL, // 17: VR4300_CP0_REGISTER_LLADDR
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0x00000000FFFFFFFBULL, // 18: VR4300_CP0_REGISTER_WATCHLO
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0x000000000000000FULL, // 19: VR4300_CP0_REGISTER_WATCHHI
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0xFFFFFFFFFFFFFFFFULL, // 20: VR4300_CP0_REGISTER_XCONTEXT
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0xFFFFFFFFFFFFFFFFULL, // 21:
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0xFFFFFFFFFFFFFFFFULL, // 22:
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0xFFFFFFFFFFFFFFFFULL, // 23:
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0xFFFFFFFFFFFFFFFFULL, // 24:
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0xFFFFFFFFFFFFFFFFULL, // 25:
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0x0000000000000000ULL, // 26: VR4300_CP0_REGISTER_PARITYERROR
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0x0000000000000000ULL, // 27: VR4300_CP0_REGISTER_CACHEERR
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0x000000000FFFFFC0ULL, // 28: VR4300_CP0_REGISTER_TAGLO
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0x0000000000000000ULL, // 29: VR4300_CP0_REGISTER_TAGHI
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0xFFFFFFFFFFFFFFFFULL, // 30: VR4300_CP0_REGISTER_ERROREPC
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0xFFFFFFFFFFFFFFFFULL, // 31
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};
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static inline uint64_t mask_reg(unsigned reg, uint64_t data) {
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return vr4300_cp0_reg_masks[reg] & data;
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};
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//
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// DMFC0
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//
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int VR4300_DMFC0(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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struct vr4300_exdc_latch *exdc_latch = &vr4300->pipeline.exdc_latch;
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unsigned dest = GET_RT(iw);
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unsigned src = GET_RD(iw);
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if (src == (VR4300_CP0_REGISTER_COUNT - 32)) {
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exdc_latch->result = (uint32_t)
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(vr4300->regs[VR4300_CP0_REGISTER_COUNT] >> 1);
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}
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else
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exdc_latch->result = mask_reg(src, vr4300->regs[32 + src]);
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exdc_latch->dest = dest;
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return 0;
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}
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//
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// DMTC0
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//
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int VR4300_DMTC0(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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unsigned dest = 32 + GET_RD(iw);
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if (dest == VR4300_CP0_REGISTER_COMPARE)
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] &= ~0x8000;
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vr4300->regs[dest] = rt;
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return 0;
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}
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//
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// ERET
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//
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int VR4300_ERET(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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struct vr4300_icrf_latch *icrf_latch = &vr4300->pipeline.icrf_latch;
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struct vr4300_rfex_latch *rfex_latch = &vr4300->pipeline.rfex_latch;
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struct vr4300_exdc_latch *exdc_latch = &vr4300->pipeline.exdc_latch;
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struct vr4300_pipeline *pipeline = &vr4300->pipeline;
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int32_t status = vr4300->regs[VR4300_CP0_REGISTER_STATUS];
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if (status & 0x4) {
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icrf_latch->pc = vr4300->regs[VR4300_CP0_REGISTER_ERROREPC];
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status &= ~0x4;
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}
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else {
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icrf_latch->pc = vr4300->regs[VR4300_CP0_REGISTER_EPC];
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status &= ~0x2;
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}
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// Until we delay CP0 writes, we have to kill ourselves
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// to prevent squashing this instruction the next cycle.
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exdc_latch->common.fault = ~0;
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rfex_latch->common.fault = ~0;
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vr4300->regs[PIPELINE_CYCLE_TYPE] = 4;
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pipeline->exception_history = 0;
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pipeline->fault_present = true;
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vr4300->regs[VR4300_CP0_REGISTER_STATUS] = status;
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pipeline->icrf_latch.segment = get_segment(icrf_latch->pc, status);
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pipeline->exdc_latch.segment = get_default_segment();
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// vr4300->llbit = 0;
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return 1;
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}
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//
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// MFC0
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//
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int VR4300_MFC0(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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struct vr4300_exdc_latch *exdc_latch = &vr4300->pipeline.exdc_latch;
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unsigned dest = GET_RT(iw);
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unsigned src = GET_RD(iw);
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if (src == (VR4300_CP0_REGISTER_COUNT - 32)) {
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exdc_latch->result = (uint32_t)
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(vr4300->regs[VR4300_CP0_REGISTER_COUNT] >> 1);
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}
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else
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exdc_latch->result = mask_reg(src, vr4300->regs[32 + src]);
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exdc_latch->dest = (int32_t) dest;
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return 0;
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}
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//
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// MTC0
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//
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int VR4300_MTC0(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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struct vr4300_icrf_latch *icrf_latch = &vr4300->pipeline.icrf_latch;
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struct vr4300_exdc_latch *exdc_latch = &vr4300->pipeline.exdc_latch;
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unsigned dest = 32 + GET_RD(iw);
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if (dest == VR4300_CP0_REGISTER_COMPARE)
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vr4300->regs[VR4300_CP0_REGISTER_CAUSE] &= ~0x8000;
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else if (dest == VR4300_CP0_REGISTER_STATUS) {
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icrf_latch->segment = get_segment(icrf_latch->common.pc, rt);
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exdc_latch->segment = get_default_segment();
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}
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vr4300->regs[dest] = (int32_t) rt;
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return 0;
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}
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//
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// TLBP
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//
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int VR4300_TLBP(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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uint64_t entry_hi = mask_reg(10, vr4300->regs[VR4300_CP0_REGISTER_ENTRYHI]);
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unsigned index;
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vr4300->regs[VR4300_CP0_REGISTER_INDEX] |= 0x80000000U;
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if (!tlb_probe(&vr4300->cp0.tlb, entry_hi, entry_hi & 0xFF, &index))
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vr4300->regs[VR4300_CP0_REGISTER_INDEX] = index;
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return 0;
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}
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//
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// TLBR
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//
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int VR4300_TLBR(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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unsigned index = vr4300->regs[VR4300_CP0_REGISTER_INDEX] & 0x3F;
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uint64_t entry_hi;
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uint32_t page_mask = (vr4300->cp0.page_mask[index] << 1) & 0x1FFE000U;
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uint32_t pfn0 = vr4300->cp0.pfn[index][0];
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uint32_t pfn1 = vr4300->cp0.pfn[index][1];
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uint8_t state0 = vr4300->cp0.state[index][0];
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uint8_t state1 = vr4300->cp0.state[index][1];
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tlb_read(&vr4300->cp0.tlb, index, &entry_hi);
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vr4300->regs[VR4300_CP0_REGISTER_ENTRYHI] = entry_hi;
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vr4300->regs[VR4300_CP0_REGISTER_ENTRYLO0] = (pfn0 >> 6) | state0;
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vr4300->regs[VR4300_CP0_REGISTER_ENTRYLO1] = (pfn1 >> 6) | state1;
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vr4300->regs[VR4300_CP0_REGISTER_PAGEMASK] = page_mask;
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return 0;
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}
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//
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// TLBWI
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//
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int VR4300_TLBWI(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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uint64_t entry_hi = mask_reg(10, vr4300->regs[VR4300_CP0_REGISTER_ENTRYHI]);
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uint64_t entry_lo_0 = mask_reg(2, vr4300->regs[VR4300_CP0_REGISTER_ENTRYLO0]);
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uint64_t entry_lo_1 = mask_reg(3, vr4300->regs[VR4300_CP0_REGISTER_ENTRYLO1]);
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uint32_t page_mask = mask_reg(5, vr4300->regs[VR4300_CP0_REGISTER_PAGEMASK]);
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unsigned index = vr4300->regs[VR4300_CP0_REGISTER_INDEX] & 0x3F;
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tlb_write(&vr4300->cp0.tlb, index, entry_hi, entry_lo_0, entry_lo_1, page_mask);
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vr4300->cp0.page_mask[index] = (page_mask | 0x1FFF) >> 1;
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vr4300->cp0.pfn[index][0] = (entry_lo_0 << 6) & ~0xFFFU;
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vr4300->cp0.pfn[index][1] = (entry_lo_1 << 6) & ~0xFFFU;
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vr4300->cp0.state[index][0] = entry_lo_0 & 0x3F;
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vr4300->cp0.state[index][1] = entry_lo_1 & 0x3F;
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return 0;
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}
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//
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// TLBWR
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//
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int VR4300_TLBWR(struct vr4300 *vr4300,
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uint32_t iw, uint64_t rs, uint64_t rt) {
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uint64_t entry_hi = mask_reg(10, vr4300->regs[VR4300_CP0_REGISTER_ENTRYHI]);
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uint64_t entry_lo_0 = mask_reg(2, vr4300->regs[VR4300_CP0_REGISTER_ENTRYLO0]);
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uint64_t entry_lo_1 = mask_reg(3, vr4300->regs[VR4300_CP0_REGISTER_ENTRYLO1]);
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uint32_t page_mask = mask_reg(5, vr4300->regs[VR4300_CP0_REGISTER_PAGEMASK]);
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unsigned index = vr4300->regs[VR4300_CP0_REGISTER_WIRED] & 0x3F;
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index = rand() % (32 - index) + index;
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tlb_write(&vr4300->cp0.tlb, index, entry_hi, entry_lo_0, entry_lo_1, page_mask);
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vr4300->cp0.page_mask[index] = (page_mask | 0x1FFF) >> 1;
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vr4300->cp0.pfn[index][0] = (entry_lo_0 << 6) & ~0xFFFU;
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vr4300->cp0.pfn[index][1] = (entry_lo_1 << 6) & ~0xFFFU;
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vr4300->cp0.state[index][0] = entry_lo_0 & 0x3F;
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vr4300->cp0.state[index][1] = entry_lo_1 & 0x3F;
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return 0;
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}
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// Initializes the coprocessor.
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void vr4300_cp0_init(struct vr4300 *vr4300) {
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tlb_init(&vr4300->cp0.tlb);
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}
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