mirror of
https://github.com/n64dev/cen64.git
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c4afd44ed7
Replaced all references to simulation with emulation Updated copyright year Updated .gitignore to reduce chances of random files being uploaded to the repo Added .gitattributes to normalize all text files, and to ignore binary files (which includes the logo and the NEC PDF)
251 lines
7.7 KiB
C
251 lines
7.7 KiB
C
//
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// dd/controller.c: DD controller.
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//
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// CEN64: Cycle-Accurate Nintendo 64 Emulator.
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// Copyright (C) 2015, Tyler J. Stachecki.
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//
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// This file is subject to the terms and conditions defined in
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// 'LICENSE', which is part of this source code package.
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//
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//
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// Thanks go out to OzOnE and Luigiblood (Seru-kun) for reverse
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// engineering, documenting, and assisting with the reversal of
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// this device!
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//
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//
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// TODO: Currently, the DD IPL spams the controller with DD_CMD_NOOP.
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// This is normal. Once you signify that a disk is present (using the
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// DD_STATUS_DISK_PRES), the DD IPL attempts to start performing seeks.
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//
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#include "common.h"
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#include "bus/address.h"
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#include "bus/controller.h"
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#include "dd/controller.h"
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#include "vr4300/interface.h"
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#ifdef DEBUG_MMIO_REGISTER_ACCESS
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const char *dd_register_mnemonics[NUM_DD_REGISTERS] = {
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#define X(reg) #reg,
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#include "dd/registers.md"
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#undef X
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};
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#endif
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// ASIC_CMD_STATUS flags.
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#define DD_CMD_NOOP 0x00000000U
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#define DD_CMD_SEEK_READ 0x00010001U
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#define DD_CMD_SEEK_WRITE 0x00020001U
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#define DD_CMD_RECALIBRATE 0x00030001U // ???
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#define DD_CMD_SLEEP 0x00040000U
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#define DD_CMD_START 0x00050001U
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#define DD_CMD_SET_STANDBY 0x00060000U
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#define DD_CMD_SET_SLEEP 0x00070000U
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#define DD_CMD_CLR_DSK_CHNG 0x00080000U
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#define DD_CMD_CLR_RESET 0x00090000U
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#define DD_CMD_READ_VERSION 0x000A0000U
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#define DD_CMD_SET_DISK_TYPE 0x000B0001U
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#define DD_CMD_REQUEST_STATUS 0x000C0000U
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#define DD_CMD_STANDBY 0x000D0000U
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#define DD_CMD_IDX_LOCK_RETRY 0x000E0000U // ???
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#define DD_CMD_SET_YEAR_MONTH 0x000F0000U
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#define DD_CMD_SET_DAY_HOUR 0x00100000U
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#define DD_CMD_SET_MIN_SEC 0x00110000U
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#define DD_CMD_GET_YEAR_MONTH 0x00120000U
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#define DD_CMD_GET_DAY_HOUR 0x00130000U
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#define DD_CMD_GET_MIN_SEC 0x00140000U
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#define DD_CMD_FEATURE_INQ 0x001B0000U
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#define DD_STATUS_DATA_RQ 0x40000000U
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#define DD_STATUS_C2_XFER 0x10000000U
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#define DD_STATUS_BM_ERR 0x08000000U
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#define DD_STATUS_BM_INT 0x04000000U
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#define DD_STATUS_MECHA_INT 0x02000000U
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#define DD_STATUS_DISK_PRES 0x01000000U
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#define DD_STATUS_BUSY_STATE 0x00800000U
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#define DD_STATUS_RST_STATE 0x00400000U
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#define DD_STATUS_MTR_N_SPIN 0x00100000U
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#define DD_STATUS_HEAD_RTRCT 0x00080000U
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#define DD_STATUS_WR_PR_ERR 0x00040000U
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#define DD_STATUS_MECHA_ERR 0x00020000U
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#define DD_STATUS_DISK_CHNG 0x00010000U
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// ASIC_BM_STATUS_CTL flags.
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#define DD_BM_STATUS_RUNNING 0x00000000U
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#define DD_BM_STATUS_ERROR 0x04000000U
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#define DD_BM_STATUS_MICRO 0x02000000U // ???
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#define DD_BM_STATUS_BLOCK 0x01000000U
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#define DD_BM_STATUS_C1CRR 0x00800000U
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#define DD_BM_STATUS_C1DBL 0x00400000U
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#define DD_BM_STATUS_C1SNG 0x00200000U
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#define DD_BM_STATUS_C1ERR 0x00010000U // Typo ???
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#define DD_BM_CTL_START 0x80000000U
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#define DD_BM_CTL_MNGRMODE 0x40000000U
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#define DD_BM_CTL_INTMASK 0x20000000U
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#define DD_BM_CTL_RESET 0x10000000U
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#define DD_BM_CTL_DIS_OR_CHK 0x08000000U // ???
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#define DD_BM_CTL_DIS_C1_CRR 0x04000000U
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#define DD_BM_CTL_BLK_TRANS 0x02000000U
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#define DD_BM_CTL_MECHA_RST 0x01000000U
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// Initializes the DD.
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int dd_init(struct dd_controller *dd, struct bus_controller *bus,
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const uint8_t *ddipl, const uint8_t *ddrom, size_t ddrom_size) {
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dd->bus = bus;
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dd->ipl_rom = ddipl;
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dd->rom = ddrom;
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dd->rom_size = ddrom_size;
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return 0;
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}
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// Reads a word from the DD MMIO register space.
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int read_dd_regs(void *opaque, uint32_t address, uint32_t *word) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_REGS_BASE_ADDRESS;
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enum dd_register reg = (offset >> 2);
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*word = dd->regs[reg];
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debug_mmio_read(dd, dd_register_mnemonics[reg], *word);
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return 0;
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}
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// Writes a word to the DD MMIO register space.
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int write_dd_regs(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_REGS_BASE_ADDRESS;
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enum dd_register reg = (offset >> 2);
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debug_mmio_write(dd, dd_register_mnemonics[reg], word, dqm);
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// Command register written: do something.
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if (reg == DD_ASIC_CMD_STATUS) {
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// Get time [minute/second]:
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if (word == DD_CMD_GET_MIN_SEC) {
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// dd->regs[DD_ASIC_DATA] = ...
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}
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else if (word == DD_CMD_GET_DAY_HOUR) {
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// dd->regs[DD_ASIC_DATA] = ...
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}
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else if (word == DD_CMD_GET_YEAR_MONTH) {
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// dd->regs[DD_ASIC_DATA] = ...
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}
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else if (word == DD_CMD_CLR_RESET)
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dd->regs[DD_ASIC_CMD_STATUS] &= ~DD_STATUS_RST_STATE;
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// Always signal an interrupt in response.
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dd->regs[DD_ASIC_CMD_STATUS] |= DD_STATUS_MECHA_INT;
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signal_dd_interrupt(dd->bus->vr4300);
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}
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// Buffer manager control request: handle it.
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else if (reg == DD_ASIC_BM_STATUS_CTL) {
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if (word == DD_BM_CTL_RESET)
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dd->regs[DD_ASIC_BM_STATUS_CTL] &= ~DD_BM_CTL_INTMASK;
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else if (word == DD_BM_CTL_MECHA_RST)
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dd->regs[DD_ASIC_CMD_STATUS] &= ~DD_STATUS_MECHA_INT;
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clear_dd_interrupt(dd->bus->vr4300);
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}
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// This is done by the IPL and a lot of games. The only word
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// ever know to be written to this register is 0xAAAA0000.
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else if (reg == DD_ASIC_HARD_RESET) {
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assert(word == 0xAAAA0000 && "dd: Hard reset without magic word?");
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dd->regs[DD_ASIC_CMD_STATUS] = DD_STATUS_RST_STATE;
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}
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else {
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dd->regs[reg] &= ~dqm;
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dd->regs[reg] |= word;
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}
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return 0;
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}
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// Reads a word from the DD IPL ROM.
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int read_dd_ipl_rom(void *opaque, uint32_t address, uint32_t *word) {
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uint32_t offset = address - DD_IPL_ROM_ADDRESS;
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struct dd_controller *dd = (struct dd_controller*) opaque;
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if (!dd->ipl_rom)
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memset(word, 0, sizeof(*word));
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else {
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memcpy(word, dd->ipl_rom + offset, sizeof(*word));
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*word = byteswap_32(*word);
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}
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//debug_mmio_read(dd, "DD_IPL_ROM", *word);
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return 0;
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}
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// Writes a word to the DD IPL ROM.
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int write_dd_ipl_rom(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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assert(0 && "Attempt to write to DD IPL ROM.");
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return 0;
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}
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// Reads a word from the DD C2S buffer.
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int read_dd_c2s_buffer(void *opaque, uint32_t address, uint32_t *word) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_C2S_BUFFER_ADDRESS;
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debug_mmio_read(dd, "DD_C2S_BUFFER", *word);
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return 0;
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}
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// Writes a word to the DD C2S BUFFER.
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int write_dd_c2s_buffer(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_C2S_BUFFER_ADDRESS;
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debug_mmio_write(dd, "DD_C2S_BUFFER", word, dqm);
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return 0;
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}
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// Reads a word from the DD DS buffer.
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int read_dd_ds_buffer(void *opaque, uint32_t address, uint32_t *word) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_DS_BUFFER_ADDRESS;
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debug_mmio_read(dd, "DD_DS_BUFFER", *word);
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return 0;
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}
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// Writes a word to the DD DS BUFFER.
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int write_dd_ds_buffer(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_DS_BUFFER_ADDRESS;
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debug_mmio_write(dd, "DD_DS_BUFFER", word, dqm);
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return 0;
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}
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// Reads a word from the DD MS RAM.
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int read_dd_ms_ram(void *opaque, uint32_t address, uint32_t *word) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_MS_RAM_ADDRESS;
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debug_mmio_read(dd, "DD_MS_RAM", *word);
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return 0;
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}
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// Writes a word to the DD MS RAM.
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int write_dd_ms_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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unsigned offset = address - DD_MS_RAM_ADDRESS;
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debug_mmio_write(dd, "DD_MS_RAM", word, dqm);
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return 0;
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}
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