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Author SHA1 Message Date
Tyler Stachecki
ba2ca6f427 Fix more byte-ordering issues. This was hard. 2014-10-24 23:43:24 -04:00
Tyler Stachecki
2a90218af5 Require SSSE3 until we get SSE2 back in order. 2014-10-24 21:38:39 -04:00
Tyler Stachecki
1292220694 Fix a byte-ordering issue in the x86_64 RSP backend. 2014-10-24 21:27:18 -04:00
Tyler Stachecki
e63b13605e Various LWC2/SWC2 fixes, add VSAR. 2014-10-24 21:07:25 -04:00
Tyler Stachecki
97587e3811 Add guards around SSSE3 version of rsp_vstore_dmem. 2014-10-24 18:34:36 -04:00
Tyler Stachecki
f395be631e Start adding in support for LWC2/SWC2 ops: LQV/SQV. 2014-10-24 18:31:13 -04:00
Tyler Stachecki
d0eb4d4532 Optimize (and fix a bug in) uncached reads. 2014-10-23 09:40:47 -04:00
Tyler Stachecki
5b49bb470d More branch folding: this time, loads. 2014-10-22 18:47:27 -04:00
Tyler Stachecki
e9e82b9b22 Fix a compilation error in the last commit. 2014-10-22 18:17:30 -04:00
Tyler Stachecki
519f59f429 Start implementing some vector operators. 2014-10-22 18:15:44 -04:00
Tyler Stachecki
1061cec86b Lots of branch folding in the LD/ST aligner. 2014-10-22 18:11:50 -04:00
Tyler Stachecki
620c1cbec5 Add SSE2 support to arch/x86_64/rsp. 2014-10-21 18:39:26 -04:00
Tyler Stachecki
8ccf4eca32 Add writes to RDP space from RSP CP0. 2014-10-20 13:20:09 -04:00
Tyler Stachecki
62ebbd8c54 Fix a typo (wrong enumeration). 2014-10-20 12:58:50 -04:00
Tyler Stachecki
b9ed6920c4 Implement multicycle instruction delays. 2014-10-20 12:55:20 -04:00
Tyler Stachecki
b245149f3e Optimize out a store, add a safety net. 
Not sure whether or not both destination register variables need
to be waxed during a faulted stage, but I imagine so.
 2014-10-20 08:41:04 -04:00
Tyler Stachecki
2079549cc5 Hoist assignment/store to assist optimizations. 2014-10-20 08:26:27 -04:00
Tyler Stachecki
4c2b49c779 Assist optimizations by changing a macro'd value. 2014-10-20 08:10:32 -04:00
Tyler Stachecki
ab8687e263 Remove an unnecessary pair of RF writes. 
We always write to $0 during bypass logic to make sure that a
forwarded value, regardless of it's desination, never alters the
value of $0. Therefore, writing it to the RF as shown here is not
strictly necessary.
 2014-10-20 07:42:07 -04:00
Tyler Stachecki
715f075088 Micro-optimization: Make LDI checks cheaper. 2014-10-19 14:15:49 -04:00
Tyler Stachecki
4f359d3ded Restructure main loop to assist in optimization. 2014-10-19 14:06:52 -04:00
Tyler Stachecki
69b810cfaa Silence an unused variable warning. 2014-10-18 12:31:28 -04:00
Tyler Stachecki
9dc2a36313 Remove some RSP debugging code and sloppyness. 2014-10-18 12:30:36 -04:00
Tyler Stachecki
749b3906c9 Fix RSP DMEM endian issues and load-use code. 2014-10-18 12:26:03 -04:00
Tyler Stachecki
421b0e0519 Implement some RSP DMEM reads and writes. 2014-10-18 11:34:09 -04:00
Tyler Stachecki
4ff41a0e34 Fix DMA/interrupt issues with the RSP. 2014-10-18 11:34:02 -04:00
Tyler Stachecki
df68d13733 FIx some PC-related bugs in the RSP. 2014-10-18 11:33:56 -04:00
Tyler Stachecki
f5dc940dee Prevent the RSP from hanging the IPL. 2014-10-18 11:33:51 -04:00
Tyler Stachecki
0eea4f213e Start fleshing out the RSP backend. 2014-10-18 11:33:44 -04:00
Tyler Stachecki
f021614648 Make sure LDI is triggered under the correct conditions. 
We need to trigger LDI on consumption of sources that are
heading into the DC stage, not coming out of it.
 2014-10-18 11:33:37 -04:00
Tyler Stachecki
b421093700 Start fleshing out the RSP frontend. 2014-10-18 11:33:14 -04:00
Tyler Stachecki
f520f6e9b8 Start fleshing out the RSP pipeline. 2014-10-18 11:33:04 -04:00
Tyler Stachecki
7ac625cec1 Implement RSP DMAs, COP0 registers, etc. 2014-10-18 11:32:51 -04:00
Tyler Stachecki
440c51fef2 Add modified functions for RSP. 2014-10-18 11:32:43 -04:00
Tyler Stachecki
71961f0b00 Implement the RSP decoder. 2014-10-18 11:32:36 -04:00
Tyler Stachecki
b20b138d99 Add the RSP opcode entries. 2014-10-18 11:32:27 -04:00
Tyler Stachecki
f569e5f839 Fix bug that produced false-positive error codes. 2014-10-18 09:20:19 -04:00
Tyler Stachecki
e9a24f09d6 Patch some undefined behaviour. 
Cast to an unsigned type before shifting to avoid shifting a
negative value to the left. Unlikely to impact integrity of
generated code; more of a correctness commit.
 2014-10-17 08:49:14 -04:00
Tyler Stachecki
62a5d5807b Fix Clang x86(_64) builds, add AddressSanitizer to debug. 2014-10-17 08:45:34 -04:00
Tyler Stachecki
7ed4d51b01 Use signed types for DMULT. 
Thanks, krom!
 2014-10-04 22:29:18 -04:00
Tyler Stachecki
971bcd131b Prevent namespace collisions. 2014-09-04 13:45:57 -04:00
Tyler Stachecki
6c4d9569d3 arch/x86_64: Fix a precedence issue in tlb_read. 2014-09-04 13:30:42 -04:00
Tyler Stachecki
62f452b4ab Fix an error in the SDL/SDR implementation. 2014-08-31 13:13:27 -04:00
Tyler Stachecki
d7aaff460d Fix a potential issue in the last commit. 
request->size need not be >= 4 for SDL/SDR; fix it.
 2014-08-31 12:11:29 -04:00
Tyler Stachecki
17010317ab Implement SDL/SDR. 2014-08-31 11:59:52 -04:00
Tyler Stachecki
e58dc2cef2 Add/adjust C-pad and D-pad, sensitivity mappings. 2014-08-30 14:58:28 -04:00
Tyler Stachecki
b921f65710 os/unix: Detect and delete auto-repeated keypresses. 
Ignore auto-repeat KeyPress and KeyRelease events sent by X11.
Thanks go out to Nacho for originally reporting this bug.
 2014-08-30 11:57:41 -04:00
Tyler Stachecki
1e0b850ef5 Add a missing break statement. 2014-08-28 22:50:51 -04:00
Tyler Stachecki
aba60c487b Flip backwards controls, remove memory delay hack. 2014-08-27 23:22:18 -04:00
Tyler Stachecki
0d15bd9ddc Add some preliminary input support. 2014-08-27 23:13:08 -04:00