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https://github.com/n64dev/cen64.git
synced 2024-06-22 05:52:37 -04:00
fix all build warnings, does not affect functionality
This commit is contained in:
parent
1d41bb8808
commit
73f4420a4c
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@ -10,8 +10,6 @@
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#include "common.h"
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#include "ai/context.h"
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#include <AL/al.h>
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#include <AL/alc.h>
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// Creates and initializes an audio context.
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int ai_context_create(struct cen64_ai_context *context) {
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@ -55,7 +55,7 @@ __m128i rsp_vrcp_vrsq(struct rsp *rsp, uint32_t iw, int dp,
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// VRSQ
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if (iw & 0x4) {
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idx = (((unsigned long long) data << shift) & 0x7FC00000U) >> 22;
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idx = (idx | 0x200) & 0x3FE | (shift % 2);
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idx = ((idx | 0x200) & 0x3FE) | (shift % 2);
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result = rsp_reciprocal_rom[idx];
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result = ((0x10000 | result) << 14) >> ((31 - shift) >> 1);
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@ -65,7 +65,7 @@ __m128i rsp_vrsq(struct rsp *rsp, int dp,
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#endif
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idx = (((unsigned long long) data << shift) & 0x7FC00000U) >> 22;
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idx = (idx | 0x200) & 0x3FE | (shift % 2);
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idx = ((idx | 0x200) & 0x3FE) | (shift % 2);
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result = rsp_reciprocal_rom[idx];
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result = ((0x10000 | result) << 14) >> ((31 - shift) >> 1);
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@ -77,7 +77,7 @@ int bus_init(struct bus_controller *bus) {
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bus->ri,
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bus->rsp,
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bus->rsp,
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bus->pi
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bus->pi,
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};
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create_memory_map(&bus->map);
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2
cen64.c
2
cen64.c
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@ -33,7 +33,7 @@ cen64_cold static CEN64_THREAD_RETURN_TYPE run_device_thread(void *opaque);
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// Called when another simulation instance is desired.
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int cen64_main(int argc, const char **argv) {
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struct controller controller[4] = { { NULL, }, };
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struct controller controller[4] = { { 0, }, };
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struct cen64_options options = default_cen64_options;
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options.controller = controller;
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struct rom_file ddipl, ddrom, pifrom, cart;
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@ -390,9 +390,7 @@ int write_dd_ipl_rom(void *opaque, uint32_t address, uint32_t word, uint32_t dqm
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}
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// Reads a word from the DD C2S/DS buffer.
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int read_dd_controller(void *opaque, uint32_t address, uint32_t *word) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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int read_dd_controller(void *opaque __attribute__ ((unused)), uint32_t address, uint32_t *word) {
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// XXX: Hack to reduce memorymap entries.
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if (address >= DD_MS_RAM_ADDRESS)
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return read_dd_ms_ram(opaque, address, word);
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@ -406,9 +404,7 @@ int read_dd_controller(void *opaque, uint32_t address, uint32_t *word) {
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}
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// Writes a word to the DD C2S/DS BUFFER.
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int write_dd_controller(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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int write_dd_controller(void *opaque __attribute__ ((unused)), uint32_t address, uint32_t word, uint32_t dqm) {
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// XXX: Hack to reduce memorymap entries.
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if (address >= DD_MS_RAM_ADDRESS)
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return write_dd_ms_ram(opaque, address, word, dqm);
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@ -422,17 +418,13 @@ int write_dd_controller(void *opaque, uint32_t address, uint32_t word, uint32_t
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}
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// Reads a word from the DD MS RAM.
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int read_dd_ms_ram(void *opaque, uint32_t address, uint32_t *word) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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int read_dd_ms_ram(void *opaque __attribute__ ((unused)), uint32_t address, uint32_t *word) {
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debug_mmio_read(dd, "DD_MS_RAM", *word);
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return 0;
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}
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// Writes a word to the DD MS RAM.
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int write_dd_ms_ram(void *opaque, uint32_t address, uint32_t word, uint32_t dqm) {
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struct dd_controller *dd = (struct dd_controller *) opaque;
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int write_dd_ms_ram(void *opaque __attribute__ ((unused)), uint32_t address, uint32_t word, uint32_t dqm) {
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debug_mmio_write(dd, "DD_MS_RAM", word, dqm);
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return 0;
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}
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@ -24,7 +24,7 @@ const struct cen64_options default_cen64_options = {
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0, // eeprom_size
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NULL, // sram_path
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NULL, // flashram_path
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{ { NULL, }, }, // controller
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NULL, // controller
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#ifdef _WIN32
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false, // console
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#endif
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@ -130,7 +130,7 @@ int parse_options(struct cen64_options *options, int argc, const char *argv[]) {
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else if (!strcmp(argv[i], "-controller")) {
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int num;
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struct controller opt = { NULL, };
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struct controller opt = { 0, };
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if ((i + 1) >= (argc - 1)) {
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printf("-controller requires a controller description.\n\n");
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@ -285,7 +285,7 @@ extern void sha1(data, size, digest)
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size_t size;
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uint8_t *digest;
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{
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struct sha1_ctxt ctx = { 0, };
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struct sha1_ctxt ctx;
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sha1_init(&ctx);
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sha1_loop(&ctx, data, size);
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sha1_result(&ctx, digest);
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@ -49,8 +49,8 @@ struct pi_controller {
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const uint8_t *rom;
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size_t rom_size;
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struct save_file *sram;
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struct save_file *flashram_file;
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const struct save_file *sram;
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const struct save_file *flashram_file;
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struct flashram flashram;
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uint64_t counter;
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@ -42,7 +42,7 @@ static int eeprom_write(struct eeprom *eeprom, uint8_t *send_buf, uint8_t send_b
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// Initializes the SI.
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int si_init(struct si_controller *si, struct bus_controller *bus,
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const uint8_t *pif_rom, const uint8_t *cart_rom, bool dd_present,
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const uint8_t *eeprom, size_t eeprom_size,
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uint8_t *eeprom, size_t eeprom_size,
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const struct controller *controller) {
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uint32_t cic_seed;
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@ -46,7 +46,7 @@ struct si_controller {
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cen64_cold int si_init(struct si_controller *si, struct bus_controller *bus,
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const uint8_t *pif_rom, const uint8_t *cart_rom, bool dd_present,
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const uint8_t *eeprom, size_t eeprom_size,
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uint8_t *eeprom, size_t eeprom_size,
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const struct controller *controller);
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int read_pif_rom_and_ram(void *opaque, uint32_t address, uint32_t *word);
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14
si/pak.c
14
si/pak.c
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@ -68,13 +68,15 @@ int controller_pak_write(struct controller *controller,
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else if (controller->pak == PAK_RUMBLE) {
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if (address == 0xC000) {
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if (send_buf[3] == 0x01)
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; // printf("Enable rumble\n");
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else
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; // printf("Disable rumble\n");
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if (send_buf[3] == 0x01) {
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// printf("Enable rumble\n");
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} else {
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// printf("Disable rumble\n");
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}
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}
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else {
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// printf("Unknown rumble address\n");
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}
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else
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; // printf("Unknown rumble address\n");
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}
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else if (controller->pak == PAK_TRANSFER)
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@ -19,7 +19,7 @@
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// Creates a rendering window/context for the VI controller.
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int vi_create_window(struct vi_controller *vi) {
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struct cen64_gl_hints hints = cen64_default_gl_hints;
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struct cen64_gl_config *config;
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cen64_gl_config *config;
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int num_matching;
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// Create a window for rendering. If we're successful,
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