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https://github.com/bsnes-emu/bsnes.git
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a266a2b5e2
Major features in this release are: serial controller emulation, a brand new scheduler that supports multiple simultaneous coprocessors, and accuracy improvements. The serial controller is something devised by blargg. With the proper voltage adjustments (5v-9v), it is possible to wire an SNES controller to a serial port, which can then be used for bidirectional communication between the SNES, and (usually, but not only) a PC. The support in bsnes was added so that such programs could be debugged and ran from within an emulator, and not just on real hardware. The scheduler rewrite was meant to allow the combination of coprocessors. It was specifically meant to allow the serial controller thread to run alongside the SuperFX and SA-1 coprocessor threads, but it also allows fun things like MSU1 support in SuperFX and SA-1 games, and even creating dev cartridges that utilize both the SuperFX and SA-1 at the same time. The one thing not yet allowed is running multiple instances of the exact same coprocessor at the same time, as this is due to design constraints favoring code inlining. There are two important accuracy updates. The first is that when PAL video mode is used without being in overscan mode, black bars are shown. Emulators have always shown this black bar at the bottom of the screen, but this is actually incorrect. resxto took pictures from his PAL TV that shows the image is in fact vertically centered in the screen. bsnes has been updated to reflect this. Also interesting is that I have backported some code from the dot-based PPU renderer. In the game Uniracers, it writes to OAM during Hblank, and expects the write to go to a specific address. In previous releases, that address was hard-coded to go to the required memory location. But the way the hardware really works is that the write goes to the extended attribute address for the last sprite that the PPU fetched, as the PPU is still asserting the OAM address bus. Now, due to the precision limitations, I was not able to also port timing access during the active display period. However, this is sufficient to at least remove the last global hack from the older, speed-focused scanline renderer.
210 lines
5.7 KiB
C++
210 lines
5.7 KiB
C++
/*
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Copyright (C) 2005-2007 NSRT Team ( http://nsrt.edgeemu.com )
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Copyright (C) 2002 Andrea Mazzoleni ( http://advancemame.sf.net )
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Copyright (C) 2001-4 Igor Pavlov ( http://www.7-zip.org )
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License version 2.1 as published by the Free Software Foundation.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __IINOUTSTREAMS_H
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#define __IINOUTSTREAMS_H
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#include <string>
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#include <fstream>
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#include "portable.h"
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class ISequentialInStream
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{
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public:
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virtual HRESULT Read(void *, UINT32, UINT32 *) = 0;
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virtual ~ISequentialInStream() {}
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};
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class ISequentialInStream_Array : public ISequentialInStream
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{
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const char *data;
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unsigned int size;
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public:
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ISequentialInStream_Array(const char *Adata, unsigned Asize) : data(Adata), size(Asize) { }
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HRESULT Read(void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialInStream_Array() {}
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};
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class ISequentialInStream_String : public ISequentialInStream
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{
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std::string& data;
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public:
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ISequentialInStream_String(std::string& Adata) : data(Adata) { }
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HRESULT Read(void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialInStream_String() {}
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};
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class ISequentialInStream_Istream : public ISequentialInStream
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{
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std::istream& data;
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public:
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ISequentialInStream_Istream(std::istream& Adata) : data(Adata) { }
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HRESULT Read(void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialInStream_Istream() {}
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};
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class ISequentialOutStream
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{
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public:
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virtual bool overflow_get() const = 0;
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virtual unsigned int size_get() const = 0;
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virtual HRESULT Write(const void *, UINT32, UINT32 *) = 0;
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virtual ~ISequentialOutStream() {}
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};
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class ISequentialOutStream_Array : public ISequentialOutStream
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{
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char *data;
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unsigned int size;
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bool overflow;
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unsigned int total;
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public:
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ISequentialOutStream_Array(char *Adata, unsigned Asize) : data(Adata), size(Asize), overflow(false), total(0) { }
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bool overflow_get() const { return(overflow); }
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unsigned int size_get() const { return(total); }
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HRESULT Write(const void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialOutStream_Array() {}
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};
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class ISequentialOutStream_String : public ISequentialOutStream
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{
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std::string& data;
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unsigned int total;
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public:
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ISequentialOutStream_String(std::string& Adata) : data(Adata), total(0) { }
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bool overflow_get() const { return(false); }
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unsigned int size_get() const { return(total); }
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HRESULT Write(const void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialOutStream_String() {}
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};
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class ISequentialOutStream_Ostream : public ISequentialOutStream
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{
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std::ostream& data;
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unsigned int total;
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public:
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ISequentialOutStream_Ostream(std::ostream& Adata) : data(Adata), total(0) { }
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bool overflow_get() const { return(false); }
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unsigned int size_get() const { return(total); }
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HRESULT Write(const void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialOutStream_Ostream() {}
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};
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class ISequentialStreamCRC32
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{
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protected:
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unsigned int crc32;
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public:
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ISequentialStreamCRC32() : crc32(0) {}
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unsigned int crc32_get() const { return(crc32); }
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virtual ~ISequentialStreamCRC32() {}
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};
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class ISequentialInStreamCRC32_Array : public ISequentialInStream_Array, public ISequentialStreamCRC32
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{
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public:
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ISequentialInStreamCRC32_Array(const char *Adata, unsigned Asize) : ISequentialInStream_Array(Adata, Asize) { }
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HRESULT Read(void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialInStreamCRC32_Array() {}
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};
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class ISequentialInStreamCRC32_String : public ISequentialInStream_String, public ISequentialStreamCRC32
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{
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public:
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ISequentialInStreamCRC32_String(std::string& Adata) : ISequentialInStream_String(Adata) { }
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HRESULT Read(void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialInStreamCRC32_String() {}
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};
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class ISequentialInStreamCRC32_Istream : public ISequentialInStream_Istream, public ISequentialStreamCRC32
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{
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public:
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ISequentialInStreamCRC32_Istream(std::istream& Adata) : ISequentialInStream_Istream(Adata) { }
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HRESULT Read(void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialInStreamCRC32_Istream() {}
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};
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class ISequentialOutStreamCRC32_Array : public ISequentialOutStream_Array, public ISequentialStreamCRC32
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{
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public:
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ISequentialOutStreamCRC32_Array(char *Adata, unsigned Asize) : ISequentialOutStream_Array(Adata, Asize) { }
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HRESULT Write(const void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialOutStreamCRC32_Array() {}
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};
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class ISequentialOutStreamCRC32_String : public ISequentialOutStream_String, public ISequentialStreamCRC32
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{
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public:
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ISequentialOutStreamCRC32_String(std::string& Adata) : ISequentialOutStream_String(Adata) { }
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HRESULT Write(const void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialOutStreamCRC32_String() {}
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};
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class ISequentialOutStreamCRC32_Ostream : public ISequentialOutStream_Ostream, public ISequentialStreamCRC32
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{
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public:
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ISequentialOutStreamCRC32_Ostream(std::ostream& Adata) : ISequentialOutStream_Ostream(Adata) { }
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HRESULT Write(const void *aData, UINT32 aSize, UINT32 *aProcessedSize);
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virtual ~ISequentialOutStreamCRC32_Ostream() {}
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};
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#endif
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