mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-04-02 10:42:14 -04:00
81f43a4d01
This represents a major code restructuring. The dot-based and scanline-based renderers are now split into two separate core libraries, asnes and bsnes. For now at least, these are -internal- names. I'm not entirely decided on how I'm going to handle releasing these two separate builds. Regardless, the folders need names. asnes has had all of the processor subfolders collapsed back into their parent folders. In other words, ppu's functions were moved into ppu/sppu, and then ppu was deleted, and then ppu/sppu became the new ppu. Repeat this for the cpu, smp and dsp and there you go. asnes/dsp also removed the DSP_STATE_MACHINE option. This was done for the sake of consistency with the rest of the core. asnes' debugger mode is currently extremely broken, but I will be fixing it in time. And for now, bsnes has kept the processor abstraction layer. I may keep it around, not sure yet. It doesn't hurt speed or anything, so I'm not too worried about making a decision right away. I may throw snesfilter, snesreader and supergameboy into this folder, just to have everything in one place. The alternate GUI forks are definitely going in there as dotnet, cocoa and python. Compiled output goes to the out/ folder now, to prevent conflicts with a file and folder named bsnes, for instance.
513 lines
20 KiB
ArmAsm
513 lines
20 KiB
ArmAsm
;*****
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;libco.ppc64 (2007-12-05)
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;author: Vas Crabb
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;license: public domain
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;
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;cross-platform 64-bit PowerPC implementation of libco
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;special thanks to byuu for writing the original version
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;
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;[ABI compatibility]
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;- gcc; mac os x; ppc64
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;
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;[nonvolatile registers]
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;- GPR1, GPR13 - GPR31
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;- FPR14 - FPR31
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;- V20 - V31
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;- VRSAVE, CR2 - CR4
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;
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;[volatile registers]
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;- GPR0, GPR2 - GPR12
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;- FPR0 - FPR13
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;- V0 - V19
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;- LR, CTR, XER, CR0, CR1, CR5 - CR7
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;*****
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;Declare some target-specific stuff
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.section __TEXT,__text,regular,pure_instructions
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.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
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.machine ppc64
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;Constants
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.cstring
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.align 3
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_sysctl_altivec:
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.ascii "hw.optional.altivec\0"
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;Declare space for variables
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.lcomm _co_environ,4,2 ;bit 0 = initialised, bit 1 = have Altivec/VMX
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.lcomm _co_primary_buffer,1024,3 ;buffer (will be zeroed by loader)
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.data
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.align 3
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_co_active_context:
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.quad _co_primary_buffer
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.text
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.align 2
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;Declare exported names
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.globl _co_active
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.globl _co_create
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.globl _co_delete
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.globl _co_switch
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;*****
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;extern "C" cothread_t co_active();
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;return = GPR3
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;*****
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_co_active:
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mflr r0 ;GPR0 = return address
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bcl 20,31,L_co_active$spb
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L_co_active$spb:
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mflr r2 ;GPR2 set for position-independance
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addis r3,r2,ha16(_co_active_context-L_co_active$spb) ;get value in GPR3
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ld r3,lo16(_co_active_context-L_co_active$spb)(r3)
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mtlr r0 ;LR = return address
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blr ;return
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;*****
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;extern "C" cothread_t co_create(unsigned int heapsize, void (*coentry)());
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;GPR3 = heapsize
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;GPR4 = coentry
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;return = GPR3
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;*****
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_co_create:
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mflr r0 ;GPR0 = return address
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std r30,-16(r1) ;save GPR30 and GPR31
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std r31,-8(r1)
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std r0,16(r1) ;save return address
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stdu r1,-(2*8+16+48)(r1) ;allocate 16 bytes for locals/parameters
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;create heap space (stack + register storage)
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addi r31,r3,1024-48 ;subtract space for linkage
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mr r30,r4 ;GPR30 = coentry
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addi r3,r3,1024 ;allocate extra memory for contextual info
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bl L_malloc$stub ;GPR3 = malloc(heapsize + 1024)
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add r4,r3,r31 ;GPR4 points to top-of-stack
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rldicr r5,r4,0,59 ;force 16-byte alignment
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;store thread entry point + registers, so that first call to co_switch will execute coentry
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std r30,16(r5) ;store entry point
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addi r6,0,2+19+18+12*2+1 ;clear for CR, old GPR1, 19 GPRs, 18 FPRs, 12 VRs, VRSAVE
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addi r0,0,0
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addi r7,0,8 ;start at 8(GPR5)
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mtctr r6
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L_co_create$clear_loop:
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stdx r0,r5,r7 ;clear a double
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addi r7,r7,-8 ;increment pointer
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bdnz L_co_create$clear_loop ;loop
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stdu r5,-544(r5) ;store top of stack
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;initialize context memory heap and return
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addis r9,0,0x8000 ;GPR13 not set (system TLS)
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std r5,0(r3) ;*cothread_t = stack heap pointer (GPR1)
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stw r9,8(r3) ;this is a flag word
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ld r1,0(r1) ;deallocate stack frame
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ld r8,16(r1) ;fetch return address
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ld r30,-16(r1) ;restore GPR30 and GPR31
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ld r31,-8(r1)
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mtlr r8 ;return address in LR
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blr ;return
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;*****
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;extern "C" void co_delete(cothread_t cothread);
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;GPR3 = cothread
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;*****
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_co_delete:
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b L_free$stub ;free(GPR3)
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;*****
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;extern "C" void co_switch(cothread_t cothread);
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;GPR3 = cothread
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;*****
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;
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;Frame looks like:
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;
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;Old New Value
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; 16(r1) 560(r1) Saved LR
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; 8(r1) 552(r1) Saved CR
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; 0(r1) 544(r1) Old GPR1
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; -8(r1) 536(r1) Saved GPR31
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; -16(r1) 528(r1) Saved GPR30
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;... ... ...
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;-144(r1) 400(r1) Saved GPR14
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;-152(r1) 392(r1) Saved GPR13
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;-160(r1) 384(r1) Saved FPR31
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;-168(r1) 376(r1) Saved FPR30
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;... ... ...
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;-288(r1) 256(r1) Saved FPR15
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;-296(r1) 248(r1) Saved FPR14
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;-304(r1) 240(r1) Saved VRSAVE
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;-312(r1) 232(r1) +++ value
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;-320(r1) 224(r1) Saved VR31 len
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;-328(r1) 216(r1) +++
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;-336(r1) 208(r1) Saved VR30
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;... ... ...
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;-456(r1) 88(r1) +++
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;-464(r1) 80(r1) Saved VR22 Param 5 (GPR7)
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;-472(r1) 72(r1) +++ Param 4 (GPR6)
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;-480(r1) 64(r1) Saved VR21 Param 3 (GPR5)
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;-488(r1) 56(r1) +++ Param 2 (GPR4)
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;-496(r1) 48(r1) Saved VR20 Param 1 (GPR3)
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;-504(r1) 40(r1) - Reserved
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;-512(r1) 32(r1) - Reserved
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;-520(r1) 24(r1) - Reserved
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;-528(r1) 16(r1) - New LR
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;-536(r1) 8(r1) - New CR
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;-544(r1) 0(r1) Saved GPR1
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_co_switch:
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std r13,-152(r1) ;save preserved GPRs
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std r14,-144(r1)
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std r15,-136(r1)
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std r16,-128(r1)
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std r17,-120(r1)
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std r18,-112(r1)
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std r19,-104(r1)
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std r20,-96(r1)
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std r21,-88(r1)
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std r22,-80(r1)
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std r23,-72(r1)
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std r24,-64(r1)
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std r25,-56(r1)
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std r26,-48(r1)
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std r27,-40(r1)
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std r28,-32(r1)
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std r29,-24(r1)
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std r30,-16(r1)
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std r31,-8(r1)
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mflr r0 ;save return address
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std r0,16(r1)
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mfcr r2 ;save condition codes
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stw r2,8(r1)
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stdu r1,-544(r1) ;create stack frame (save 19 GPRs, 18 FRPs, 12 VRs, VRSAVE)
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stfd f14,248(r1) ;save preserved FPRs
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stfd f15,256(r1)
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stfd f16,264(r1)
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stfd f17,272(r1)
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stfd f18,280(r1)
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stfd f19,288(r1)
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stfd f20,296(r1)
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stfd f21,304(r1)
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stfd f22,312(r1)
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stfd f23,320(r1)
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stfd f24,328(r1)
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stfd f25,336(r1)
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stfd f26,344(r1)
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stfd f27,352(r1)
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stfd f28,360(r1)
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stfd f29,368(r1)
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stfd f30,376(r1)
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stfd f31,384(r1)
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mr r30,r3 ;save new context pointer
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bcl 20,31,L_co_switch$spb ;get address of co_active_context
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L_co_switch$spb:
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mflr r31
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addis r29,r31,ha16(_co_environ-L_co_switch$spb) ;get environment flags
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lwz r8,lo16(_co_environ-L_co_switch$spb)(r29)
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andis. r9,r8,0x8000 ;is it initialised?
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bne+ L_co_switch$initialised
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addi r0,0,4 ;len = sizeof(int)
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std r0,224(r1)
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addis r3,r31,ha16(_sysctl_altivec-L_co_switch$spb) ;GPR3 = "hw.optional.altivec"
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addi r3,r3,lo16(_sysctl_altivec-L_co_switch$spb)
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addi r4,r1,232 ;GPR4 = &value
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addi r5,r1,224 ;GPR5 = &len
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addi r6,0,0 ;newp = 0
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addi r7,0,0 ;newlen = 0
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bl L_sysctlbyname$stub ;call sysctlbyname
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lwz r2,232(r1) ;fetch result
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addis r8,0,0x8000 ;set initialised bit
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cmpdi cr5,r3,0 ;assume error means not present
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cmpwi cr6,r2,0 ;test result
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blt- cr5,L_co_switch$store_environ
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beq cr6,L_co_switch$store_environ
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oris r8,r8,0x4000 ;set the flag to say we have it!
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L_co_switch$store_environ:
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stw r8,lo16(_co_environ-L_co_switch$spb)(r29) ;store environment flags
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L_co_switch$initialised:
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andis. r10,r8,0x4000 ;do we have Altivec/VMX?
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beq L_co_switch$save_no_vmx
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mfspr r11,256 ;save VRSAVE
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andi. r0,r11,0x0FFF ;short-circuit if it's zero
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stw r11,240(r1)
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beq L_co_switch$save_no_vmx
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andi. r0,r11,0x0800 ;check bit 20
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addi r2,0,48 ;starting index
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beq L_co_switch$save_skip_vr20
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stvx v20,r1,r2 ;save VR20
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L_co_switch$save_skip_vr20:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0400 ;check bit 21
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beq L_co_switch$save_skip_vr21
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stvx v21,r1,r2 ;save VR21
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L_co_switch$save_skip_vr21:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0200 ;check bit 22
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beq L_co_switch$save_skip_vr22
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stvx v22,r1,r2 ;save VR22
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L_co_switch$save_skip_vr22:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0100 ;check bit 23
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beq L_co_switch$save_skip_vr23
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stvx v23,r1,r2 ;save VR23
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L_co_switch$save_skip_vr23:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0080 ;check bit 24
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beq L_co_switch$save_skip_vr24
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stvx v24,r1,r2 ;save VR24
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L_co_switch$save_skip_vr24:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0040 ;check bit 25
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beq L_co_switch$save_skip_vr25
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stvx v25,r1,r2 ;save VR25
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L_co_switch$save_skip_vr25:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0020 ;check bit 26
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beq L_co_switch$save_skip_vr26
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stvx v26,r1,r2 ;save VR26
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L_co_switch$save_skip_vr26:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0010 ;check bit 27
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beq L_co_switch$save_skip_vr27
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stvx v27,r1,r2 ;save VR27
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L_co_switch$save_skip_vr27:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0008 ;check bit 28
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beq L_co_switch$save_skip_vr28
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stvx v28,r1,r2 ;save VR28
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L_co_switch$save_skip_vr28:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0004 ;check bit 29
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beq L_co_switch$save_skip_vr29
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stvx v29,r1,r2 ;save VR29
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L_co_switch$save_skip_vr29:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0002 ;check bit 30
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beq L_co_switch$save_skip_vr30
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stvx v30,r1,r2 ;save VR30
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L_co_switch$save_skip_vr30:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0001 ;check bit 31
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beq L_co_switch$save_skip_vr31
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stvx v31,r1,r2 ;save VR31
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L_co_switch$save_skip_vr31:
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L_co_switch$save_no_vmx:
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addis r4,r31,ha16(_co_active_context-L_co_switch$spb) ;save current context
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ld r5,lo16(_co_active_context-L_co_switch$spb)(r4)
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std r30,lo16(_co_active_context-L_co_switch$spb)(r4);set new context
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std r1,0(r5) ;save current stack pointer
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ld r1,0(r30) ;get new stack pointer
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lwz r12,8(r30) ;have we already set GPR13 (system TLS)?
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andis. r0,r12,0x8000
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beq+ L_co_switch$gpr13_set
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std r13,392(r1)
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xoris r12,r12,0x8000
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stw r12,8(r30)
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L_co_switch$gpr13_set:
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andis. r10,r8,0x4000 ;do we have Altivec/VMX?
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beq L_co_switch$restore_no_vmx
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lwz r11,240(r1) ;restore VRSAVE
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andi. r0,r11,0x0FFF ;short-circuit if it's zero
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mtspr 256,r11
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beq L_co_switch$restore_no_vmx
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andi. r0,r11,0x0800 ;check bit 20
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addi r2,0,48 ;starting index
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beq L_co_switch$restore_skip_vr20
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lvx v20,r1,r2 ;restore VR20
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L_co_switch$restore_skip_vr20:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0400 ;check bit 21
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beq L_co_switch$restore_skip_vr21
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lvx v21,r1,r2 ;restore VR21
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L_co_switch$restore_skip_vr21:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0200 ;check bit 22
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beq L_co_switch$restore_skip_vr22
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lvx v22,r1,r2 ;restore VR22
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L_co_switch$restore_skip_vr22:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0100 ;check bit 23
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beq L_co_switch$restore_skip_vr23
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lvx v23,r1,r2 ;restore VR23
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L_co_switch$restore_skip_vr23:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0080 ;check bit 24
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beq L_co_switch$restore_skip_vr24
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lvx v24,r1,r2 ;restore VR24
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L_co_switch$restore_skip_vr24:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0040 ;check bit 25
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beq L_co_switch$restore_skip_vr25
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lvx v25,r1,r2 ;restore VR25
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L_co_switch$restore_skip_vr25:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0020 ;check bit 26
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beq L_co_switch$restore_skip_vr26
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lvx v26,r1,r2 ;restore VR26
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L_co_switch$restore_skip_vr26:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0010 ;check bit 27
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beq L_co_switch$restore_skip_vr27
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lvx v27,r1,r2 ;restore VR27
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L_co_switch$restore_skip_vr27:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0008 ;check bit 28
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beq L_co_switch$restore_skip_vr28
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lvx v28,r1,r2 ;restore VR28
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L_co_switch$restore_skip_vr28:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0004 ;check bit 29
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beq L_co_switch$restore_skip_vr29
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lvx v29,r1,r2 ;restore VR29
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L_co_switch$restore_skip_vr29:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0002 ;check bit 30
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beq L_co_switch$restore_skip_vr30
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lvx v30,r1,r2 ;restore VR30
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L_co_switch$restore_skip_vr30:
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addi r2,r2,16 ;stride
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andi. r0,r11,0x0001 ;check bit 31
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beq L_co_switch$restore_skip_vr31
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lvx v31,r1,r2 ;restore VR31
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L_co_switch$restore_skip_vr31:
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L_co_switch$restore_no_vmx:
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lfd f14,248(r1) ;restore preserved FPRs
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lfd f15,256(r1)
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lfd f16,264(r1)
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lfd f17,272(r1)
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lfd f18,280(r1)
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lfd f19,288(r1)
|
|
lfd f20,296(r1)
|
|
lfd f21,304(r1)
|
|
lfd f22,312(r1)
|
|
lfd f23,320(r1)
|
|
lfd f24,328(r1)
|
|
lfd f25,336(r1)
|
|
lfd f26,344(r1)
|
|
lfd f27,352(r1)
|
|
lfd f28,360(r1)
|
|
lfd f29,368(r1)
|
|
lfd f30,376(r1)
|
|
lfd f31,384(r1)
|
|
addi r0,0,0 ;make thread main crash if it returns
|
|
ld r1,0(r1) ;deallocate stack frame
|
|
ld r6,16(r1) ;return address in GPR6
|
|
lwz r7,8(r1) ;condition codes in GPR7
|
|
ld r13,-152(r1) ;restore preserved GPRs
|
|
ld r14,-144(r1)
|
|
ld r15,-136(r1)
|
|
ld r16,-128(r1)
|
|
ld r17,-120(r1)
|
|
ld r18,-112(r1)
|
|
ld r19,-104(r1)
|
|
ld r20,-96(r1)
|
|
ld r21,-88(r1)
|
|
ld r22,-80(r1)
|
|
ld r23,-72(r1)
|
|
ld r24,-64(r1)
|
|
ld r25,-56(r1)
|
|
ld r26,-48(r1)
|
|
ld r27,-40(r1)
|
|
ld r28,-32(r1)
|
|
ld r29,-24(r1)
|
|
ld r30,-16(r1)
|
|
ld r31,-8(r1)
|
|
mtlr r0
|
|
mtctr r6 ;restore return address
|
|
mtcrf 32,r7 ;restore preserved condition codes
|
|
mtcrf 16,r7
|
|
mtcrf 8,r7
|
|
bctr ;return
|
|
|
|
|
|
|
|
;Import external functions
|
|
|
|
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
|
|
.align 5
|
|
L_malloc$stub:
|
|
.indirect_symbol _malloc
|
|
mflr r0
|
|
bcl 20,31,L_malloc$spb
|
|
L_malloc$spb:
|
|
mflr r11
|
|
addis r11,r11,ha16(L_malloc$lazy_ptr-L_malloc$spb)
|
|
mtlr r0
|
|
ldu r12,lo16(L_malloc$lazy_ptr-L_malloc$spb)(r11)
|
|
mtctr r12
|
|
bctr
|
|
.lazy_symbol_pointer
|
|
L_malloc$lazy_ptr:
|
|
.indirect_symbol _malloc
|
|
.quad dyld_stub_binding_helper
|
|
|
|
|
|
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
|
|
.align 5
|
|
L_free$stub:
|
|
.indirect_symbol _free
|
|
mflr r0
|
|
bcl 20,31,L_free$spb
|
|
L_free$spb:
|
|
mflr r11
|
|
addis r11,r11,ha16(L_free$lazy_ptr-L_free$spb)
|
|
mtlr r0
|
|
ldu r12,lo16(L_free$lazy_ptr-L_free$spb)(r11)
|
|
mtctr r12
|
|
bctr
|
|
.lazy_symbol_pointer
|
|
L_free$lazy_ptr:
|
|
.indirect_symbol _free
|
|
.quad dyld_stub_binding_helper
|
|
|
|
|
|
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
|
|
.align 5
|
|
L_sysctlbyname$stub:
|
|
.indirect_symbol _sysctlbyname
|
|
mflr r0
|
|
bcl 20,31,L_sysctlbyname$spb
|
|
L_sysctlbyname$spb:
|
|
mflr r11
|
|
addis r11,r11,ha16(L_sysctlbyname$lazy_ptr-L_sysctlbyname$spb)
|
|
mtlr r0
|
|
ldu r12,lo16(L_sysctlbyname$lazy_ptr-L_sysctlbyname$spb)(r11)
|
|
mtctr r12
|
|
bctr
|
|
.lazy_symbol_pointer
|
|
L_sysctlbyname$lazy_ptr:
|
|
.indirect_symbol _sysctlbyname
|
|
.quad dyld_stub_binding_helper
|
|
|
|
|
|
;This needs to be here!
|
|
|
|
.subsections_via_symbols
|
|
|