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https://github.com/devinacker/bsnes-plus.git
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125 lines
2.5 KiB
C++
125 lines
2.5 KiB
C++
#include "bus.hpp"
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class Cx4 : public Coprocessor, public Memory {
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public:
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unsigned frequency;
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static void Enter();
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void enter();
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//memory.cpp
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uint8 read(unsigned addr);
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void write(unsigned addr, uint8 data);
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uint8 rom_read(unsigned addr);
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uint8 ram_read(unsigned addr);
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void ram_write(unsigned addr, uint8 data);
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void init();
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void enable();
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void power();
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void reset();
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void serialize(serializer&);
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//data.cpp
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static const uint24 dataROM[1024];
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protected:
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void add_clocks(unsigned);
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//memory.cpp
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uint8 op_read(unsigned addr);
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void op_write(unsigned addr, uint8 data);
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uint8 dsp_read(unsigned addr);
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void dsp_write(unsigned addr, uint8 data);
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void push();
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void pull();
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unsigned sa();
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unsigned ri();
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unsigned np();
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void instruction();
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void nextpc();
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void change_page();
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void load_page(uint8 cachePage, uint16 programPage);
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//registers.cpp
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uint24 register_read(uint8 addr);
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void register_write(uint8 addr, uint24 data);
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uint8 dataRAM[3072];
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struct Registers {
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bool halt;
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uint8 cachePage;
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bool irqPending;
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uint24 rwbusaddr;
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uint8 rwbustime;
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bool writebus;
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uint24 writebusdata;
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uint23 pc;
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uint15 p;
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bool n;
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bool z;
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bool v;
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bool c;
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uint24 a;
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uint24 acch;
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uint24 accl;
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uint24 busdata;
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uint24 romdata;
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uint24 ramdata;
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uint24 busaddr;
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uint24 ramaddr;
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uint24 gpr[16];
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uint24 mdr;
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} regs;
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uint23 stack[8];
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uint16 opcode;
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struct MMIO {
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bool dma; //true during DMA transfers
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bool suspend;
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bool cacheLoading;
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uint24 dmaSource; //$1f40-$1f42
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uint24 dmaLength; //$1f43-$1f44
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uint24 dmaTarget; //$1f45-$1f47
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uint8 cachePreload; //$1f48
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uint24 programOffset; //$1f49-$1f4b
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uint16 pageNumber; //$1f4d-$1f4e
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uint8 programCounter; //$1f4f
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uint8 romSpeed; //$1f50
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uint8 ramSpeed; //$1f50
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uint8 irqDisable; //$1f51
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uint8 r1f52; //$1f52
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uint8 suspendCycles; //$1f55-$1f5c
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uint8 vector[32]; //$1f60-$1f7f
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} mmio;
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struct CachePage {
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bool lock;
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uint15 pageNumber;
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uint16 data[256];
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} cache[2];
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alwaysinline bool bus_access() {
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// cartridge bus in use
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return mmio.dma || mmio.cacheLoading || regs.rwbustime > 0;
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}
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alwaysinline bool busy() {
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// performing DMA, cache preload, or running code
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return mmio.dma || mmio.cacheLoading || !regs.halt;
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}
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};
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extern Cx4 cx4;
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extern Cx4Bus cx4bus;
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