Emulation/bsnes-plus
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518 commits 3 branches 8 tags 23 MiB
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102 commits

Author SHA1 Message Date
devinacker
9c8495847e run to vblank/hblank options 2019-05-27 00:50:05 -04:00
devinacker
1f10eac106 run to next NMI/IRQ for CPU and SA1 2019-05-26 23:13:04 -04:00
Benjamin Schulte
5ca2da30ce allow to break on startup and on BRK 2018-11-24 20:38:16 -05:00
devinacker
afdd3e4cb8 updated cx4 instruction info (closes #196) 2018-11-24 00:24:43 -05:00
devinacker
4137df2116 get rid of questionable bsxcart "hidden register" behavior that's difficult to verify (or even reproduce) 2018-10-23 21:06:55 -04:00
devinacker
9cf3c9b1e2 bsx: more experimental base/cart register handling 2018-08-25 18:59:30 -04:00
devinacker
05a65f5995 cx4: fix typo reading RAM from wrong source 
(which affected no games due to the lack of on-cart RAM in both, but...)
 2018-08-25 18:48:52 -04:00
devinacker
80260b66eb cx4: set irq in the same cycle as irqPending 2018-07-31 00:02:06 -04:00
devinacker
7df296f720 more Cx4 timing/mapping revisions 2018-07-29 22:24:33 -04:00
devinacker
90352e504b bsx: don't unnecessarily allocate empty memory pack twice 2018-07-28 17:18:36 -04:00
devinacker
050263c4c8 BS-X: report correct flash size in vendor info 2018-07-23 08:55:28 -04:00
devinacker
82ed2343af BS-X: don't let debugger interfere with flash writes 2018-07-23 08:31:39 -04:00
devinacker
fafc2a8d13 more accurate satellite data xfer rate 2018-07-21 21:14:11 -04:00
devinacker
1203147678 slight BS-X stream status fix 
(actually reset queued packets when writing latch enable registers,
don't get stuck if an overflow happens)
 2018-07-21 04:10:05 -04:00
devinacker
8dfda29fc9 minor Cx4 timing tweaks (not tested) 2018-07-21 00:41:24 -04:00
devinacker
c00ad9f1e4 use same timing for Time Channel 2018-07-13 22:44:07 -04:00
devinacker
9f278dddae try simulating satellaview bandwidth limits (partially to avoid software glitches that can occur if the entire stream is available instantaneously) 2018-07-12 23:16:37 -04:00
devinacker
d1051b33e9 add BS-X savestate support (and some other savestate safety checks) 2018-07-08 00:02:51 -04:00
devinacker
99b66a4bff cleanup/refactor some bsx code (closes #182) 2018-07-07 13:44:08 -04:00
devinacker
b0bfab47ea superfx dithering fix from higan v106r18 2018-05-19 16:01:19 -04:00
Alex W. Jackson
119c3c3524 necdsp: improve OV1/S1 flag calculations 2018-05-15 01:45:00 -04:00
devinacker
84bb255d16 cx4: missing parens (#172) 2018-05-07 22:55:04 -04:00
devinacker
c60f0373fc more properties viewer stuff (fixes #152) 2018-04-29 01:13:18 -04:00
devinacker
9a298b1ff1 don't show cart ROM in debugger when GSU owns it 2018-04-29 01:13:18 -04:00
devinacker
1bdcd73e17 do better at ignoring dummy reads (fixes #170) 2018-04-29 01:13:17 -04:00
LuigiBlood
5a420536a8 BSX code clean up and more accurate reset values 2017-12-16 11:36:40 +01:00
LuigiBlood
beccbec1df Satellaview Bigger Data File again 2017-12-15 19:11:48 +01:00
LuigiBlood
e8953959fb Support Bigger Satellite Data Files 2017-12-15 19:04:22 +01:00
devinacker
54ffadff05 more Cx4 tweaks 2017-09-04 01:31:06 -04:00
devinacker
67b279fde7 Cx4 IRQs 2017-09-04 01:30:46 -04:00
devinacker
8946469816 start applying ikari_01's cx4 findings 2017-09-04 01:30:46 -04:00
devinacker
842ebaac25 superfx: track pipeline better when disassembling 
(should fix #116)
 2017-09-04 00:38:14 -04:00
devinacker
5d2846fd59 cx4 memory tweaks 2017-08-29 20:08:19 -04:00
devinacker
9ecf8b3777 backport higan's Cx4 LLE implementation 2017-08-27 12:09:39 -04:00
devinacker
4bf8196826 better behavior for M/X flags in register editor 2017-05-03 22:47:47 -04:00
ARM9
5f52c042cf SuperFX property viewer improvements 
added register 3036 (rom bank register ROMBR)

fixed register 3039 (clock register CLSR), used to display wrong values due
to misinterpreted implementation detail
 2017-01-31 16:50:20 +01:00
devinacker
b5eaaeb691 bsx: only map if register values actually change 
(fixes Treasure Conflix and who knows what else)
 2017-01-12 22:06:32 -05:00
devinacker
75a9496e5a superfx: make a couple of registers 7-bit 2016-12-13 20:58:22 -05:00
devinacker
843afbff15 try to avoid mapping RAM when it doesn't exist 2016-12-10 08:19:38 -05:00
luigiblood
c32e7423d7 [BS-X] Fix Satellaview behavior for Itoi Bass Fishing 
Unemulated behavior with data latches and data queue is now supported and makes Itoi Bass Fishing working.
 2016-11-22 21:09:10 +01:00
devinacker
b9abe4a7ab bsx: set regs.time_day correctly (tm_mday is 1-31) 2016-11-22 09:57:05 -05:00
devinacker
9b35a0499f add support for custom BS-X date/time 2016-11-22 09:43:00 -05:00
luigiblood
4d3cb7dee3 Satellaview signal data emulation 2016-11-21 18:38:29 -05:00
devinacker
502a159238 msu1: unload files when unloading cartridge 
closes #82
 2016-11-19 15:52:46 -05:00
devinacker
758363b890 small cleanup 2016-11-19 00:04:53 -05:00
luigiblood
5300d506e2 AND byte on write to Memory Pack 
Fixes Sound Novel Tsukuru save
 2016-11-16 01:39:24 +01:00
devinacker
6dfebcc886 msu1: return to previous flag behavior for $2005 
per byuu, this is the intended behavior and the removal was an
unintended regression in higan v95. reverting will continue to keep it
compatible with most higan versions and the sd2snes
 2016-10-24 19:27:39 -04:00
devinacker
bed80e8636 msu1: adhere to current spec init volume 2016-10-21 21:39:11 -04:00
devinacker
6cb7e30a2d msu1: don't break playback after loading a state 
fixes #54
 2016-10-21 21:22:46 -04:00
devinacker
3d7b4e3785 msu1: seek to resume position correctly 2016-10-21 01:22:10 -04:00