13 commits

Author	SHA1	Message	Date
devinacker	9c8495847e	run to vblank/hblank options	2019-05-27 00:50:05 -04:00
devinacker	1f10eac106	run to next NMI/IRQ for CPU and SA1	2019-05-26 23:13:04 -04:00
Benjamin Schulte	01ca91f6cf	try to lookahead the current code for better preview	2018-11-25 12:07:14 -05:00
devinacker	2fe8550c6b	use a proper interface to get/set registers	2016-08-03 21:06:34 -04:00
Alex W. Jackson	5a64f078d5	Use bus_access for disassembler too; remove some dead code	2015-05-29 23:35:12 -04:00
devinacker	5c4cfe8110	more of the above (inc. for additional debuggers)	2015-05-24 20:04:44 -04:00
devinacker	b8bc79551d	don't disassemble every single byte	2015-04-11 17:25:39 -04:00
devinacker	fbadb7cfaf	mark read/write during DMA and MMIO WRAM access	2014-11-30 19:07:08 -05:00
devinacker	0bd32c44a6	update CPU debugger comment	2014-11-30 05:48:23 -05:00
devinacker	2a3d2e7614	merge redundant CPU debuggers ... and enable debugging for all profiles, not just performance	2014-11-30 05:21:29 -05:00
devinacker	d54c2bd3ea	add cart ROM view to memory editor	2014-11-29 05:50:17 -05:00
devinacker	f754ba0c21	add color coding to memory viewer for usage ... (and also mark operand bytes as executed, not just read)	2014-11-29 02:38:43 -05:00
devinacker	d88ac78d30	initial commit	2014-11-26 18:35:12 -05:00