124 commits

Author	SHA1	Message	Date
Devin Acker	c593fd0b96	disasm: treat calls and branches differently for state tracking purposes	2021-08-15 21:52:32 -04:00
Devin Acker	a8f91cf151	sgb: use 24-bit addresses to make debugger more aware of MBC bank ... switching (#249)	2020-02-27 18:43:15 -05:00
devinacker	a7b7faebb6	improved SGB disassembly and analysis	2020-02-16 15:50:13 -05:00
devinacker	8b1b7bcab6	SGB: more accurate handling of LCD buffering, per #247. this also involves modifying libgambatte to return after finishing a scanline and not just after finishing a frame, in order to keep it from running too far ahead before the SGB BIOS has buffered current LCD output successfully	2020-02-08 21:26:55 -05:00
devinacker	def842531f	allow multiple simultaneous coprocessor audio sources	2020-02-08 00:04:06 -05:00
devinacker	ffaf4c7881	add call/return tracking to sgb debug	2020-02-06 22:44:15 -05:00
devinacker	10b5368e09	sgb: don't mix GB audio when SNES DSP is muted	2020-01-08 00:25:25 -05:00
devinacker	4dafe10cc2	sgb: add GB CPU speed control via 003	2020-01-06 22:46:09 -05:00
devinacker	5c41e11590	don't try to pass SGB memory to the plugin if it's not loaded	2020-01-04 02:01:15 -05:00
devinacker	ea7f021872	tweak other disasm flag displays to match while i'm at it, it's probably a bit easier on the eyes this way	2020-01-04 02:01:15 -05:00
devinacker	5246c7eb0f	incorporate sgb register interface into disasm/trace	2020-01-04 02:01:14 -05:00
devinacker	ac35b36972	sgb register editing interface	2020-01-04 02:01:14 -05:00
devinacker	4c5f1d0c28	start adding sgb disassembly/debugging stuff	2020-01-04 01:25:54 -05:00
devinacker	acc3304825	begin minimal sgb debug interface	2020-01-03 02:48:51 -05:00
devinacker	e4edc7a229	backport some scheduler improvements from current bsnes; should hopefully fix some potential serialization deadlocks including possibly what was causing issues #233 and #240	2019-12-07 17:27:32 -05:00
devinacker	4383a232bb	add automatic analysis to sa1 debugger	2019-12-04 21:33:11 -05:00
devinacker	e398ad5685	make sure register displays for different chips line up in text disasm	2019-09-07 15:00:41 -04:00
devinacker	9899678437	improvements to superfx disassembly/debugging	2019-09-06 22:31:31 -04:00
devinacker	4c86ec19cf	make sure SNES config struct is initialized before first access (should fix #229)	2019-08-31 17:26:50 -04:00
devinacker	7afc25fe34	make chip firmware path configurable (closes #177)	2019-08-28 23:42:36 -04:00
devinacker	07c7cb3924	Merge branch 'master' into newdebugger	2019-07-23 22:08:04 -04:00
devinacker	5f39119b23	backport fixes to SA1 mul/div	2019-05-28 23:00:22 -04:00
devinacker	9c8495847e	run to vblank/hblank options	2019-05-27 00:50:05 -04:00
devinacker	1f10eac106	run to next NMI/IRQ for CPU and SA1	2019-05-26 23:13:04 -04:00
Benjamin Schulte	5ca2da30ce	allow to break on startup and on BRK	2018-11-24 20:38:16 -05:00
devinacker	afdd3e4cb8	updated cx4 instruction info (closes #196)	2018-11-24 00:24:43 -05:00
devinacker	4137df2116	get rid of questionable bsxcart "hidden register" behavior that's difficult to verify (or even reproduce)	2018-10-23 21:06:55 -04:00
devinacker	9cf3c9b1e2	bsx: more experimental base/cart register handling	2018-08-25 18:59:30 -04:00
devinacker	05a65f5995	cx4: fix typo reading RAM from wrong source ... (which affected no games due to the lack of on-cart RAM in both, but...)	2018-08-25 18:48:52 -04:00
devinacker	80260b66eb	cx4: set irq in the same cycle as irqPending	2018-07-31 00:02:06 -04:00
devinacker	7df296f720	more Cx4 timing/mapping revisions	2018-07-29 22:24:33 -04:00
devinacker	90352e504b	bsx: don't unnecessarily allocate empty memory pack twice	2018-07-28 17:18:36 -04:00
devinacker	050263c4c8	BS-X: report correct flash size in vendor info	2018-07-23 08:55:28 -04:00
devinacker	82ed2343af	BS-X: don't let debugger interfere with flash writes	2018-07-23 08:31:39 -04:00
devinacker	fafc2a8d13	more accurate satellite data xfer rate	2018-07-21 21:14:11 -04:00
devinacker	1203147678	slight BS-X stream status fix ... (actually reset queued packets when writing latch enable registers, don't get stuck if an overflow happens)	2018-07-21 04:10:05 -04:00
devinacker	8dfda29fc9	minor Cx4 timing tweaks (not tested)	2018-07-21 00:41:24 -04:00
devinacker	c00ad9f1e4	use same timing for Time Channel	2018-07-13 22:44:07 -04:00
devinacker	9f278dddae	try simulating satellaview bandwidth limits (partially to avoid software glitches that can occur if the entire stream is available instantaneously)	2018-07-12 23:16:37 -04:00
devinacker	d1051b33e9	add BS-X savestate support (and some other savestate safety checks)	2018-07-08 00:02:51 -04:00
devinacker	99b66a4bff	cleanup/refactor some bsx code (closes #182)	2018-07-07 13:44:08 -04:00
devinacker	b0bfab47ea	superfx dithering fix from higan v106r18	2018-05-19 16:01:19 -04:00
Alex W. Jackson	119c3c3524	necdsp: improve OV1/S1 flag calculations	2018-05-15 01:45:00 -04:00
devinacker	84bb255d16	cx4: missing parens (#172)	2018-05-07 22:55:04 -04:00
devinacker	c60f0373fc	more properties viewer stuff (fixes #152)	2018-04-29 01:13:18 -04:00
devinacker	9a298b1ff1	don't show cart ROM in debugger when GSU owns it	2018-04-29 01:13:18 -04:00
devinacker	1bdcd73e17	do better at ignoring dummy reads (fixes #170)	2018-04-29 01:13:17 -04:00
LuigiBlood	5a420536a8	BSX code clean up and more accurate reset values	2017-12-16 11:36:40 +01:00
LuigiBlood	beccbec1df	Satellaview Bigger Data File again	2017-12-15 19:11:48 +01:00
LuigiBlood	e8953959fb	Support Bigger Satellite Data Files	2017-12-15 19:04:22 +01:00