6 commits

Author	SHA1	Message	Date
devinacker	1f10eac106	run to next NMI/IRQ for CPU and SA1	2019-05-26 23:13:04 -04:00
devinacker	2fe8550c6b	use a proper interface to get/set registers	2016-08-03 21:06:34 -04:00
devinacker	cc6cfefae9	some SA-1 bus read changes ... (read from SA-1 bus instead of CPU bus from the disassembler, and stop reading from a different bus than the main SA-1 since it isn't necessary anymore)	2015-05-30 00:39:38 -04:00
devinacker	5c4cfe8110	more of the above (inc. for additional debuggers)	2015-05-24 20:04:44 -04:00
devinacker	b8bc79551d	don't disassemble every single byte	2015-04-11 17:25:39 -04:00
devinacker	f1581e8464	SA-1 debugging/disasm/viewing/tracing ... (still needs read/write logging for MMIO, DMA, bitmap RAM accesses, and other stuff, as well as the properties window items, but it's 6 am and i'm tired)	2014-12-06 06:03:02 -05:00