mirror of
https://github.com/Marat-Tanalin/bsnes-mt.git
synced 2025-04-02 10:21:42 -04:00
52 lines
1.6 KiB
C++
52 lines
1.6 KiB
C++
//MCC - Memory Controller Chip
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//Custom logic chip inside the BS-X Satellaview base cartridge
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struct MCC {
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ReadableMemory rom;
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WritableMemory psram;
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//mcc.cpp
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auto unload() -> void;
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auto power() -> void;
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auto commit() -> void;
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auto read(uint address, uint8 data) -> uint8;
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auto write(uint address, uint8 data) -> void;
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auto mcuRead(uint address, uint8 data) -> uint8;
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auto mcuWrite(uint address, uint8 data) -> void;
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auto mcuAccess(bool mode, uint address, uint8 data) -> uint8;
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auto romAccess(bool mode, uint address, uint8 data) -> uint8;
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auto psramAccess(bool mode, uint address, uint8 data) -> uint8;
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auto exAccess(bool mode, uint address, uint8 data) -> uint8;
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auto bsAccess(bool mode, uint address, uint8 data) -> uint8;
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//serialization.cpp
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auto serialize(serializer&) -> void;
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private:
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struct IRQ {
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uint1 flag; //bit 0
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uint1 enable; //bit 1
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} irq;
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struct Registers {
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uint1 mapping; //bit 2 (0 = ignore A15; 1 = use A15)
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uint1 psramEnableLo; //bit 3
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uint1 psramEnableHi; //bit 4
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uint2 psramMapping; //bits 5-6
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uint1 romEnableLo; //bit 7
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uint1 romEnableHi; //bit 8
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uint1 exEnableLo; //bit 9
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uint1 exEnableHi; //bit 10
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uint1 exMapping; //bit 11
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uint1 internallyWritable; //bit 12 (1 = MCC allows writes to BS Memory Cassette)
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uint1 externallyWritable; //bit 13 (1 = BS Memory Cassette allows writes to flash memory)
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} r, w;
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//bit 14 = commit
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//bit 15 = unknown (test register interface?)
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};
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extern MCC mcc;
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