mirror of
https://github.com/Marat-Tanalin/bsnes-mt.git
synced 2025-04-02 10:21:42 -04:00
273 lines
8.5 KiB
C++
273 lines
8.5 KiB
C++
auto HitachiDSP::isROM(uint address) -> bool {
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return (bool)addressROM(address);
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}
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auto HitachiDSP::isRAM(uint address) -> bool {
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return (bool)addressRAM(address);
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}
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auto HitachiDSP::read(uint address) -> uint8 {
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if(auto linear = addressROM (address)) return readROM (*linear);
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if(auto linear = addressRAM (address)) return readRAM (*linear);
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if(auto linear = addressDRAM(address)) return readDRAM(*linear);
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if(auto linear = addressIO (address)) return readIO (*linear);
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return 0x00;
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}
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auto HitachiDSP::write(uint address, uint8 data) -> void {
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if(auto linear = addressROM (address)) return writeROM (*linear, data);
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if(auto linear = addressRAM (address)) return writeRAM (*linear, data);
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if(auto linear = addressDRAM(address)) return writeDRAM(*linear, data);
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if(auto linear = addressIO (address)) return writeIO (*linear, data);
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}
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//
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auto HitachiDSP::addressROM(uint address) const -> maybe<uint> {
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if(Mapping == 0) {
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//00-3f,80-bf:8000-ffff; c0-ff:0000-ffff
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if((address & 0x408000) == 0x008000 || (address & 0xc00000) == 0xc00000) {
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address = (address & 0x3f0000) >> 1 | (address & 0x7fff);
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return {address & 0x1fffff};
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}
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} else {
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//00-3f,80-bf:8000-ffff; c0-ff:0000-ffff
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if((address & 0x408000) == 0x008000 || (address & 0xc00000) == 0xc00000) {
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return {address & 0x3fffff};
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}
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}
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return {};
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}
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auto HitachiDSP::readROM(uint address, uint8 data) -> uint8 {
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if(hitachidsp.active() || !busy()) {
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address = bus.mirror(address, rom.size());
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//if(Roms == 2 && mmio.r1f52 == 1 && address >= (bit::round(rom.size()) >> 1)) return 0x00;
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return rom.read(address, data);
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}
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//DSP has the bus acquired: CPU reads from 00:ffc0-ffff return IO registers (including reset vector overrides)
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if(Mapping == 0 && (address & 0xbfffc0) == 0x007fc0) return readIO(0x7f40 | address & 0x3f);
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if(Mapping == 1 && (address & 0xbfffc0) == 0x00ffc0) return readIO(0x7f40 | address & 0x3f);
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return data;
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}
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auto HitachiDSP::writeROM(uint address, uint8 data) -> void {
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}
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//
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auto HitachiDSP::addressRAM(uint address) const -> maybe<uint> {
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if(Mapping == 0) {
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//70-77:0000-7fff
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if((address & 0xf88000) == 0x700000) {
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address = (address & 0x070000) >> 1 | (address & 0x7fff);
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return {address & 0x03ffff};
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}
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} else {
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//30-3f,b0-bf:6000-7fff
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if((address & 0x70e000) == 0x306000) {
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address = (address & 0x0f0000) >> 3 | (address & 0x1fff);
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return {address & 0x01ffff};
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}
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}
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return {};
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}
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auto HitachiDSP::readRAM(uint address, uint8 data) -> uint8 {
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if(ram.size() == 0) return 0x00; //not open bus
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return ram.read(bus.mirror(address, ram.size()), data);
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}
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auto HitachiDSP::writeRAM(uint address, uint8 data) -> void {
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if(ram.size() == 0) return;
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return ram.write(bus.mirror(address, ram.size()), data);
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}
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//
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auto HitachiDSP::addressDRAM(uint address) const -> maybe<uint> {
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if(Mapping == 0) {
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//00-3f,80-bf:6000-6bff,7000-7bff
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if((address & 0x40e000) == 0x006000 && (address & 0x0c00) != 0x0c00) {
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return {address & 0x0fff};
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}
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} else {
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//00-2f,80-af:6000-6bff,7000-7bff
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if((address & 0x40e000) == 0x006000 && (address & 0x0c00) != 0x0c00 && (address & 0x300000) != 0x300000) {
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return {address & 0x0fff};
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}
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}
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return {};
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}
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auto HitachiDSP::readDRAM(uint address, uint8 data) -> uint8 {
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address &= 0xfff;
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if(address >= 0xc00) return data;
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return dataRAM[address];
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}
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auto HitachiDSP::writeDRAM(uint address, uint8 data) -> void {
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address &= 0xfff;
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if(address >= 0xc00) return;
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dataRAM[address] = data;
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}
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//
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auto HitachiDSP::addressIO(uint address) const -> maybe<uint> {
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if(Mapping == 0) {
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//00-3f,80-bf:6c00-6fff,7c00-7fff
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if((address & 0x40ec00) == 0x006c00) {
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return {address & 0x03ff};
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}
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} else {
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//00-2f,80-af:6c00-6fff,7c00-7fff
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if((address & 0x40ec00) == 0x006c00 && (address & 0x300000) != 0x300000) {
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return {address & 0x03ff};
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}
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}
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return {};
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}
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auto HitachiDSP::readIO(uint address, uint8 data) -> uint8 {
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address = 0x7c00 | (address & 0x03ff);
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//IO
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switch(address) {
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case 0x7f40: return io.dma.source >> 0;
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case 0x7f41: return io.dma.source >> 8;
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case 0x7f42: return io.dma.source >> 16;
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case 0x7f43: return io.dma.length >> 0;
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case 0x7f44: return io.dma.length >> 8;
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case 0x7f45: return io.dma.target >> 0;
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case 0x7f46: return io.dma.target >> 8;
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case 0x7f47: return io.dma.target >> 16;
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case 0x7f48: return io.cache.page;
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case 0x7f49: return io.cache.base >> 0;
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case 0x7f4a: return io.cache.base >> 8;
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case 0x7f4b: return io.cache.base >> 16;
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case 0x7f4c: return io.cache.lock[0] << 0 | io.cache.lock[1] << 1;
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case 0x7f4d: return io.cache.pb >> 0;
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case 0x7f4e: return io.cache.pb >> 8;
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case 0x7f4f: return io.cache.pc;
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case 0x7f50: return io.wait.ram << 0 | io.wait.rom << 4;
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case 0x7f51: return io.irq;
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case 0x7f52: return io.rom;
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case 0x7f53: case 0x7f54: case 0x7f55: case 0x7f56: case 0x7f57:
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case 0x7f59: case 0x7f5b: case 0x7f5c: case 0x7f5d: case 0x7f5e:
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case 0x7f5f: return io.suspend.enable << 0 | r.i << 1 | running() << 6 | busy() << 7;
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}
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//vectors
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if(address >= 0x7f60 && address <= 0x7f7f) {
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return io.vector[address & 0x1f];
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}
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//registers
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if((address >= 0x7f80 && address <= 0x7faf) || (address >= 0x7fc0 && address <= 0x7fef)) {
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address &= 0x3f;
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switch(address % 3) {
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case 0: return r.gpr[address / 3] >> 0;
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case 1: return r.gpr[address / 3] >> 8;
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case 2: return r.gpr[address / 3] >> 16;
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}
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}
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return 0x00;
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}
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auto HitachiDSP::writeIO(uint address, uint8 data) -> void {
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address = 0x7c00 | (address & 0x03ff);
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//IO
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switch(address) {
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case 0x7f40: io.dma.source = io.dma.source & 0xffff00 | data << 0; return;
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case 0x7f41: io.dma.source = io.dma.source & 0xff00ff | data << 8; return;
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case 0x7f42: io.dma.source = io.dma.source & 0x00ffff | data << 16; return;
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case 0x7f43: io.dma.length = io.dma.length & 0xff00 | data << 0; return;
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case 0x7f44: io.dma.length = io.dma.length & 0x00ff | data << 8; return;
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case 0x7f45: io.dma.target = io.dma.target & 0xffff00 | data << 0; return;
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case 0x7f46: io.dma.target = io.dma.target & 0xff00ff | data << 8; return;
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case 0x7f47: io.dma.target = io.dma.target & 0x00ffff | data << 16;
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if(io.halt) io.dma.enable = 1;
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return;
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case 0x7f48:
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io.cache.page = data & 1;
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if(io.halt) io.cache.enable = 1;
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return;
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case 0x7f49: io.cache.base = io.cache.base & 0xffff00 | data << 0; return;
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case 0x7f4a: io.cache.base = io.cache.base & 0xff00ff | data << 8; return;
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case 0x7f4b: io.cache.base = io.cache.base & 0x00ffff | data << 16; return;
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case 0x7f4c:
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io.cache.lock[0] = bool(data & 1);
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io.cache.lock[1] = bool(data & 2);
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return;
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case 0x7f4d: io.cache.pb = io.cache.pb & 0xff00 | data << 0; return;
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case 0x7f4e: io.cache.pb = io.cache.pb & 0x00ff | data << 8; return;
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case 0x7f4f:
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io.cache.pc = data;
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if(io.halt) {
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io.halt = 0;
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r.pb = io.cache.pb;
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r.pc = io.cache.pc;
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}
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return;
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case 0x7f50:
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io.wait.ram = data >> 0 & 7;
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io.wait.rom = data >> 4 & 7;
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return;
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case 0x7f51:
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io.irq = data & 1;
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if(io.irq == 1) cpu.irq(r.i = 0);
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return;
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case 0x7f52:
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io.rom = data & 1;
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return;
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case 0x7f53:
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io.lock = 0;
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io.halt = 1;
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return;
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case 0x7f55: io.suspend.enable = 1; io.suspend.duration = 0; return; //indefinite
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case 0x7f56: io.suspend.enable = 1; io.suspend.duration = 32; return;
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case 0x7f57: io.suspend.enable = 1; io.suspend.duration = 64; return;
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case 0x7f58: io.suspend.enable = 1; io.suspend.duration = 96; return;
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case 0x7f59: io.suspend.enable = 1; io.suspend.duration = 128; return;
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case 0x7f5a: io.suspend.enable = 1; io.suspend.duration = 160; return;
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case 0x7f5b: io.suspend.enable = 1; io.suspend.duration = 192; return;
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case 0x7f5c: io.suspend.enable = 1; io.suspend.duration = 224; return;
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case 0x7f5d: io.suspend.enable = 0; return; //resume
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case 0x7f5e:
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r.i = 0; //does not deassert CPU IRQ line
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return;
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}
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//vectors
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if(address >= 0x7f60 && address <= 0x7f7f) {
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io.vector[address & 0x1f] = data;
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return;
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}
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//registers
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if((address >= 0x7f80 && address <= 0x7faf) || (address >= 0x7fc0 && address <= 0x7fef)) {
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address &= 0x3f;
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switch(address % 3) {
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case 0: r.gpr[address / 3] = r.gpr[address / 3] & 0xffff00 | data << 0; break;
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case 1: r.gpr[address / 3] = r.gpr[address / 3] & 0xff00ff | data << 8; break;
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case 2: r.gpr[address / 3] = r.gpr[address / 3] & 0x00ffff | data << 16; break;
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}
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return;
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}
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}
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