mirror of
https://github.com/Michael-Prince-Sharpe/bsnes-classic.git
synced 2025-04-02 10:21:42 -04:00
224 lines
6.9 KiB
C++
224 lines
6.9 KiB
C++
#ifdef SA1_CPP
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VBRBus vbrbus;
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SA1Bus sa1bus;
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namespace memory {
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StaticRAM iram(2048);
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UnmappedSA1 sa1_unmapped;
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//accessed by:
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VSPROM vsprom; //S-CPU + SA-1
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CPUIRAM cpuiram; //S-CPU
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SA1IRAM sa1iram; //SA-1
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SA1BWRAM sa1bwram; //SA-1
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CC1BWRAM cc1bwram; //S-CPU
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BitmapRAM bitmapram; //SA-1
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}
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//$230c (VDPL), $230d (VDPH) use this bus to read variable-length data.
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//this is used both to avoid VBR-reads from accessing MMIO registers, and
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//to avoid syncing the S-CPU and SA-1*; as both chips are able to access
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//these ports.
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//(* eg, memory::cartram is used directly, as memory::sa1bwram syncs to the S-CPU)
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void VBRBus::init() {
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map(MapMode::Direct, 0x00, 0xff, 0x0000, 0xffff, memory::sa1_unmapped);
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map(MapMode::Linear, 0x00, 0x3f, 0x0000, 0x07ff, memory::iram);
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map(MapMode::Linear, 0x00, 0x3f, 0x3000, 0x37ff, memory::iram);
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map(MapMode::Linear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cartram);
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map(MapMode::Linear, 0x00, 0x3f, 0x8000, 0xffff, memory::vsprom);
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map(MapMode::Linear, 0x40, 0x4f, 0x0000, 0xffff, memory::cartram);
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map(MapMode::Linear, 0x80, 0xbf, 0x0000, 0x07ff, memory::iram);
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map(MapMode::Linear, 0x80, 0xbf, 0x3000, 0x37ff, memory::iram);
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map(MapMode::Linear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cartram);
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map(MapMode::Linear, 0x80, 0xbf, 0x8000, 0xffff, memory::vsprom);
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map(MapMode::Linear, 0xc0, 0xff, 0x0000, 0xffff, memory::vsprom);
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}
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void SA1Bus::init() {
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map(MapMode::Direct, 0x00, 0xff, 0x0000, 0xffff, memory::sa1_unmapped);
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map(MapMode::Linear, 0x00, 0x3f, 0x0000, 0x07ff, memory::sa1iram);
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map(MapMode::Shadow, 0x00, 0x3f, 0x2200, 0x23ff, memory::mmio);
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map(MapMode::Linear, 0x00, 0x3f, 0x3000, 0x37ff, memory::sa1iram);
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map(MapMode::Linear, 0x00, 0x3f, 0x6000, 0x7fff, memory::sa1bwram);
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map(MapMode::Linear, 0x00, 0x3f, 0x8000, 0xffff, memory::vsprom);
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map(MapMode::Linear, 0x40, 0x4f, 0x0000, 0xffff, memory::sa1bwram);
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map(MapMode::Linear, 0x60, 0x6f, 0x0000, 0xffff, memory::bitmapram);
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map(MapMode::Linear, 0x80, 0xbf, 0x0000, 0x07ff, memory::sa1iram);
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map(MapMode::Shadow, 0x80, 0xbf, 0x2200, 0x23ff, memory::mmio);
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map(MapMode::Linear, 0x80, 0xbf, 0x3000, 0x37ff, memory::sa1iram);
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map(MapMode::Linear, 0x80, 0xbf, 0x6000, 0x7fff, memory::sa1bwram);
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map(MapMode::Linear, 0x80, 0xbf, 0x8000, 0xffff, memory::vsprom);
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map(MapMode::Linear, 0xc0, 0xff, 0x0000, 0xffff, memory::vsprom);
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}
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unsigned UnmappedSA1::size() const { return 16 * 1024 * 1024; }
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uint8 UnmappedSA1::read(unsigned) { return sa1.regs.mdr; }
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void UnmappedSA1::write(unsigned, uint8) {}
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//======
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//VSPROM
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//======
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//this class maps $00:[ff00-ffff] for the purpose of supporting:
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//$2209.d6 IVSW (S-CPU IRQ vector selection) (0 = cart, 1 = SA-1)
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//$2209.d4 NVSW (S-CPU NMI vector selection) (0 = cart, 1 = SA-1)
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//when set, vector addresses are over-ridden with SA-1 register settings:
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//SIV = S-CPU IRQ vector address override
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//SNV = S-CPU NMI vector address override
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//
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//$00:[ffea-ffeb|ffee-ffef] are special cased on read;
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//all other addresses return original mapped data.
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unsigned VSPROM::size() const {
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return memory::cartrom.size();
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}
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uint8 VSPROM::read(unsigned addr) {
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//use $7fex instead of $ffex due to linear mapping of 32k granularity ROM data
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if((addr & 0xffffe0) == 0x007fe0) {
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if(addr == 0x7fea && sa1.mmio.cpu_nvsw) return sa1.mmio.snv >> 0;
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if(addr == 0x7feb && sa1.mmio.cpu_nvsw) return sa1.mmio.snv >> 8;
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if(addr == 0x7fee && sa1.mmio.cpu_ivsw) return sa1.mmio.siv >> 0;
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if(addr == 0x7fef && sa1.mmio.cpu_ivsw) return sa1.mmio.siv >> 8;
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}
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return memory::cartrom.read(addr);
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}
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void VSPROM::write(unsigned addr, uint8 data) {
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memory::cartrom.write(addr, data);
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}
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//=======
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//SA1IRAM
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//=======
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unsigned SA1IRAM::size() const {
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return memory::iram.size();
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}
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uint8 SA1IRAM::read(unsigned addr) {
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if(!debugger_access()) sa1.synchronize_cpu();
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return memory::iram.read(addr);
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}
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void SA1IRAM::write(unsigned addr, uint8 data) {
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if(!debugger_access()) sa1.synchronize_cpu();
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memory::iram.write(addr, data);
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}
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//=======
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//CPUIRAM
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//=======
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unsigned CPUIRAM::size() const {
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return memory::iram.size();
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}
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uint8 CPUIRAM::read(unsigned addr) {
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if(!debugger_access()) cpu.synchronize_coprocessor();
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return memory::iram.read(addr);
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}
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void CPUIRAM::write(unsigned addr, uint8 data) {
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if(!debugger_access()) cpu.synchronize_coprocessor();
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memory::iram.write(addr, data);
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}
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//========
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//SA1BWRAM
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//========
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unsigned SA1BWRAM::size() const {
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return memory::cartram.size();
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}
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uint8 SA1BWRAM::read(unsigned addr) {
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if(!debugger_access()) sa1.synchronize_cpu();
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return memory::cartram.read(addr);
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}
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void SA1BWRAM::write(unsigned addr, uint8 data) {
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if(!debugger_access()) sa1.synchronize_cpu();
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memory::cartram.write(addr, data);
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}
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//========
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//CC1BWRAM
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//========
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unsigned CC1BWRAM::size() const {
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return memory::cartram.size();
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}
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uint8 CC1BWRAM::read(unsigned addr) {
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if(!debugger_access()) cpu.synchronize_coprocessor();
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if(dma) return sa1.dma_cc1_read(addr);
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return memory::cartram.read(addr);
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}
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void CC1BWRAM::write(unsigned addr, uint8 data) {
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if(!debugger_access()) cpu.synchronize_coprocessor();
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memory::cartram.write(addr, data);
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}
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//=========
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//BitmapRAM
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//=========
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unsigned BitmapRAM::size() const {
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return 0x100000;
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}
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uint8 BitmapRAM::read(unsigned addr) {
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if(!debugger_access()) sa1.synchronize_cpu();
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if(sa1.mmio.bbf == 0) {
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//4bpp
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unsigned shift = addr & 1;
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addr = (addr >> 1) & (memory::cartram.size() - 1);
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switch(shift) { default:
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case 0: return (memory::cartram.read(addr) >> 0) & 15;
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case 1: return (memory::cartram.read(addr) >> 4) & 15;
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}
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} else {
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//2bpp
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unsigned shift = addr & 3;
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addr = (addr >> 2) & (memory::cartram.size() - 1);
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switch(shift) { default:
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case 0: return (memory::cartram.read(addr) >> 0) & 3;
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case 1: return (memory::cartram.read(addr) >> 2) & 3;
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case 2: return (memory::cartram.read(addr) >> 4) & 3;
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case 3: return (memory::cartram.read(addr) >> 6) & 3;
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}
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}
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}
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void BitmapRAM::write(unsigned addr, uint8 data) {
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if(!debugger_access()) sa1.synchronize_cpu();
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if(sa1.mmio.bbf == 0) {
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//4bpp
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unsigned shift = addr & 1;
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addr = (addr >> 1) & (memory::cartram.size() - 1);
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switch(shift) { default:
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case 0: data = (memory::cartram.read(addr) & 0xf0) | ((data & 15) << 0); break;
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case 1: data = (memory::cartram.read(addr) & 0x0f) | ((data & 15) << 4); break;
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}
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} else {
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//2bpp
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unsigned shift = addr & 3;
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addr = (addr >> 2) & (memory::cartram.size() - 1);
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switch(shift) { default:
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case 0: data = (memory::cartram.read(addr) & 0xfc) | ((data & 3) << 0); break;
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case 1: data = (memory::cartram.read(addr) & 0xf3) | ((data & 3) << 2); break;
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case 2: data = (memory::cartram.read(addr) & 0xcf) | ((data & 3) << 4); break;
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case 3: data = (memory::cartram.read(addr) & 0x3f) | ((data & 3) << 6); break;
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}
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}
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memory::cartram.write(addr, data);
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}
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#endif
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