mirror of
https://github.com/Vita3K/Vita3K.git
synced 2025-04-02 11:02:10 -04:00
1628 lines
No EOL
34 KiB
YAML
1628 lines
No EOL
34 KiB
YAML
VMAD2:
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description: Vector multiply-add (Normal version)
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members:
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- opcode1: '00000'
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- dat_fmt:
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offset: 58
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size: 1
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|
- pred:
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offset: 56
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size: 2
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|
- skipinv:
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offset: 55
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|
size: 1
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|
- src0_swiz_bits2:
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size: 1
|
|
offset: 53
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|
- syncstart:
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offset: 52
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size: 1
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|
- src0_abs:
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offset: 50
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size: 1
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- src1_bank_ext:
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offset: 49
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size: 1
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- src2_bank_ext:
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offset: 48
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size: 1
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- src2_swiz:
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offset: 45
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size: 3
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|
- src1_swiz_bit2:
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offset: 44
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size: 1
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- nosched:
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offset: 43
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size: 1
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- dest_mask:
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offset: 39
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size: 4
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- src1_mod:
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size: 2
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offset: 37
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- src2_mod:
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size: 2
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offset: 35
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- src0_bank:
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size: 1
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offset: 34
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- dest_bank:
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size: 2
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offset: 32
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- src1_bank:
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size: 2
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offset: 30
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- src2_bank:
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size: 2
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offset: 28
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- dest_n:
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offset: 22
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size: 6
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- src1_swiz_bits01:
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size: 2
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offset: 20
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- src0_swiz_bits01:
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size: 2
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offset: 18
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- src0_n:
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size: 6
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offset: 12
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- src1_n:
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size: 6
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offset: 6
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- src2_n:
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size: 6
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offset: 0
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V32NMAD:
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description: Vector operations except for MAD (F32)
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members:
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- opcode1: '00001'
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- pred:
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size: 3
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type: ExtVecPredicate
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- skipinv:
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size: 1
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type: bool
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- src1_swiz_10_11:
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size: 2
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- syncstart:
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size: 1
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type: bool
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- dest_bank_ext: 1
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- src1_swiz_9: 1
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- src1_bank_ext: 1
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- src2_bank_ext: 1
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- src2_swiz: 4
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- nosched:
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size: 1
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type: bool
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- dest_mask:
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size: 4
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type: Imm4
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- src1_mod: 2
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- src2_mod: 1
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- src1_swiz_7_8: 2
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- dest_bank_sel: 2
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- src1_bank_sel: 2
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- src2_bank_sel: 2
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- dest_n: 6
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- src1_swiz_0_6: 7
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- op2: 3
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- src1_n: 6
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- src2_n: 6
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V16NMAD:
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description: Vector operations except for MAD (F16)
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members:
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- opcode1: '00010'
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- pred:
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size: 3
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type: ExtVecPredicate
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- skipinv:
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size: 1
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type: bool
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- src1_swiz_10_11:
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size: 2
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- syncstart:
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size: 1
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type: bool
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- dest_bank_ext: 1
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- src1_swiz_9: 1
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- src1_bank_ext: 1
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- src2_bank_ext: 1
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- src2_swiz: 4
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- nosched:
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size: 1
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type: bool
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- dest_mask:
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size: 4
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type: Imm4
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- src1_mod: 2
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- src2_mod: 1
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- src1_swiz_7_8: 2
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- dest_bank_sel: 2
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- src1_bank_sel: 2
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- src2_bank_sel: 2
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- dest_n: 6
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- src1_swiz_0_6: 7
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- op2: 3
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- src1_n: 6
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- src2_n: 6
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VMAD:
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description: "Vector multiply-add"
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members:
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- opcode1: '00011'
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- pred:
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size: 3
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type: ExtVecPredicate
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- skipinv: 1
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- gpi1_swiz_ext: 1
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- present_bit_1: '1'
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- opcode2: 1
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- dest_use_bank_ext: 1
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- end: 1
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- src1_bank_ext: 1
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- repeat_mode:
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size: 2
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type: RepeatMode
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- gpi0_abs: 1
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- repeat_count:
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size: 2
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type: RepeatCount
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- nosched:
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size: 1
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type: bool
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- write_mask: 4
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- src1_neg: 1
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- src1_abs: 1
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- gpi1_neg: 1
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- gpi1_abs: 1
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- gpi0_swiz_ext: 1
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- dest_bank: 2
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- src1_bank: 2
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- gpi0_n: 2
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- dest_n: 6
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- gpi0_swiz: 4
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- gpi1_swiz: 4
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- gpi1_n: 2
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- gpi0_neg: 1
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- src1_swiz_ext:
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size: 1
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offset: 10
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- src1_swiz: 4
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- src1_n: 6
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VDP:
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description: Vector Dot Product (single issue)
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members:
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- opcode1: '00011'
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- pred:
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size: 3
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type: ExtVecPredicate
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- skipinv: 1
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- clip_plane_enable:
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size: 1
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type: bool
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- present_bit_0: '0'
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- opcode2: 1
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- dest_use_bank_ext: 1
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- end: 1
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- src1_bank_ext: 1
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- repeat_mode:
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size: 2
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type: RepeatMode
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- gpi0_abs: 1
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- repeat_count:
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size: 2
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type: RepeatCount
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- nosched:
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size: 1
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type: bool
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- write_mask: 4
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- src1_neg: 1
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- src1_abs: 1
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- clip_plane_n: 3
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- dest_bank: 2
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- src1_bank: 2
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- gpi0_n: 2
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- dest_n: 6
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- gpi0_swiz: 4
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- src1_swiz_w: 3
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- src1_swiz_z: 3
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- src1_swiz_y: 3
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- src1_swiz_x: 3
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- src1_n: 6
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# 00100 00101
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VDUAL:
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description: Dual issue instruction
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members:
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- op1: '0010'
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- comp_count_type:
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size: 1
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offset: 59
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- gpi1_neg:
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size: 1
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offset: 58
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- sv_pred:
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size: 2
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offset: 56
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- skipinv:
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size: 1
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offset: 55
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- dual_op1_ext_vec3_or_has_w_vec4:
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size: 1
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offset: 54
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- type_f16:
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size: 1
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offset: 53
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type: bool
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- gpi1_swizz_ext:
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size: 1
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offset: 52
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- unified_store_swizz:
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size: 4
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offset: 48
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- unified_store_neg:
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size: 1
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offset: 47
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- dual_op1:
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size: 3
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offset: 44
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- dual_op2_ext:
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size: 1
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offset: 43
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- prim_ustore:
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offset: 42
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size: 1
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type: bool
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- gpi0_swizz:
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offset: 38
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size: 4
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- gpi1_swizz:
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offset: 34
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size: 4
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- prim_dest_bank:
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size: 2
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offset: 32
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- unified_store_slot_bank:
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size: 2
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offset: 30
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- prim_dest_num_gpi_case:
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size: 2
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offset: 28
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- prim_dest_num:
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size: 7
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offset: 21
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- dual_op2:
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size: 3
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offset: 18
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- src_config:
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size: 2
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offset: 16
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- gpi2_slot_num_bit_1:
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size: 1
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offset: 15
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- gpi2_slot_num_bit_0_or_unified_store_abs:
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size: 1
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offset: 14
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- gpi1_slot_num:
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size: 2
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offset: 12
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- gpi0_slot_num:
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size: 2
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offset: 10
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- write_mask_non_gpi:
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size: 3
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offset: 7
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- unified_store_slot_num:
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size: 7
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offset: 0
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VCOMP:
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description: Vector Complex Instructions
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members:
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- op1: '00110'
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- pred:
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size: 3
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type: ExtPredicate
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offset: 56
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- skipinv:
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size: 1
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type: bool
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offset: 55
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- dest_type:
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size: 2
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offset: 53
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- syncstart:
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size: 1
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type: bool
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offset: 52
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- dest_bank_ext:
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size: 1
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type: bool
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offset: 51
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- end:
|
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size: 1
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type: bool
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offset: 50
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- src1_bank_ext:
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size: 1
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type: bool
|
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offset: 49
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- repeat_count:
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size: 4
|
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type: RepeatCount
|
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offset: 44
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- nosched:
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size: 1
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offset: 43
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type: bool
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- op2:
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size: 2
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offset: 41
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- src_type:
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size: 2
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offset: 39
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- src1_mod:
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size: 2
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offset: 37
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- src_comp:
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size: 2
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offset: 35
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- dest_bank:
|
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size: 2
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offset: 32
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- src1_bank:
|
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size: 2
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offset: 30
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- dest_n:
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offset: 21
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size: 7
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- src1_n:
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offset: 7
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size: 7
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- write_mask:
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size: 4
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offset: 0
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|
VMOV:
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description: Vector move
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members:
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- op1: '00111'
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- pred:
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size: 3
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type: ExtPredicate
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- skipinv:
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size: 1
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type: bool
|
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- test_bit_2: 1
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- src0_comp_sel: 1
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- syncstart:
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size: 1
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type: bool
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- dest_bank_ext: 1
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- end_or_src0_bank_ext: 1
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- src1_bank_ext: 1
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- src2_bank_ext: 1
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- move_type:
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size: 2
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type: MoveType
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- repeat_count:
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size: 2
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type: RepeatCount
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- nosched:
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size: 1
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type: bool
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- move_data_type:
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size: 3
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type: DataType
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- test_bit_1: 1
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- src0_swiz: 4
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- src0_bank_sel: 1
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- dest_bank_sel: 2
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- src1_bank_sel: 2
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- src2_bank_sel: 2
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- dest_mask:
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size: 4
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type: Imm4
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- dest_n: 6
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- src0_n: 6
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- src1_n: 6
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- src2_n: 6
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|
VPCK:
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description: Vector pack/unpack
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members:
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- op1: '01000'
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- pred:
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size: 3
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type: ExtPredicate
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- skipinv:
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size: 1
|
|
type: bool
|
|
- nosched:
|
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size: 1
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type: bool
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- unknown: 1
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- syncstart:
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size: 1
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|
type: bool
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- dest_bank_ext: 1
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- end: 1
|
|
- src1_bank_ext: 1
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- src2_bank_ext: 1
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|
- repeat_count:
|
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size: 3
|
|
type: RepeatCount
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|
offset: 44
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|
- src_fmt: 3
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- dest_fmt: 3
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- dest_mask: 4
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- dest_bank_sel: 2
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- src1_bank_sel: 2
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- src2_bank_sel: 2
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- dest_n:
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offset: 21
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size: 7
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- comp_sel_3:
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offset: 19
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size: 2
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- scale:
|
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offset: 18
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size: 1
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- comp_sel_1:
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offset: 16
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size: 2
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|
- comp_sel_2:
|
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offset: 14
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size: 2
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|
- src1_n:
|
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offset: 8
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size: 6
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|
- comp0_sel_bit1:
|
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offset: 7
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|
size: 1
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|
- src2_n:
|
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offset: 1
|
|
size: 6
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|
- comp_sel_0_bit0:
|
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offset: 0
|
|
size: 1
|
|
VTST:
|
|
description: Test Instructions
|
|
members:
|
|
- op1: '01001'
|
|
- pred:
|
|
size: 3
|
|
offset: 56
|
|
type: ExtPredicate
|
|
- skipinv:
|
|
size: 1
|
|
offset: 55
|
|
- onceonly:
|
|
size: 1
|
|
offset: 53
|
|
- syncstart:
|
|
size: 1
|
|
offset: 52
|
|
- dest_ext:
|
|
size: 1
|
|
offset: 51
|
|
- src1_neg:
|
|
size: 1
|
|
offset: 50
|
|
- src1_ext:
|
|
size: 1
|
|
offset: 49
|
|
- src2_ext:
|
|
size: 1
|
|
offset: 48
|
|
- prec:
|
|
size: 1
|
|
offset: 47
|
|
- src2_vscomp:
|
|
size: 1
|
|
offset: 46
|
|
- rpt_count:
|
|
type: RepeatCount
|
|
size: 2
|
|
offset: 44
|
|
- sign_test:
|
|
size: 2
|
|
offset: 42
|
|
- zero_test:
|
|
size: 2
|
|
offset: 40
|
|
- test_crcomb_and:
|
|
size: 1
|
|
offset: 39
|
|
- chan_cc:
|
|
size: 3
|
|
offset: 36
|
|
- pdst_n:
|
|
size: 2
|
|
offset: 34
|
|
- dest_bank:
|
|
size: 2
|
|
offset: 32
|
|
- src1_bank:
|
|
size: 2
|
|
offset: 30
|
|
- src2_bank:
|
|
size: 2
|
|
offset: 28
|
|
- dest_n:
|
|
offset: 21
|
|
size: 7
|
|
- test_wben:
|
|
offset: 20
|
|
size: 1
|
|
- alu_sel:
|
|
size: 2
|
|
offset: 18
|
|
- alu_op:
|
|
size: 4
|
|
offset: 14
|
|
- src1_n:
|
|
size: 7
|
|
offset: 7
|
|
- src2_n:
|
|
size: 7
|
|
offset: 0
|
|
VTSTMSK:
|
|
description: Test mask Instructions
|
|
members:
|
|
- op1: '01111'
|
|
- pred:
|
|
size: 3
|
|
offset: 56
|
|
type: ExtPredicate
|
|
- skipinv:
|
|
size: 1
|
|
offset: 55
|
|
- onceonly:
|
|
size: 1
|
|
offset: 53
|
|
- syncstart:
|
|
size: 1
|
|
offset: 52
|
|
- dest_ext:
|
|
size: 1
|
|
offset: 51
|
|
- test_flag_2:
|
|
size: 1
|
|
offset: 50
|
|
- src1_ext:
|
|
size: 1
|
|
offset: 49
|
|
- src2_ext:
|
|
size: 1
|
|
offset: 48
|
|
- prec:
|
|
size: 1
|
|
offset: 47
|
|
- src2_vscomp:
|
|
size: 1
|
|
offset: 46
|
|
- rpt_count:
|
|
type: RepeatCount
|
|
size: 2
|
|
offset: 44
|
|
- sign_test:
|
|
size: 2
|
|
offset: 42
|
|
- zero_test:
|
|
size: 2
|
|
offset: 40
|
|
- test_crcomb_and:
|
|
size: 1
|
|
offset: 39
|
|
- tst_mask_type:
|
|
size: 2
|
|
offset: 36
|
|
- dest_bank:
|
|
size: 2
|
|
offset: 32
|
|
- src1_bank:
|
|
size: 2
|
|
offset: 30
|
|
- src2_bank:
|
|
size: 2
|
|
offset: 28
|
|
- dest_n:
|
|
offset: 21
|
|
size: 7
|
|
- test_wben:
|
|
offset: 20
|
|
size: 1
|
|
- alu_sel:
|
|
size: 2
|
|
offset: 18
|
|
- alu_op:
|
|
size: 4
|
|
offset: 14
|
|
- src1_n:
|
|
size: 7
|
|
offset: 7
|
|
- src2_n:
|
|
size: 7
|
|
offset: 0
|
|
# 01010 01011 01100 01101 01110
|
|
VBW:
|
|
description: Bitwise Instructions
|
|
members:
|
|
- op1_cnst: '01'
|
|
- op1: 3
|
|
- pred:
|
|
type: ExtPredicate
|
|
size: 3
|
|
- skipinv:
|
|
size: 1
|
|
- nosched:
|
|
size: 1
|
|
- repeat_sel:
|
|
type: bool
|
|
size: 1
|
|
- sync_start: 1
|
|
- dest_ext: 1
|
|
- end: 1
|
|
- src1_ext: 1
|
|
- src2_ext: 1
|
|
- repeat_count:
|
|
type: RepeatCount
|
|
size: 4
|
|
- src2_invert: 1
|
|
- src2_rot: 5
|
|
- src2_exth: 2
|
|
- op2: 1
|
|
- bitwise_partial: 1
|
|
- dest_bank: 2
|
|
- src1_bank: 2
|
|
- src2_bank: 2
|
|
- dest_n: 7
|
|
- src2_sel: 7
|
|
- src1_n: 7
|
|
- src2_n: 7
|
|
SOP2:
|
|
description: Sum of Products with 2 sources
|
|
members:
|
|
- op1: '10000'
|
|
- pred:
|
|
offset: 57
|
|
size: 2
|
|
- cmod1:
|
|
offset: 56
|
|
size: 1
|
|
- skipinv:
|
|
offset: 55
|
|
size: 1
|
|
- nosched:
|
|
offset: 54
|
|
size: 1
|
|
- asel1:
|
|
offset: 52
|
|
size: 2
|
|
- dest_bank_ext:
|
|
offset: 51
|
|
size: 1
|
|
- end:
|
|
offset: 50
|
|
size: 1
|
|
- src1_bank_ext:
|
|
offset: 49
|
|
size: 1
|
|
- src2_bank_ext:
|
|
offset: 48
|
|
size: 1
|
|
- cmod2:
|
|
offset: 47
|
|
size: 1
|
|
- count:
|
|
offset: 44
|
|
size: 3
|
|
- amod1:
|
|
offset: 43
|
|
size: 1
|
|
- asel2:
|
|
offset: 41
|
|
size: 2
|
|
- csel1:
|
|
offset: 38
|
|
size: 3
|
|
- csel2:
|
|
offset: 35
|
|
size: 3
|
|
- amod2:
|
|
offset: 34
|
|
size: 1
|
|
- dest_bank:
|
|
offset: 32
|
|
size: 2
|
|
- src1_bank:
|
|
offset: 30
|
|
size: 2
|
|
- src2_bank:
|
|
offset: 28
|
|
size: 2
|
|
- dest_n:
|
|
offset: 21
|
|
size: 7
|
|
- src1_mod:
|
|
offset: 20
|
|
size: 1
|
|
- cop:
|
|
offset: 18
|
|
size: 2
|
|
- aop:
|
|
offset: 16
|
|
size: 2
|
|
- asrc1_mod:
|
|
offset: 15
|
|
size: 1
|
|
- dest_mod:
|
|
offset: 14
|
|
size: 1
|
|
- src1_n:
|
|
offset: 7
|
|
size: 7
|
|
- src2_n:
|
|
offset: 0
|
|
size: 7
|
|
SOP2M:
|
|
description: Sum of Products with 2 sources and a write mask
|
|
members:
|
|
- opcode1: '10010'
|
|
- pred:
|
|
offset: 57
|
|
size: 2
|
|
- mod1:
|
|
offset: 56
|
|
size: 1
|
|
- skipinv:
|
|
offset: 55
|
|
size: 1
|
|
- nosched:
|
|
offset: 54
|
|
size: 1
|
|
- cop:
|
|
offset: 52
|
|
size: 2
|
|
- destbankext:
|
|
offset: 51
|
|
size: 1
|
|
- end:
|
|
offset: 50
|
|
size: 1
|
|
- src1bankext:
|
|
offset: 49
|
|
size: 1
|
|
- src2bankext:
|
|
offset: 48
|
|
size: 1
|
|
- mod2:
|
|
offset: 47
|
|
size: 1
|
|
- wmask:
|
|
offset: 43
|
|
size: 4
|
|
- aop:
|
|
offset: 41
|
|
size: 2
|
|
- sel1:
|
|
offset: 38
|
|
size: 3
|
|
- sel2:
|
|
offset: 35
|
|
size: 3
|
|
- destbank:
|
|
offset: 32
|
|
size: 2
|
|
- src1bank:
|
|
offset: 30
|
|
size: 2
|
|
- src2bank:
|
|
offset: 28
|
|
size: 2
|
|
- destnum:
|
|
offset: 21
|
|
size: 7
|
|
- src1num:
|
|
offset: 7
|
|
size: 7
|
|
- src2num:
|
|
offset: 0
|
|
size: 7
|
|
SOP3:
|
|
description: Sum of Products with 3 sources
|
|
members:
|
|
- opcode1: '10001'
|
|
- pred:
|
|
offset: 57
|
|
size: 2
|
|
- mod1:
|
|
offset: 56
|
|
size: 1
|
|
- skipinv:
|
|
offset: 55
|
|
size: 1
|
|
- nosched:
|
|
offset: 54
|
|
size: 1
|
|
- cop:
|
|
offset: 52
|
|
size: 2
|
|
- destbext:
|
|
offset: 51
|
|
size: 1
|
|
- end:
|
|
offset: 50
|
|
size: 1
|
|
- src1bext:
|
|
offset: 49
|
|
size: 1
|
|
- src2bext:
|
|
offset: 48
|
|
size: 1
|
|
- mod2:
|
|
offset: 47
|
|
size: 1
|
|
- wrmask:
|
|
offset: 43
|
|
size: 4
|
|
- aop:
|
|
offset: 41
|
|
size: 2
|
|
- sel1:
|
|
offset: 38
|
|
size: 3
|
|
- sel2:
|
|
offset: 35
|
|
size: 3
|
|
- src0bank:
|
|
offset: 34
|
|
size: 1
|
|
- destbank:
|
|
offset: 32
|
|
size: 2
|
|
- src1bank:
|
|
offset: 30
|
|
size: 2
|
|
- src2bank:
|
|
offset: 28
|
|
size: 2
|
|
- destn:
|
|
offset: 21
|
|
size: 7
|
|
- src0n:
|
|
offset: 14
|
|
size: 7
|
|
- src1n:
|
|
offset: 7
|
|
size: 7
|
|
- src2n:
|
|
offset: 0
|
|
size: 7
|
|
I8MAD:
|
|
description: 8-bit integer Multiply and Add
|
|
members:
|
|
- opcode1: '10011'
|
|
- pred:
|
|
size: 2
|
|
offset: 57
|
|
- cmod1:
|
|
size: 1
|
|
offset: 56
|
|
- skipinv:
|
|
size: 1
|
|
offset: 55
|
|
- nosched:
|
|
size: 1
|
|
offset: 54
|
|
- csel0:
|
|
size: 2
|
|
offset: 52
|
|
- dest_bank_ext:
|
|
size: 1
|
|
offset: 51
|
|
- end:
|
|
size: 1
|
|
offset: 50
|
|
- src1_bank_ext:
|
|
size: 1
|
|
offset: 49
|
|
- src2_bank_ext:
|
|
size: 1
|
|
offset: 48
|
|
- cmod2:
|
|
size: 1
|
|
offset: 47
|
|
- repeat_count:
|
|
size: 3
|
|
offset: 44
|
|
- saturated:
|
|
size: 1
|
|
offset: 43
|
|
- cmod0:
|
|
size: 1
|
|
offset: 42
|
|
- asel0:
|
|
size: 1
|
|
offset: 41
|
|
- amod2:
|
|
size: 1
|
|
offset: 40
|
|
- amod1:
|
|
size: 1
|
|
offset: 39
|
|
- amod0:
|
|
size: 1
|
|
offset: 38
|
|
- csel1:
|
|
size: 1
|
|
offset: 37
|
|
- csel2:
|
|
size: 1
|
|
offset: 36
|
|
- src0_neg:
|
|
size: 1
|
|
offset: 35
|
|
- src0_bank:
|
|
size: 1
|
|
offset: 34
|
|
- dest_bank:
|
|
size: 2
|
|
offset: 32
|
|
- src1_bank:
|
|
size: 2
|
|
offset: 30
|
|
- src2_bank:
|
|
size: 2
|
|
offset: 28
|
|
- dest_num:
|
|
size: 7
|
|
offset: 21
|
|
- src0_num:
|
|
size: 7
|
|
offset: 14
|
|
- src1_num:
|
|
size: 7
|
|
offset: 7
|
|
- src2_num:
|
|
size: 7
|
|
offset: 0
|
|
I16MAD:
|
|
description: 16-bit Integer multiply-add
|
|
members:
|
|
- opcode1: '10100'
|
|
- DONTCARE:
|
|
size: 59
|
|
I32MAD:
|
|
description: 32-bit Integer multiply-add
|
|
members:
|
|
- opcode1: '10101'
|
|
- pred:
|
|
size: 2
|
|
type: ShortPredicate
|
|
- src0_high:
|
|
size: 1
|
|
- DONTCARE:
|
|
size: 1
|
|
- nosched:
|
|
size: 1
|
|
- src1_high:
|
|
size: 1
|
|
- src2_high:
|
|
size: 1
|
|
- dest_bank_ext:
|
|
size: 1
|
|
type: bool
|
|
- end:
|
|
size: 1
|
|
- src1_bank_ext:
|
|
size: 1
|
|
type: bool
|
|
- src2_bank_ext:
|
|
size: 1
|
|
type: bool
|
|
- unk0: '0'
|
|
- repeat_count:
|
|
size: 3
|
|
type: RepeatCount
|
|
- is_signed:
|
|
size: 1
|
|
type: bool
|
|
- is_sat:
|
|
size: 1
|
|
type: bool
|
|
- unk1: '00'
|
|
- src2_type:
|
|
size: 2
|
|
- unk2: '000'
|
|
- src0_bank:
|
|
size: 1
|
|
- dest_bank:
|
|
size: 2
|
|
- src1_bank:
|
|
size: 2
|
|
- src2_bank:
|
|
size: 2
|
|
- dest_n:
|
|
size: 7
|
|
- src0_n:
|
|
size: 7
|
|
- src1_n:
|
|
size: 7
|
|
- src2_n:
|
|
size: 7
|
|
|
|
ILLEGAL22:
|
|
description: Illegal instruction
|
|
members:
|
|
- opcode1: '10110'
|
|
- DONTCARE:
|
|
size: 59
|
|
ILLEGAL23:
|
|
description: Illegal instruction
|
|
members:
|
|
- opcode1: '10111'
|
|
- DONTCARE:
|
|
size: 59
|
|
ILLEGAL24:
|
|
description: Illegal instruction
|
|
members:
|
|
- opcode1: '11000'
|
|
- DONTCARE:
|
|
size: 59
|
|
I8MAD2:
|
|
description: 8-bit Integer multiply-add 2
|
|
members:
|
|
- opcode1: '11001'
|
|
- DONTCARE:
|
|
size: 59
|
|
I32MAD2:
|
|
description: 32-bit Integer multiply-add 2
|
|
members:
|
|
- op1: '11010'
|
|
- pred:
|
|
size: 3
|
|
type: ExtPredicate
|
|
- DONTCARE:
|
|
size: 1
|
|
- nosched:
|
|
size: 1
|
|
- sn:
|
|
size: 2
|
|
- dest_bank_ext:
|
|
size: 1
|
|
type: bool
|
|
- end:
|
|
size: 1
|
|
- src1_bank_ext:
|
|
size: 1
|
|
type: bool
|
|
- src2_bank_ext:
|
|
size: 1
|
|
type: bool
|
|
- src0_bank_ext:
|
|
size: 1
|
|
type: bool
|
|
- count:
|
|
size: 3
|
|
- unk0: '00'
|
|
- is_signed:
|
|
size: 1
|
|
type: bool
|
|
- negative_src1:
|
|
size: 1
|
|
- negative_src2:
|
|
size: 1
|
|
- unk1: '0000'
|
|
- src0_bank:
|
|
size: 1
|
|
- dest_bank:
|
|
size: 2
|
|
- src1_bank:
|
|
size: 2
|
|
- src2_bank:
|
|
size: 2
|
|
- dest_n:
|
|
size: 7
|
|
- src0_n:
|
|
size: 7
|
|
- src1_n:
|
|
size: 7
|
|
- src2_n:
|
|
size: 7
|
|
ILLEGAL27:
|
|
description: Ilegal instruction
|
|
members:
|
|
- opcode1: '11011'
|
|
- DONTCARE:
|
|
size: 59
|
|
SMP:
|
|
description: Sample Instructions
|
|
members:
|
|
- op1: '11100'
|
|
- pred:
|
|
type: ExtPredicate
|
|
offset: 56
|
|
size: 3
|
|
- skipinv:
|
|
size: 1
|
|
offset: 55
|
|
- nosched:
|
|
size: 1
|
|
offset: 54
|
|
- syncstart:
|
|
offset: 52
|
|
size: 1
|
|
- minpack:
|
|
size: 1
|
|
offset: 51
|
|
- src0_ext:
|
|
size: 1
|
|
offset: 50
|
|
- src1_ext:
|
|
offset: 49
|
|
size: 1
|
|
- src2_ext:
|
|
offset: 48
|
|
size: 1
|
|
- fconv_type:
|
|
offset: 46
|
|
size: 2
|
|
- mask_count:
|
|
size: 2
|
|
offset: 44
|
|
- dim:
|
|
size: 2
|
|
offset: 42
|
|
- lod_mode:
|
|
size: 2
|
|
offset: 40
|
|
- dest_use_pa:
|
|
size: 1
|
|
type: bool
|
|
offset: 39
|
|
- sb_mode:
|
|
offset: 37
|
|
size: 2
|
|
- src0_type:
|
|
offset: 35
|
|
size: 2
|
|
- src0_bank:
|
|
size: 1
|
|
offset: 34
|
|
- drc_sel:
|
|
size: 2
|
|
offset: 32
|
|
- src1_bank:
|
|
offset: 30
|
|
size: 2
|
|
- src2_bank:
|
|
offset: 28
|
|
size: 2
|
|
- dest_n:
|
|
size: 7
|
|
offset: 21
|
|
- src0_n:
|
|
size: 7
|
|
offset: 14
|
|
- src1_n:
|
|
size: 7
|
|
offset: 7
|
|
- src2_n:
|
|
size: 7
|
|
offset: 0
|
|
PHAS:
|
|
description: Phase
|
|
members:
|
|
- op1: '11111'
|
|
- op2:
|
|
size: 3
|
|
offset: 56
|
|
match: '010'
|
|
- sprvv:
|
|
size: 1
|
|
offset: 55
|
|
- phas:
|
|
match: '100'
|
|
offset: 52
|
|
size: 3
|
|
- end:
|
|
size: 1
|
|
offset: 51
|
|
- imm:
|
|
size: 1
|
|
offset: 50
|
|
- src1_bank_ext:
|
|
size: 1
|
|
offset: 49
|
|
- src2_bank_ext:
|
|
size: 1
|
|
offset: 48
|
|
- mode:
|
|
size: 1
|
|
offset: 45
|
|
- rate_hi:
|
|
size: 1
|
|
offset: 44
|
|
- rate_lo_or_nosched:
|
|
size: 1
|
|
offset: 43
|
|
- wait_cond:
|
|
size: 3
|
|
offset: 40
|
|
- temp_count:
|
|
size: 8
|
|
offset: 32
|
|
- src1_bank:
|
|
size: 2
|
|
offset: 30
|
|
- src2_bank:
|
|
size: 2
|
|
offset: 28
|
|
- exe_addr_high:
|
|
size: 6
|
|
offset: 14
|
|
- src1_n_or_exe_addr_mid:
|
|
size: 7
|
|
offset: 7
|
|
- src2_n_or_exe_addr_low:
|
|
size: 7
|
|
offset: 0
|
|
NOP:
|
|
description: Nop
|
|
members:
|
|
- op1: '11111'
|
|
- opcat_extra:
|
|
match: '0'
|
|
size: 1
|
|
offset: 54
|
|
- op2_flow_ctrl:
|
|
match: '00'
|
|
size: 2
|
|
offset: 52
|
|
- nop:
|
|
match: '101'
|
|
offset: 38
|
|
size: 3
|
|
BR:
|
|
description: Branch
|
|
members:
|
|
- op1: '11111'
|
|
- pred:
|
|
type: ExtPredicate
|
|
size: 3
|
|
offset: 56
|
|
- syncend:
|
|
size: 1
|
|
offset: 55
|
|
- opcat_extra:
|
|
match: '0'
|
|
size: 1
|
|
offset: 54
|
|
- op2_flow_ctrl:
|
|
match: '00'
|
|
size: 2
|
|
offset: 52
|
|
- exception:
|
|
type: bool
|
|
size: 1
|
|
offset: 51
|
|
- pwait:
|
|
type: bool
|
|
size: 1
|
|
offset: 45
|
|
- sync_ext:
|
|
size: 1
|
|
offset: 44
|
|
- nosched:
|
|
type: bool
|
|
size: 1
|
|
offset: 43
|
|
- br_monitor:
|
|
type: bool
|
|
size: 1
|
|
offset: 42
|
|
- save_link:
|
|
type: bool
|
|
size: 1
|
|
offset: 41
|
|
- br_op:
|
|
match: '00'
|
|
offset: 39
|
|
size: 2
|
|
- br_type:
|
|
offset: 38
|
|
size: 1
|
|
- any_inst:
|
|
offset: 21
|
|
size: 1
|
|
- all_inst:
|
|
offset: 20
|
|
size: 1
|
|
- br_off:
|
|
size: 20
|
|
offset: 0
|
|
type: uint32_t
|
|
SMLSI:
|
|
description: SMLSI control instruction
|
|
members:
|
|
- op1: '11111'
|
|
- op2:
|
|
size: 3
|
|
offset: 56
|
|
match: '010'
|
|
- opcat:
|
|
match: '01'
|
|
size: 2
|
|
offset: 52
|
|
- nosched:
|
|
offset: 50
|
|
size: 1
|
|
- temp_limit:
|
|
offset: 44
|
|
size: 4
|
|
- pa_limit:
|
|
offset: 40
|
|
size: 4
|
|
- sa_limit:
|
|
offset: 36
|
|
size: 4
|
|
- dest_inc_mode:
|
|
offset: 35
|
|
size: 1
|
|
- src0_inc_mode:
|
|
offset: 34
|
|
size: 1
|
|
- src1_inc_mode:
|
|
offset: 33
|
|
size: 1
|
|
- src2_inc_mode:
|
|
offset: 32
|
|
size: 1
|
|
- dest_inc:
|
|
offset: 24
|
|
size: 8
|
|
- src0_inc:
|
|
offset: 16
|
|
size: 8
|
|
- src1_inc:
|
|
offset: 8
|
|
size: 8
|
|
- src2_inc:
|
|
offset: 0
|
|
size: 8
|
|
KILL:
|
|
description: Kill program
|
|
members:
|
|
- op1: '11111'
|
|
- op2:
|
|
size: 3
|
|
match: '001'
|
|
- DONTCARE:
|
|
size: 2
|
|
- opcat:
|
|
match: '11'
|
|
size: 2
|
|
- kill:
|
|
match: '000000000'
|
|
size: 9
|
|
- pred:
|
|
type: ShortPredicate
|
|
size: 2
|
|
- kill2:
|
|
match: '0000001101111'
|
|
size: 13
|
|
- DONTCARE:
|
|
size: 28
|
|
# EMIT:
|
|
# description: Emit Output
|
|
# members:
|
|
# - op1: '11111'
|
|
# - op2:
|
|
# size: 3
|
|
# offset: 56
|
|
# match: '011'
|
|
# - sideband_high:
|
|
# size: 2
|
|
# offset: 54
|
|
# - opcat:
|
|
# size: 2
|
|
# offset: 52
|
|
# match: '10'
|
|
# - src0_bank_ext:
|
|
# size: 1
|
|
# offset: 51
|
|
# - end:
|
|
# size: 1
|
|
# offset: 50
|
|
# - src1_bank_ext:
|
|
# size: 1
|
|
# offset: 49
|
|
# - src2_bank_ext:
|
|
# size: 1
|
|
# offset: 48
|
|
# - target:
|
|
# size: 2
|
|
# offset: 46
|
|
# - task_start_or_mte_hi:
|
|
# size: 1
|
|
# offset: 45
|
|
# - task_end_or_mte_lo:
|
|
# size: 1
|
|
# offset: 44
|
|
# - nosched:
|
|
# size: 1
|
|
# offset: 43
|
|
# - sideband_mid:
|
|
# size: 6
|
|
# offset: 35
|
|
# - src0_bank:
|
|
# size: 1
|
|
# offset: 34
|
|
# - incp:
|
|
# size: 2
|
|
# offset: 32
|
|
# - src1_bank:
|
|
# size: 2
|
|
# offset: 30
|
|
# - src2_bank:
|
|
# size: 2
|
|
# offset: 28
|
|
# - sideband_low:
|
|
# size: 6
|
|
# offset: 22
|
|
# - freep:
|
|
# size: 1
|
|
# offset: 21
|
|
# - src0_n:
|
|
# size: 7
|
|
# offset: 14
|
|
# - src1_n:
|
|
# size: 7
|
|
# offset: 7
|
|
# - src2_n:
|
|
# size: 7
|
|
# offset: 0
|
|
LIMM:
|
|
description: Load immediate value
|
|
members:
|
|
- op1: '11111'
|
|
- op2:
|
|
match: '100'
|
|
size: 3
|
|
offset: 56
|
|
- skipinv:
|
|
size: 1
|
|
offset: 55
|
|
type: bool
|
|
- nosched:
|
|
size: 1
|
|
offset: 54
|
|
type: bool
|
|
- opcat:
|
|
match: '10'
|
|
size: 2
|
|
offset: 52
|
|
- dest_bank_ext:
|
|
size: 1
|
|
offset: 51
|
|
type: bool
|
|
- end:
|
|
size: 1
|
|
offset: 50
|
|
type: bool
|
|
- imm_value_bits26to31:
|
|
offset: 44
|
|
size: 6
|
|
- pred:
|
|
type: ExtPredicate
|
|
size: 3
|
|
offset: 41
|
|
- imm_value_bits21to25:
|
|
size: 5
|
|
offset: 36
|
|
- dest_bank:
|
|
size: 2
|
|
offset: 32
|
|
- dest_num:
|
|
size: 7
|
|
offset: 21
|
|
- imm_value_first_21bits:
|
|
size: 21
|
|
offset: 0
|
|
|
|
SPEC:
|
|
description: Special
|
|
members:
|
|
- op1: '11111'
|
|
- special:
|
|
size: 1
|
|
offset: 54
|
|
type: bool
|
|
- category:
|
|
size: 2
|
|
type: SpecialCategory
|
|
# 11101 11110
|
|
VLDST:
|
|
description: Load and Store
|
|
members:
|
|
- op1_cnst: '111'
|
|
- op1:
|
|
size: 2
|
|
offset: 59
|
|
- pred:
|
|
size: 3
|
|
offset: 56
|
|
type: ExtPredicate
|
|
- skipinv:
|
|
size: 1
|
|
offset: 55
|
|
- nosched:
|
|
size: 1
|
|
offset: 54
|
|
- moe_expand:
|
|
size: 1
|
|
offest: 53
|
|
- sync_start:
|
|
size: 1
|
|
offset: 52
|
|
- cache_ext:
|
|
size: 1
|
|
offset: 51
|
|
- src0_bank_ext:
|
|
size: 1
|
|
offset: 50
|
|
- src1_bank_ext:
|
|
size: 1
|
|
offset: 49
|
|
- src2_bank_ext:
|
|
size: 1
|
|
offset: 48
|
|
- mask_count:
|
|
size: 4
|
|
offset: 44
|
|
- addr_mode:
|
|
size: 2
|
|
offset: 42
|
|
- mode:
|
|
size: 2
|
|
offset: 40
|
|
- dest_bank_primattr:
|
|
size: 1
|
|
offset: 39
|
|
- range_enable:
|
|
size: 1
|
|
offset: 38
|
|
- data_type:
|
|
size: 2
|
|
offset: 36
|
|
- increment_or_decrement:
|
|
size: 1
|
|
offset: 35
|
|
- src0_bank:
|
|
size: 1
|
|
offset: 34
|
|
- cache_by_pass12:
|
|
size: 1
|
|
offset: 33
|
|
- drc_sel:
|
|
size: 1
|
|
offset: 32
|
|
- src1_bank:
|
|
size: 2
|
|
offset: 30
|
|
- src2_bank:
|
|
size: 2
|
|
offset: 28
|
|
- dest_n:
|
|
size: 7
|
|
offset: 21
|
|
- src0_n:
|
|
size: 7
|
|
offset: 14
|
|
- src1_n:
|
|
size: 7
|
|
offset: 7
|
|
- src2_n:
|
|
size: 7
|
|
offset: 0 |