Emulation/Vita3K
1
0
Fork 0
mirror of https://github.com/Vita3K/Vita3K.git synced 2025-04-02 11:02:10 -04:00
Code Issues Projects Releases Packages Wiki Activity
3748 commits 2 branches 1 tag 107 MiB
Commit graph

338 commits

Author SHA1 Message Date
mangren
ae25063e0e shader/translator: Use all 4 components when do ALU dot 2021-01-16 20:02:47 +01:00
pent0
9e5b977bc4
Merge pull request #1081 from pent0/vtt 
shader: Fix typos and implement high/low modifier for IMAD32
 2021-01-08 21:51:26 +07:00
mangren
f6f20a3775 shader: Correct constant lookup 
fix regressions and also clear out how it works
 2021-01-08 20:40:40 +07:00
mangren
9ad5c13012 shader: Rotate VDP write mask instead giving current repeat 
Well because disasm is wrong lol and no easy way to fix
 2021-01-08 20:40:29 +07:00
mangren
5b922469c1 shader: Correct repeat offset behaviour on GPI sources 
- Don't ignore INTERNAL repeat mode on GPI sources
- Otherwise GPI source does not get affected by repeat offset
 2021-01-08 20:32:09 +07:00
mangren
5024698b1d shader: Add repeat multiplier and edge cases of its for VMOV and VPCK 2021-01-07 00:22:09 +07:00
mangren
131410df11 shader/translator: Pack u16/u8/s6/s8 without data modification 
Since if we pack it as u16 and unpack it as s16 we probably doom. This try to avoid data modification by using bitfieldExtract/bitfieldInsert. Sign extension code is from kd-11.
 2021-01-06 16:37:11 +07:00
mangren
5cfb30387c shader/analyzer: Add I32MAD predicates 2021-01-06 16:37:10 +07:00
mangren
2b366fa857 shader/translator: Multiply by data type size on conditions 2021-01-06 10:48:35 +07:00
mangren
b736a0f939 shader/utilities: Fix typo 2021-01-06 10:48:34 +07:00
mangren
b7ed371886 shader/ialu: Make use of high imms 2021-01-06 10:48:23 +07:00
Zangetsu38
ecb71d851d shader: Add Opcode ISUB16/ISUBU16. 2021-01-02 14:42:09 +01:00
mangren
e6b81cd008 shader/data: Fix typo 2021-01-02 00:14:00 +07:00
Zangetsu38
57a7043889 shader: add sb_mode 0 in smp 2020-12-28 10:38:13 +01:00
sunho
27d956cb64 shader: convert position in screen space 
When viewport is disabled, vertex position is in screen space.
 2020-11-25 17:31:42 +09:00
Sunho Kim
4f9574bc8b shader: style nits 
Co-authored-by: scribam <scribam@users.noreply.github.com>
 2020-11-25 17:31:15 +09:00
sunho
4dee9931ac shader: correct the unit of src1 in ldr 2020-11-25 17:31:15 +09:00
sunho
8e7155652b shader: add uniform buffer input null check 2020-11-25 17:31:15 +09:00
sunho
9de0de422a shader: fix vbw repeat offset 2020-11-25 17:31:15 +09:00
sunho
a72267e87f shader: add shader name comment in glsl file 2020-11-25 17:31:15 +09:00
sunho
598d0a8fd0 shader: add disasm log of ldr 2020-11-25 17:31:15 +09:00
sunho
6b252b50f3 shader: remove duplicate logs 2020-11-25 17:31:15 +09:00
sunho
a422c983e9 shader: fix immediate logging 
This is not hex value.
 2020-11-25 17:31:15 +09:00
sunho
76143d8d5a shader: implement repeat mode 2020-11-24 12:25:42 +09:00
sunho
0f6f5088ca shader: fix swizzle disasm when repeat_offset % 4 != 0 
We already shifted register by adding to register number in operand_to_str. So, we shouldn't shift it again in swizzle_to_str.
 2020-11-24 12:25:42 +09:00
sunho
d6450b80d1 shader: consider negative reg shift in disasm 2020-11-24 12:25:42 +09:00
sunho
3c83322e1c shader: add repeat mode enum 2020-11-24 12:25:42 +09:00
sunho
86e41136b1 shader: remove duplicated paramters logs 2020-11-18 17:14:38 +09:00
scribam
e9ac039fe4 msvc: fix some compiler warnings 2020-11-15 21:46:13 +01:00
sunho
1149e099bd shader: implement sb_mode in smp 2020-11-10 02:23:09 +09:00
sunho
bb090c8f7c shader: remove small hack 2020-10-29 12:06:45 +09:00
sunho
073890c3dd shader: use memory address in bytes 2020-10-29 12:06:45 +09:00
sunho
1e0be033d0 shader: more cleverly stub i32mad2 2020-10-29 12:06:45 +09:00
sunho
d598174276 shader: basic i32mad implementation 2020-10-29 12:06:45 +09:00
sunho
ebd26498d6 shader: add i32mad decoder 2020-10-29 12:06:45 +09:00
sunho
54e051e23a shader: increase output register count 2020-10-25 05:44:36 +09:00
sunho
444adb34f0 shader: memory load instruction with actual base and float scalar array 2020-10-25 05:44:36 +09:00
sunho
bc9b33d99f shader: don't use saturated conversion 2020-10-25 05:44:11 +09:00
sunho
5ae95664da shader: enable early testing for programmable blending 
The depth test is not in action if we use image_store to write to framebuffer. Early z testing would throw away pixel so that imagestore is not called.
 2020-09-08 19:19:50 +09:00
sunho
f6332894a5 shader: consider multiple dependent sampler parameters for one sampler 2020-09-08 19:19:40 +09:00
sunho
4a0a5391fa shader: fix non-zero reg start ub 2020-09-06 23:15:47 +09:00
sunho
425555fb76 shader: stub ldr 2020-09-06 23:15:47 +09:00
sunho
8f2dd87785 shader: determine uniform buffer size of stripped gxp 2020-09-06 23:15:47 +09:00
sunho
f92f9711dd shader: revert SA register maximum num 
The glsl error was from half register half memory uniform buffer. We can now safely use sane value 32.
 2020-09-06 23:15:47 +09:00
sunho
6b0a118d1e shader: rework uniform buffers 
We used to analyze the program to determine the size of memory uniform buffer. However, this method will require tons of works when dealing with ldr with temporary register for base field. (this can happen)

From my observation, uniform parameters of memory uniform buffer are not stripped away. Utilizing this, I tried to determine uniform buffer size from uniform paramters. I also observed half register half memory uniform buffer. (this seems to happen in large default uniform buffer) In this case the size_in_f32 is less than the total size of uniform buffer, and the ldr instruction will be used to access fields not available in register. Also, the base of ldr instruction should start from the end of "register block " of uniform buffer. I updated recompiler to consider this information.
 2020-09-06 23:15:47 +09:00
sunho
8772766ec6 shader: clamp float when converting to int 2020-09-05 20:56:40 +09:00
sunho
4c30aedc53 shader: fix mistake 2020-09-04 21:04:35 +09:00
sunho
d8268b424b shader: fix bugs in loading and storing of vertex output with non-four components 
First bug: When the component size is not 4, the vertext shader will create out variable with the actual size (that is not 4), but fragment shader always uses 4 for input variable size.
Second bug: Wen the copmponent size is 1, fragment shader will load the variable as vector with size 4. (since it's not finalized) However, util::store uses the spirv function to get components to write (it doesn't utilize dest_mask for determining size)

With these bugs fixed, we can safely remove the assert(number_of_comp_vec != 1) that we had for a long time.
 2020-09-04 17:37:12 +09:00
sunho
d6a8597052 shader: correct the order and size of vertext ouputs 2020-09-04 17:37:12 +09:00
sunho
620a9d3463 shader: fix vpck with f32 source 
It turned out source 2 is used when swizzle refer to "z" or "w"
 2020-09-04 15:26:08 +09:00