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Initialize PCI config space of all devices

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Based on a DVT4 dump using an official 5558 debug ROM as seen in http://xboxdevwiki.net/PCI
This commit is contained in:
StrikerX3 2018-12-30 14:49:18 -02:00
parent 71d18c70a0
commit c5f0363c61
15 changed files with 257 additions and 24 deletions
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16
src/core/vixen/hw/bus/smbus.cpp
View file

@ -31,7 +31,7 @@
namespace vixen {
SMBus::SMBus(IRQ *irq)
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01B4, 0xD1,
: PCIDevice(PCI_HEADER_TYPE_MULTIFUNCTION, PCI_VENDOR_ID_NVIDIA, 0x01B4, 0xB1,
0x0c, 0x05, 0x00) // SMBus
, m_irq(irq)
{
@ -42,8 +42,22 @@ SMBus::~SMBus() {
}
void SMBus::Init() {
RegisterBAR(0, 0x10, PCI_BAR_TYPE_IO); // 0x0 - 0xF (never used)
RegisterBAR(1, 0x10, PCI_BAR_TYPE_IO); // 0xC000 - 0xC00F
RegisterBAR(2, 0x20, PCI_BAR_TYPE_IO); // 0xC200 - 0xC21F
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x44);
Write8(m_configSpace, PCI_MIN_GNT, 0x03);
Write8(m_configSpace, PCI_MAX_LAT, 0x01);
// Capability list
Write8(m_configSpace, 0x44, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x45, 0x00);
// Unknown registers
Write16(m_configSpace, 0x46, 0x2);
}
void SMBus::Reset() {

18
src/core/vixen/hw/pci/ac97.cpp
View file

@ -4,8 +4,8 @@
namespace vixen {
AC97Device::AC97Device()
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01B1, 0xD2,
0x0f, 0x02, 0x00) // Audio controller
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01B1, 0xB1,
0x04, 0x01, 0x00) // Multimedia Audio Controller
{
}
@ -18,6 +18,20 @@ void AC97Device::Init() {
RegisterBAR(0, 0x100, PCI_BAR_TYPE_IO); // 0xD000 - 0xD0FF
RegisterBAR(1, 0x80, PCI_BAR_TYPE_IO); // 0xD200 - 0xD27F
RegisterBAR(2, 0x1000, PCI_BAR_TYPE_MEMORY); // 0xFEC00000 - 0xFEC00FFF
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x44);
Write8(m_configSpace, PCI_MIN_GNT, 0x02);
Write8(m_configSpace, PCI_MAX_LAT, 0x05);
// Capability list
Write8(m_configSpace, 0x44, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x45, 0x00);
// Unknown registers
Write16(m_configSpace, 0x46, 0x2);
Write16(m_configSpace, 0x4c, 0x106);
}
void AC97Device::Reset() {

28
src/core/vixen/hw/pci/agpbridge.cpp
View file

@ -17,6 +17,34 @@ void AGPBridgeDevice::Init() {
Write16(m_configSpace, PCI_PREF_MEMORY_BASE, PCI_PREF_RANGE_TYPE_32);
Write16(m_configSpace, PCI_PREF_MEMORY_LIMIT, PCI_PREF_RANGE_TYPE_32);
PCIBridgeDevice::Init();
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
Write16(m_configSpace, PCI_SEC_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
Write8(m_configSpace, PCI_MIN_GNT, 0x80);
Write8(m_configSpace, PCI_MAX_LAT, 0x00);
Write8(m_configSpace, PCI_IO_BASE, 0xf0);
Write8(m_configSpace, PCI_IO_LIMIT, 0x0);
Write16(m_configSpace, PCI_MEMORY_BASE, 0xfd00);
Write16(m_configSpace, PCI_MEMORY_LIMIT, 0xfe70);
Write16(m_configSpace, PCI_PREF_MEMORY_BASE, 0xf000);
Write16(m_configSpace, PCI_PREF_MEMORY_LIMIT, 0xf3f0);
Write32(m_configSpace, PCI_PREF_BASE_UPPER32, 0xff3fbfff);
Write32(m_configSpace, PCI_PREF_LIMIT_UPPER32, 0xafff7fff);
Write16(m_configSpace, PCI_IO_BASE_UPPER16, 0xf5fd);
Write16(m_configSpace, PCI_IO_LIMIT_UPPER16, 0x3eff);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x0);
// Unknown registers
Write16(m_configSpace, 0x44, 0x0);
Write16(m_configSpace, 0x46, 0x8000);
Write16(m_configSpace, 0x48, 0x14);
Write16(m_configSpace, 0x4c, 0x1);
Write16(m_configSpace, 0x50, 0x0);
Write32(m_configSpace, 0x54, 0x10000000);
for (uint8_t i = 0; i < 0x100 - 0x58; i += 4) {
Write32(m_configSpace, 0x58 + i, 0xffffffff);
}
}
}

14
src/core/vixen/hw/pci/bmide.cpp
View file

@ -34,6 +34,20 @@ BMIDEDevice::~BMIDEDevice() {
void BMIDEDevice::Init() {
RegisterBAR(4, 16, PCI_BAR_TYPE_IO); // 0xFF60 - 0xFF6F
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x44);
Write8(m_configSpace, PCI_MIN_GNT, 0x03);
Write8(m_configSpace, PCI_MAX_LAT, 0x01);
// Capability list
Write8(m_configSpace, 0x44, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x45, 0x00);
// Unknown registers
Write16(m_configSpace, 0x46, 0x2);
Write32(m_configSpace, 0x5c, 0xffff00ff);
}
void BMIDEDevice::Reset() {

48
src/core/vixen/hw/pci/hostbridge.cpp
View file

@ -4,12 +4,10 @@
namespace vixen {
HostBridgeDevice::HostBridgeDevice()
: PCIDevice(PCI_HEADER_TYPE_BRIDGE, PCI_VENDOR_ID_NVIDIA, 0x02A5, 0xA1,
: PCIDevice(PCI_HEADER_TYPE_MULTIFUNCTION, PCI_VENDOR_ID_NVIDIA, 0x02A5, 0xA1,
0x06, 0x00, 0x00, // Host bridge
/*TODO: subsystemVendorID*/0x00, /*TODO: subsystemID*/0x00)
{
Write8(m_configSpace, PCI_INTERRUPT_PIN, 0x1);
Write8(m_configSpace, 0x87, 3);
}
HostBridgeDevice::~HostBridgeDevice() {
@ -18,7 +16,49 @@ HostBridgeDevice::~HostBridgeDevice() {
// PCI Device functions
void HostBridgeDevice::Init() {
//RegisterBAR(0, 1024 * 1024 * 1024, PCI_BAR_TYPE_MEMORY); // 0x40000000 - 0x7FFFFFFF
RegisterBAR(0, 1024 * 1024 * 1024, PCI_BAR_TYPE_MEMORY); // 0x40000000 - 0x7FFFFFFF
Write32(m_configSpace, PCI_BASE_ADDRESS_0, 0x40000008);
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x40);
// Capability list
Write8(m_configSpace, 0x40, PCI_CAP_ID_AGP);
Write8(m_configSpace, 0x41, 0x60);
Write8(m_configSpace, 0x60, PCI_CAP_ID_HT);
Write8(m_configSpace, 0x61, 0x00);
// Unknown registers
Write16(m_configSpace, 0x42, 0x20);
Write32(m_configSpace, 0x44, 0x1f000217);
Write8(m_configSpace, 0x4c, 0x1);
Write8(m_configSpace, 0x57, 0x10);
Write32(m_configSpace, 0x58, 0xffffffff);
Write32(m_configSpace, 0x5c, 0xffffffff);
Write32(m_configSpace, 0x60, 0x20010008);
Write32(m_configSpace, 0x64, 0x88880120);
Write32(m_configSpace, 0x68, 0x10);
Write32(m_configSpace, 0x6c, 0x0f0f0f21);
Write32(m_configSpace, 0x70, 0xffffffff);
Write32(m_configSpace, 0x74, 0xffffffff);
Write32(m_configSpace, 0x78, 0xffffffff);
Write32(m_configSpace, 0x7c, 0xffffffff);
Write32(m_configSpace, 0x87, 3);
Write32(m_configSpace, 0x88, 0x1);
Write32(m_configSpace, 0x8c, 0x3ff6f417);
Write32(m_configSpace, 0x94, 0xf9feffff);
Write32(m_configSpace, 0xa4, 0x2001);
Write32(m_configSpace, 0xb0, 0x1);
Write32(m_configSpace, 0xc0, 0x33333);
Write32(m_configSpace, 0xc4, 0x33333);
Write32(m_configSpace, 0xc8, 0x13);
Write32(m_configSpace, 0xd4, 0x1);
Write32(m_configSpace, 0xd8, 0x7f0ffff);
Write32(m_configSpace, 0xe0, 0x400006);
Write32(m_configSpace, 0xe4, 0x1ff75b7);
Write32(m_configSpace, 0xf0, 0xf0000001);
}
void HostBridgeDevice::Reset() {

34
src/core/vixen/hw/pci/lpc.cpp
View file

@ -29,7 +29,7 @@
namespace vixen {
LPCDevice::LPCDevice(IRQ *irqs, uint8_t *rom, uint8_t *bios, uint32_t biosSize, uint8_t *mcpxROM, bool initMcpxROM)
: PCIDevice(PCI_HEADER_TYPE_BRIDGE, PCI_VENDOR_ID_NVIDIA, 0x01B2, 0xD4,
: PCIDevice(PCI_HEADER_TYPE_MULTIFUNCTION, PCI_VENDOR_ID_NVIDIA, 0x01B2, 0xB2,
0x06, 0x01, 0x00, // ISA bridge
/*TODO: subsystemVendorID*/0x00, /*TODO: subsystemID*/0x00)
, m_irqs(irqs)
@ -62,6 +62,38 @@ void LPCDevice::HandleIRQ(uint8_t irqNum, bool level) {
void LPCDevice::Init() {
RegisterBAR(0, 0x100, PCI_BAR_TYPE_IO); // 0x8000 - 0x80FF
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x50);
Write8(m_configSpace, PCI_MIN_GNT, 0x03);
Write8(m_configSpace, PCI_MAX_LAT, 0x01);
// Capability list
Write8(m_configSpace, 0x50, PCI_CAP_ID_HT);
Write8(m_configSpace, 0x51, 0x00);
// Unknown registers
Write32(m_configSpace, 0x44, 0x20000000);
Write32(m_configSpace, 0x48, 0x440);
Write16(m_configSpace, 0x52, 0x141);
Write32(m_configSpace, 0x54, 0x88880070);
Write32(m_configSpace, 0x58, 0xa0);
Write16(m_configSpace, 0x68, 0x1000);
Write32(m_configSpace, 0x80, 0x4001000);
Write32(m_configSpace, 0x88, 0xf);
Write32(m_configSpace, 0x90, 0x80);
Write32(m_configSpace, 0x98, 0x811ced04);
Write32(m_configSpace, 0xa4, 0x1500044);
Write32(m_configSpace, 0xa8, 0x150004);
Write32(m_configSpace, 0xac, 0x70001);
Write32(m_configSpace, 0xb0, 0x2010000);
Write32(m_configSpace, 0xb4, 0x10012);
Write32(m_configSpace, 0xbc, 0x1008001);
Write32(m_configSpace, 0xd0, 0x607f7e7c);
Write32(m_configSpace, 0xd4, 0x7c7e7c78);
Write32(m_configSpace, 0xd8, 0x7e7f);
Write32(m_configSpace, 0xf0, 0xf00);
Reset();
}

8
src/core/vixen/hw/pci/mcpx_ram.cpp
View file

@ -4,7 +4,7 @@
namespace vixen {
MCPXRAMDevice::MCPXRAMDevice(MCPXRevision revision)
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x02A6, 0xA1,
: PCIDevice(PCI_HEADER_TYPE_MULTIFUNCTION, PCI_VENDOR_ID_NVIDIA, 0x02A6, 0xA1,
0x05, 0x00, 0x00) // RAM controller
{
m_revision = revision;
@ -16,6 +16,12 @@ MCPXRAMDevice::~MCPXRAMDevice() {
// PCI Device functions
void MCPXRAMDevice::Init() {
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_66MHZ);
// Unknown registers
Write32(m_configSpace, 0x64, 0x1208001);
Write32(m_configSpace, 0x68, 0x6c);
}
void MCPXRAMDevice::Reset() {

32
src/core/vixen/hw/pci/nv2a.cpp
View file

@ -82,12 +82,34 @@ NV2ADevice::~NV2ADevice() {
// PCI Device functions
void NV2ADevice::Init() {
RegisterBAR(0, 16 * 1024 * 1024, PCI_BAR_TYPE_MEMORY); // 0xFD000000 - 0xFDFFFFFF
RegisterBAR(1, 128 * 1024 * 1024, PCI_BAR_TYPE_MEMORY); // 0xF0000000 - 0xF7FFFFFF
// TODO: check if this is correct
RegisterBAR(2, 64 * 1024 * 1024, PCI_BAR_TYPE_MEMORY); // 0xF8000000 - 0xFBFFFFFF
RegisterBAR(0, 0x1000000, PCI_BAR_TYPE_MEMORY); // 0xFD000000 - 0xFDFFFFFF
RegisterBAR(1, 0x8000000, PCI_BAR_TYPE_MEMORY | PCI_BAR_MEMORY_PREFETCHABLE); // 0xF0000000 - 0xF7FFFFFF
RegisterBAR(2, 0x80000, PCI_BAR_TYPE_MEMORY | PCI_BAR_MEMORY_PREFETCHABLE); // 0x0 - 0x7FFFF
Write8(m_configSpace, PCI_INTERRUPT_PIN, 1);
Write8(m_configSpace, PCI_LATENCY_TIMER, 0xf8);
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_MEDIUM);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x60);
Write8(m_configSpace, PCI_MIN_GNT, 0x05);
Write8(m_configSpace, PCI_MAX_LAT, 0x01);
// Capability list
Write8(m_configSpace, 0x60, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x61, 0x44);
Write8(m_configSpace, 0x44, PCI_CAP_ID_AGP);
Write8(m_configSpace, 0x45, 0x00);
// Unknown registers
Write16(m_configSpace, 0x46, 0x20);
Write32(m_configSpace, 0x48, 0x1f000017);
Write16(m_configSpace, 0x4c, 0x1f00);
Write32(m_configSpace, 0x54, 0x1);
Write32(m_configSpace, 0x58, 0x23d6ce);
Write32(m_configSpace, 0x5c, 0xf);
Write32(m_configSpace, 0x60, 0x24401);
Write32(m_configSpace, 0x80, 0x2b16d065);
Reset();

21
src/core/vixen/hw/pci/nvapu.cpp
View file

@ -53,8 +53,8 @@ uint32_t GetAPUTime() {
// TODO: Audio Processing/Thread
NVAPUDevice::NVAPUDevice()
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01B0, 0xD2,
0x0f, 0x02, 0x00) // Audio controller
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01B0, 0xB1,
0x04, 0x01, 0x00) // Multimedia Audio Controller
{
}
@ -65,6 +65,23 @@ NVAPUDevice::~NVAPUDevice() {
void NVAPUDevice::Init() {
RegisterBAR(0, 0x80000, PCI_BAR_TYPE_MEMORY); // 0xFE800000 - 0xFE87FFFF
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x44);
Write8(m_configSpace, PCI_MIN_GNT, 0x01);
Write8(m_configSpace, PCI_MAX_LAT, 0x0c);
// Capability list
Write8(m_configSpace, 0x44, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x45, 0x00);
// Unknown registers
Write16(m_configSpace, 0x46, 0x2);
Write32(m_configSpace, 0x4c, 0x50a);
for (uint8_t i = 0; i < 0x100 - 0x50; i += 4) {
Write32(m_configSpace, 0x50 + i, 0x20001);
}
}
void NVAPUDevice::Reset() {

18
src/core/vixen/hw/pci/nvnet.cpp
View file

@ -478,7 +478,7 @@ void EmuNVNet_Write(uint32_t addr, uint32_t value, int size) {
/* NVNetDevice */
NVNetDevice::NVNetDevice()
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01C3, 0xD2,
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01C3, 0xB1,
0x02, 0x00, 0x00) // Ethernet controller
{
}
@ -490,7 +490,21 @@ NVNetDevice::~NVNetDevice() {
void NVNetDevice::Init() {
RegisterBAR(0, NVNET_SIZE, PCI_BAR_TYPE_MEMORY); // 0xFEF00000 - 0xFEF003FF
RegisterBAR(1, 8, PCI_BAR_TYPE_IO); // 0xE000 - 0xE007
RegisterBAR(1, 16, PCI_BAR_TYPE_IO); // 0xE000 - 0xE00F
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x44);
Write8(m_configSpace, PCI_MIN_GNT, 0x01);
Write8(m_configSpace, PCI_MAX_LAT, 0x14);
// Capability list
Write8(m_configSpace, 0x44, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x45, 0x00);
// Unknown registers
Write16(m_configSpace, 0x46, 0xfe02);
Write32(m_configSpace, 0x4c, 0x4);
}
void NVNetDevice::Reset() {

9
src/core/vixen/hw/pci/pci.cpp
View file

@ -134,7 +134,8 @@ bool PCIDevice::GetIOBar(uint32_t port, uint8_t* barIndex, uint32_t *baseAddress
uint8_t numBARs;
switch (headerType) {
case PCI_HEADER_TYPE_NORMAL: {
case PCI_HEADER_TYPE_NORMAL:
case PCI_HEADER_TYPE_MULTIFUNCTION: {
numBARs = PCI_NUM_BARS_DEVICE;
break;
}
@ -176,7 +177,8 @@ bool PCIDevice::GetMMIOBar(uint32_t addr, uint8_t* barIndex, uint32_t *baseAddre
uint8_t numBARs;
switch (headerType) {
case PCI_HEADER_TYPE_NORMAL: {
case PCI_HEADER_TYPE_NORMAL:
case PCI_HEADER_TYPE_MULTIFUNCTION: {
numBARs = PCI_NUM_BARS_DEVICE;
break;
}
@ -218,7 +220,8 @@ bool PCIDevice::RegisterBAR(int index, uint32_t size, uint32_t type) {
uint8_t numBARs;
switch (headerType) {
case PCI_HEADER_TYPE_NORMAL: {
case PCI_HEADER_TYPE_NORMAL:
case PCI_HEADER_TYPE_MULTIFUNCTION: {
numBARs = PCI_NUM_BARS_DEVICE;
break;
}

2
src/core/vixen/hw/pci/pci.h
View file

@ -13,6 +13,8 @@ namespace vixen {
#define PCI_BAR_TYPE_IO 1
#define PCI_BAR_TYPE_MEMORY 0
#define PCI_BAR_MEMORY_PREFETCHABLE (1 << 3)
#define PCI_NUM_BARS_DEVICE 6
#define PCI_NUM_BARS_PCI_BRIDGE 2

1
src/core/vixen/hw/pci/pci_regs.h
View file

@ -67,6 +67,7 @@
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_HEADER_TYPE_MULTIFUNCTION 0x80
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */

16
src/core/vixen/hw/pci/pcibridge.cpp
View file

@ -39,7 +39,7 @@
namespace vixen {
PCIBridgeDevice::PCIBridgeDevice()
: PCIBridgeDevice(PCI_VENDOR_ID_NVIDIA, 0x01B8, 0xD2)
: PCIBridgeDevice(PCI_VENDOR_ID_NVIDIA, 0x01B8, 0xB1)
{
}
@ -58,8 +58,20 @@ PCIBridgeDevice::~PCIBridgeDevice() {
// PCI Device functions
void PCIBridgeDevice::Init() {
// Initialize configuration space
TestAndSet16(m_configSpace, PCI_STATUS, PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
Write16(m_configSpace, PCI_SEC_STATUS, PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
Write16(m_configSpace, PCI_SEC_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x44);
// Capabilities list
Write8(m_configSpace, 0x44, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x45, 0x0);
// Unknown registers
Write16(m_configSpace, 0x46, 0x2);
Write16(m_configSpace, 0x4c, 0xb08);
Write16(m_configSpace, 0x50, 0xd0c);
Write16(m_configSpace, 0x54, 0xf0e);
m_secBus->m_owner = this;
m_secBus->m_irqMapper = GetIRQMapper();

16
src/core/vixen/hw/pci/usb_pci.cpp
View file

@ -58,7 +58,7 @@ using namespace vixen::cpu;
#define SETUP_STATE_PARAM 4
USBPCIDevice::USBPCIDevice(uint8_t irqn, Cpu& cpu)
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x02A5, 0xA1,
: PCIDevice(PCI_HEADER_TYPE_NORMAL, PCI_VENDOR_ID_NVIDIA, 0x01C2, 0xB1,
0x0c, 0x03, 0x10) // USB OHCI
, m_irqn(irqn)
, m_cpu(cpu)
@ -73,6 +73,20 @@ USBPCIDevice::~USBPCIDevice() {
void USBPCIDevice::Init() {
RegisterBAR(0, 0x1000, PCI_BAR_TYPE_MEMORY); // 0xFED00000 - 0xFED00FFF and 0xFED08000 - 0xFED08FFF
// Initialize configuration space
Write16(m_configSpace, PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_CAP_LIST);
Write8(m_configSpace, PCI_CAPABILITY_LIST, 0x44);
Write8(m_configSpace, PCI_MIN_GNT, 0x03);
Write8(m_configSpace, PCI_MAX_LAT, 0x01);
// Capability list
Write8(m_configSpace, 0x44, PCI_CAP_ID_PM);
Write8(m_configSpace, 0x45, 0x00);
// Unknown registers
Write16(m_configSpace, 0x46, 0xda02);
Write32(m_configSpace, 0x4c, 0x2);
if (m_irqn == 1) {
m_PciPath = "pci.0:02.0";
}