13 commits

Author	SHA1	Message	Date
Amish K. Naidu	9ef245fd09	fix(cpu): branch timing ... Closes #35	2025-01-04 17:57:54 +05:30
Amish K. Naidu	80d17ba00d	fix: improve interrupt timing	2022-08-21 20:39:36 +05:30
grimoire	9a73b46afe	add mappercontrolled mirroring, fix irq callback	2022-07-18 22:07:26 +08:00
Amish Naidu	6ad88354bb	Removed unnecessary redirection and small rename	2016-07-24 12:13:20 +05:30
Amish Naidu	ce46a97788	CHR-ROM read delayed by one byte and OAM basics	2016-07-23 13:38:23 +05:30
Amish Naidu	8ca7ed0fb3	SOME crap shows on screen (many things done) ... * CPU trace is logged independently * VBlank Interrupt firing * Branch offset is now signed * MANY small logic bugs fixed	2016-07-19 19:54:56 +05:30
Amish Naidu	8954926389	Compiles. "nestest.nes" path hardcoded for now.	2016-07-17 10:06:57 +05:30
Amish Naidu	018f1c44dc	Some work done (arguably)	2016-07-15 15:44:57 +05:30
Amish Naidu	21af8b990b	Renamed stuff	2016-07-09 19:18:27 +05:30
Amish Naidu	a5eadfea5a	About half of CPU thoroughly tested with a hacky interface ... Some lines commented and added for testing CPU	2016-06-10 16:53:51 +05:30
Amish Naidu	76229a68bd	CPU Interrupts done and rudimentary memory class ... CPU implemented completely (If I'm not missing anything) and added a rudimentary memory class.	2016-06-08 12:15:23 +05:30
Amish Naidu	315e9df2fe	Implemented all Opcodes in CPU	2016-06-07 12:58:01 +05:30
Amish Naidu	fb8d6736ac	Initial commit	2016-06-01 15:48:21 +05:30