SAROO/FPGA_old/SSMaster.sdc
2023-02-13 17:09:34 +08:00

10 lines
255 B
Tcl

#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks -create_base_clocks
#create_clock -name {CLOCK_50M} -period 20.000 [get_ports {CLK_50M}]