mirror of
https://github.com/BluestormDNA/ProjectPSX.git
synced 2025-04-02 10:52:34 -04:00
Renamed Instr <-> opcode as it made more sense
This commit is contained in:
Blue
parent
b4169d8c7e
commit
51fccd73a2
1 changed files with 120 additions and 120 deletions
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@ -34,8 +34,8 @@ namespace ProjectPSX {
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public uint WriteValue;
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}
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private struct Opcode {
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public uint instruction; //Opcode Instruction
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private struct Instr {
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public uint opcode; //Instr opcode
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public uint value; //debug
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//I-Type
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public uint rs; //Register Source
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@ -54,20 +54,20 @@ namespace ProjectPSX {
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public uint fs;
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public uint fd;
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public void Decode(uint opcode) {
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instruction = opcode >> 26;
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value = opcode;
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public void Decode(uint instr) {
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opcode = instr >> 26;
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value = instr;
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//I-Type
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rs = (opcode >> 21) & 0x1F;
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rt = (opcode >> 16) & 0x1F;
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imm = opcode & 0xFFFF;
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rs = (instr >> 21) & 0x1F;
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rt = (instr >> 16) & 0x1F;
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imm = instr & 0xFFFF;
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imm_s = (uint)(short)imm;
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//R-Type
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rd = (opcode >> 11) & 0x1F;
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sa = (opcode >> 6) & 0x1F;
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function = opcode & 0x3F;
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rd = (instr >> 11) & 0x1F;
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sa = (instr >> 6) & 0x1F;
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function = instr & 0x3F;
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//J-Type
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addr = opcode & 0x3FFFFFF;
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addr = instr & 0x3FFFFFF;
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//CoProcessor
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format = rs;
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ft = rt;
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@ -75,7 +75,7 @@ namespace ProjectPSX {
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fd = sa;
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}
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}
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private Opcode opcode;
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private Instr instr;
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private WB wb;
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private MEM mem;
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@ -104,7 +104,7 @@ namespace ProjectPSX {
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return;
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}
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opcode.Decode(load);
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instr.Decode(load);
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cycle++;
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}
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@ -123,9 +123,9 @@ namespace ProjectPSX {
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}
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private void Execute(MMU mmu) {
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switch (opcode.instruction) {
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case 0b00_0000: //R-Type Instructions
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switch (opcode.function) {
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switch (instr.opcode) {
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case 0b00_0000: //R-Type opcodes
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switch (instr.function) {
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case 0b00_0000: SLL(); break;
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case 0b00_0010: SRL(); break;
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case 0b00_0011: SRA(); break;
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@ -154,7 +154,7 @@ namespace ProjectPSX {
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}
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break;
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case 0b00_0001:
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switch (opcode.rt) {
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switch (instr.rt) {
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case 0b00_0000: BLTZ(); break;
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case 0b00_0001: BGEZ(); break;
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default: unimplementedWarning(); break;
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@ -175,8 +175,8 @@ namespace ProjectPSX {
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case 0b00_1101: ORI(); break;
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case 0b00_1111: LUI(); break;
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case 0b01_0000: //CoProcessor Instructions
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switch (opcode.format) {
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case 0b01_0000: //CoProcessor opcodes
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switch (instr.format) {
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case 0b0_0000: MFC0(); break;
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case 0b0_0100: MTC0(); break;
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case 0b1_0000: RFE(); break;
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@ -200,33 +200,33 @@ namespace ProjectPSX {
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}
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private void MULTU() {
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ulong value = REG[opcode.rs] * REG[opcode.rt];
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ulong value = REG[instr.rs] * REG[instr.rt];
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HI = (uint)(value >> 32);
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LO = (uint)value;
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}
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private void SRLV() {
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setReg(opcode.rd, REG[opcode.rt] >> (int)(REG[opcode.rs] & 0x1F));
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setReg(instr.rd, REG[instr.rt] >> (int)(REG[instr.rs] & 0x1F));
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}
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private void SRAV() {
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setReg(opcode.rd, (uint)((int)REG[opcode.rt] >> (int)(REG[opcode.rs] & 0x1F)));
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setReg(instr.rd, (uint)((int)REG[instr.rt] >> (int)(REG[instr.rs] & 0x1F)));
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}
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private void NOR() {
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setReg(opcode.rd, ~(REG[opcode.rs] | REG[opcode.rt]));
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setReg(instr.rd, ~(REG[instr.rs] | REG[instr.rt]));
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}
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private void LH(MMU mmu) {
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if ((SR & 0x10000) == 0) {
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uint addr = REG[opcode.rs] + opcode.imm_s;
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uint addr = REG[instr.rs] + instr.imm_s;
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if ((addr % 2) != 0) {
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EXCEPTION(EX.LOAD_ADRESS_ERROR);
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} else {
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uint value = (uint)(short)mmu.read32(addr);
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mem.LoadRegN = opcode.rt;
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mem.LoadRegN = instr.rt;
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mem.LoadValue = value;
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}
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@ -234,18 +234,18 @@ namespace ProjectPSX {
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}
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private void SLLV() {
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setReg(opcode.rd, REG[opcode.rt] << (int)(REG[opcode.rs] & 0x1F));
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setReg(instr.rd, REG[instr.rt] << (int)(REG[instr.rs] & 0x1F));
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}
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private void LHU(MMU mmu) {
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if ((SR & 0x10000) == 0) {
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uint addr = REG[opcode.rs] + opcode.imm_s;
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uint addr = REG[instr.rs] + instr.imm_s;
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if ((addr % 2) != 0) {
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EXCEPTION(EX.LOAD_ADRESS_ERROR);
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} else {
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uint value = (ushort)mmu.read32(addr);
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mem.LoadRegN = opcode.rt;
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mem.LoadRegN = instr.rt;
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mem.LoadValue = value;
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}
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@ -259,11 +259,11 @@ namespace ProjectPSX {
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}
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private void MTHI() {
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HI = REG[opcode.rs];
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HI = REG[instr.rs];
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}
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private void MTLO() {
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LO = REG[opcode.rs];
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LO = REG[instr.rs];
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}
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private void EXCEPTION(uint cause) {
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@ -295,17 +295,17 @@ namespace ProjectPSX {
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}
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private void SLT() {
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bool condition = (int)REG[opcode.rs] < (int)REG[opcode.rt];
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setReg(opcode.rd, condition ? 1u : 0u);
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bool condition = (int)REG[instr.rs] < (int)REG[instr.rt];
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setReg(instr.rd, condition ? 1u : 0u);
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}
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private void MFHI() {
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setReg(opcode.rd, HI);
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setReg(instr.rd, HI);
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}
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private void DIVU() {
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uint n = REG[opcode.rs];
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uint d = REG[opcode.rt];
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uint n = REG[instr.rs];
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uint d = REG[instr.rt];
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if(d == 0) {
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HI = n;
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@ -317,21 +317,21 @@ namespace ProjectPSX {
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}
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private void SLTIU() {
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bool condition = REG[opcode.rs] < opcode.imm_s;
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setReg(opcode.rt, condition ? 1u : 0u);
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bool condition = REG[instr.rs] < instr.imm_s;
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setReg(instr.rt, condition ? 1u : 0u);
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}
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private void SRL() {
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setReg(opcode.rd, REG[opcode.rt] >> (int)opcode.sa);
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setReg(instr.rd, REG[instr.rt] >> (int)instr.sa);
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}
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private void MFLO() {
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setReg(opcode.rd, LO);
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setReg(instr.rd, LO);
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}
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private void DIV() { //signed division
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int n = (int)REG[opcode.rs];
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int d = (int)REG[opcode.rt];
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int n = (int)REG[instr.rs];
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int d = (int)REG[instr.rt];
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if(d == 0) {
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HI = (uint) n;
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@ -350,109 +350,109 @@ namespace ProjectPSX {
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}
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private void SRA() { //TODO revisit this
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setReg(opcode.rd, (uint)((int)REG[opcode.rt] >> (int)opcode.sa));
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setReg(instr.rd, (uint)((int)REG[instr.rt] >> (int)instr.sa));
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}
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private void SUBU() {
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setReg(opcode.rd, REG[opcode.rs] - REG[opcode.rt]);
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setReg(instr.rd, REG[instr.rs] - REG[instr.rt]);
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}
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private void SLTI() {
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bool condition = (int)REG[opcode.rs] < (int)opcode.imm_s;
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setReg(opcode.rt, condition ? 1u : 0u);
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bool condition = (int)REG[instr.rs] < (int)instr.imm_s;
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setReg(instr.rt, condition ? 1u : 0u);
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}
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private void BRANCH() {
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isBranch = true;
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PC_Predictor -= 4;
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PC_Predictor += opcode.imm_s << 2;
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PC_Predictor += instr.imm_s << 2;
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}
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private void BGEZ() {
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if (((int)REG[opcode.rs]) >= 0) {
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if (((int)REG[instr.rs]) >= 0) {
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BRANCH();
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}
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}
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private void BLTZ() {
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if (((int)REG[opcode.rs]) < 0) {
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if (((int)REG[instr.rs]) < 0) {
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BRANCH();
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}
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}
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private void JALR() {
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isBranch = true;
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setReg(opcode.rd, PC_Predictor);
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setReg(instr.rd, PC_Predictor);
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JR();
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}
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private void LBU(MMU mmu) { //todo recheck this
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if ((SR & 0x10000) == 0) {
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uint value = (byte)mmu.read32(REG[opcode.rs] + opcode.imm_s);
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mem.LoadRegN = opcode.rt;
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uint value = (byte)mmu.read32(REG[instr.rs] + instr.imm_s);
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mem.LoadRegN = instr.rt;
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mem.LoadValue = value;
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} //else Console.WriteLine("Ignoring Load");
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}
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private void BLEZ() {
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if (((int)REG[opcode.rs]) <= 0) {
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if (((int)REG[instr.rs]) <= 0) {
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BRANCH();
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}
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}
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private void BGTZ() {
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if (((int)REG[opcode.rs]) > 0) {
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if (((int)REG[instr.rs]) > 0) {
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BRANCH();
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}
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}
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private void ADD() {
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int rs = (int)REG[opcode.rs];
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int rt = (int)REG[opcode.rt];
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int rs = (int)REG[instr.rs];
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int rt = (int)REG[instr.rt];
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try {
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uint add = (uint)checked(rs + rt);
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setReg(opcode.rd, add);
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setReg(instr.rd, add);
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} catch (OverflowException) {
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EXCEPTION(EX.OVERFLOW);
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}
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}
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private void AND() {
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setReg(opcode.rd, REG[opcode.rs] & REG[opcode.rt]);
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setReg(instr.rd, REG[instr.rs] & REG[instr.rt]);
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}
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private void MFC0() {
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mem.LoadRegN = opcode.ft;
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mem.LoadValue = Cop0Reg[opcode.fs];
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mem.LoadRegN = instr.ft;
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mem.LoadValue = Cop0Reg[instr.fs];
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}
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private void BEQ() {
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if (REG[opcode.rs] == REG[opcode.rt]) {
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if (REG[instr.rs] == REG[instr.rt]) {
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BRANCH();
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}
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}
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private void LB(MMU mmu) { //todo redo this as it unnecesary read32
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if ((SR & 0x10000) == 0) {
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uint lb = (uint)((sbyte)(mmu.read32(REG[opcode.rs] + opcode.imm_s)));
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mem.LoadRegN = opcode.rt;
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uint lb = (uint)((sbyte)(mmu.read32(REG[instr.rs] + instr.imm_s)));
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mem.LoadRegN = instr.rt;
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mem.LoadValue = lb;
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} //else Console.WriteLine("Ignoring Write");
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}
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private void JR() {
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isBranch = true;
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PC_Predictor = REG[opcode.rs];
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PC_Predictor = REG[instr.rs];
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}
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private void SB(MMU mmu) {
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if ((SR & 0x10000) == 0)
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mmu.write8(REG[opcode.rs] + opcode.imm_s, (byte)REG[opcode.rt]);
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mmu.write8(REG[instr.rs] + instr.imm_s, (byte)REG[instr.rt]);
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//else Console.WriteLine("Ignoring Write");
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}
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private void ANDI() {
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setReg(opcode.rt, REG[opcode.rs] & opcode.imm);
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setReg(instr.rt, REG[instr.rs] & instr.imm);
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}
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private void JAL() {
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@ -462,35 +462,35 @@ namespace ProjectPSX {
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private void SH(MMU mmu) {
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if ((SR & 0x10000) == 0) {
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uint addr = REG[opcode.rs] + opcode.imm_s;
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uint addr = REG[instr.rs] + instr.imm_s;
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if ((addr % 2) != 0) {
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EXCEPTION(EX.STORE_ADRESS_ERROR);
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} else {
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mmu.write16(addr, (ushort)REG[opcode.rt]);
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mmu.write16(addr, (ushort)REG[instr.rt]);
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}
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}
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//else Console.WriteLine("Ignoring Write");
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}
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private void ADDU() {
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setReg(opcode.rd, REG[opcode.rs] + REG[opcode.rt]);
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setReg(instr.rd, REG[instr.rs] + REG[instr.rt]);
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}
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private void SLTU() {
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bool condition = REG[opcode.rs] < REG[opcode.rt];
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setReg(opcode.rd, condition ? 1u : 0u);
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bool condition = REG[instr.rs] < REG[instr.rt];
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setReg(instr.rd, condition ? 1u : 0u);
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}
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private void LW(MMU mmu) {
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if ((SR & 0x10000) == 0) {
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uint addr = REG[opcode.rs] + opcode.imm_s;
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uint addr = REG[instr.rs] + instr.imm_s;
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if ((addr % 4) != 0) {
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EXCEPTION(EX.LOAD_ADRESS_ERROR);
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} else {
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uint value = mmu.read32(addr);
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mem.LoadRegN = opcode.rt;
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mem.LoadRegN = instr.rt;
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mem.LoadValue = value;
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}
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@ -498,62 +498,62 @@ namespace ProjectPSX {
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}
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private void ADDI() {
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int rs = (int)REG[opcode.rs];
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int imm_s = (int)opcode.imm_s;
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int rs = (int)REG[instr.rs];
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int imm_s = (int)instr.imm_s;
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try {
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uint addi = (uint) checked(rs + imm_s);
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setReg(opcode.rt, addi);
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setReg(instr.rt, addi);
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} catch (OverflowException) {
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EXCEPTION(EX.OVERFLOW);
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}
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}
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private void BNE() {
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if (REG[opcode.rs] != REG[opcode.rt]) {
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if (REG[instr.rs] != REG[instr.rt]) {
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BRANCH();
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}
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}
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private void MTC0() {
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Cop0Reg[opcode.fs] = REG[opcode.ft];
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Cop0Reg[instr.fs] = REG[instr.ft];
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}
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private void OR() {
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setReg(opcode.rd, REG[opcode.rs] | REG[opcode.rt]);
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setReg(instr.rd, REG[instr.rs] | REG[instr.rt]);
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}
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private void J() {
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isBranch = true;
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PC_Predictor = (PC_Predictor & 0xF000_0000) | (opcode.addr << 2);
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PC_Predictor = (PC_Predictor & 0xF000_0000) | (instr.addr << 2);
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}
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private void ADDIU() {
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setReg(opcode.rt, REG[opcode.rs] + opcode.imm_s);
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setReg(instr.rt, REG[instr.rs] + instr.imm_s);
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}
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private void SLL() {
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setReg(opcode.rd, REG[opcode.rt] << (int)opcode.sa);
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setReg(instr.rd, REG[instr.rt] << (int)instr.sa);
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}
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private void SW(MMU mmu) {
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if ((SR & 0x10000) == 0) {
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uint addr = REG[opcode.rs] + opcode.imm_s;
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uint addr = REG[instr.rs] + instr.imm_s;
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if ((addr % 4) != 0) {
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EXCEPTION(EX.STORE_ADRESS_ERROR);
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} else {
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mmu.write32(addr, REG[opcode.rt]);
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mmu.write32(addr, REG[instr.rt]);
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}
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}
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//else Console.WriteLine("Ignoring Write");
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}
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private void LUI() {
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setReg(opcode.rt, opcode.imm << 16);
|
||||
setReg(instr.rt, instr.imm << 16);
|
||||
}
|
||||
|
||||
private void ORI() {
|
||||
setReg(opcode.rt, REG[opcode.rs] | opcode.imm);
|
||||
setReg(instr.rt, REG[instr.rs] | instr.imm);
|
||||
}
|
||||
|
||||
private void setReg(uint regN, uint value) {
|
||||
|
|
@ -562,11 +562,11 @@ namespace ProjectPSX {
|
|||
}
|
||||
|
||||
private void unimplementedWarning() {
|
||||
Console.WriteLine("Unimplemented OPCODE");
|
||||
string funct_string = opcode.instruction == 0 ? " Function: " + opcode.function.ToString("x8") : "";
|
||||
string format_string = opcode.instruction == 0b01_0000 ? " Function: " + opcode.format.ToString("x8") : "";
|
||||
Console.WriteLine("Cycle: " + cycle + " PC: " + PC_Now.ToString("x8") + " Load32: " + opcode.value.ToString("x8")
|
||||
+ " Instr: " + opcode.instruction.ToString("x8") + funct_string + format_string);
|
||||
Console.WriteLine("Unimplemented instr");
|
||||
string funct_string = instr.opcode == 0 ? " Function: " + instr.function.ToString("x8") : "";
|
||||
string format_string = instr.opcode == 0b01_0000 ? " Function: " + instr.format.ToString("x8") : "";
|
||||
Console.WriteLine("Cycle: " + cycle + " PC: " + PC_Now.ToString("x8") + " Load32: " + instr.value.ToString("x8")
|
||||
+ " Instr: " + instr.opcode.ToString("x8") + funct_string + format_string);
|
||||
disassemble();
|
||||
PrintRegs();
|
||||
throw new NotImplementedException();
|
||||
|
|
@ -580,16 +580,16 @@ namespace ProjectPSX {
|
|||
|
||||
private void disassemble() {
|
||||
string pc = PC_Now.ToString("x8");
|
||||
string load = opcode.value.ToString("x8");
|
||||
string load = instr.value.ToString("x8");
|
||||
string output = "";
|
||||
string values = "";
|
||||
|
||||
switch (opcode.instruction) {
|
||||
case 0b00_0000: //R-Type Instructions
|
||||
switch (opcode.function) {
|
||||
switch (instr.opcode) {
|
||||
case 0b00_0000: //R-Type opcodes
|
||||
switch (instr.function) {
|
||||
case 0b00_0000: //SLL(); break;
|
||||
if(opcode.value == 0) output = "NOP";
|
||||
else output = "SLL" + opcode.rd;
|
||||
if(instr.value == 0) output = "NOP";
|
||||
else output = "SLL" + instr.rd;
|
||||
break;
|
||||
case 0b00_0010: output = "SRL"; break;
|
||||
case 0b00_0011: output = "SRA"; break;
|
||||
|
|
@ -613,13 +613,13 @@ namespace ProjectPSX {
|
|||
case 0b10_1010: output = "SLT"; break;
|
||||
case 0b10_1011: output = "SLTU"; break;
|
||||
case 0b10_0101: output = "OR";
|
||||
values = "R" + opcode.rd + "," + (REG[opcode.rs] | REG[opcode.rt]).ToString("x8");
|
||||
values = "R" + instr.rd + "," + (REG[instr.rs] | REG[instr.rt]).ToString("x8");
|
||||
break;
|
||||
default: /*unimplementedWarning();*/ break;
|
||||
}
|
||||
break;
|
||||
case 0b00_0001:
|
||||
switch (opcode.rt) {
|
||||
switch (instr.rt) {
|
||||
case 0b00_0000: output = "BLTZ"; break;
|
||||
case 0b00_0001: output = "BGEZ"; break;
|
||||
default: /*unimplementedWarning();*/ break;
|
||||
|
|
@ -628,7 +628,7 @@ namespace ProjectPSX {
|
|||
|
||||
case 0b00_0010: //J();
|
||||
output = "J";
|
||||
values = ((PC_Predictor & 0xF000_0000) | (opcode.addr << 2)).ToString("x8");
|
||||
values = ((PC_Predictor & 0xF000_0000) | (instr.addr << 2)).ToString("x8");
|
||||
break;
|
||||
case 0b00_0011: //JAL();
|
||||
output = "JAL";
|
||||
|
|
@ -638,7 +638,7 @@ namespace ProjectPSX {
|
|||
break;
|
||||
case 0b00_0101: //BNE();
|
||||
output = "BNE";
|
||||
values = "R" + opcode.rs +"[" + REG[opcode.rs].ToString("x8") + "]" +"," + "R" + opcode.rt + "[" + REG[opcode.rt].ToString("x8") + "], (" + ((PC_Now)+(opcode.imm_s << 2)).ToString("x8") +")";
|
||||
values = "R" + instr.rs +"[" + REG[instr.rs].ToString("x8") + "]" +"," + "R" + instr.rt + "[" + REG[instr.rt].ToString("x8") + "], (" + ((PC_Now)+(instr.imm_s << 2)).ToString("x8") +")";
|
||||
break;
|
||||
case 0b00_0110: //BLEZ();
|
||||
output = "BLEZ";
|
||||
|
|
@ -648,20 +648,20 @@ namespace ProjectPSX {
|
|||
break;
|
||||
case 0b00_1000: //ADDI();
|
||||
output = "ADDI";
|
||||
int rs = (int)REG[opcode.rs];
|
||||
int imm_s = (int)opcode.imm_s;
|
||||
int rs = (int)REG[instr.rs];
|
||||
int imm_s = (int)instr.imm_s;
|
||||
try {
|
||||
uint addi = (uint)checked(rs + imm_s);
|
||||
values = "R" + opcode.rs + "," + (addi).ToString("x8") + " R" + opcode.rs + "=" + REG[opcode.rs].ToString("x8"); ;
|
||||
values = "R" + instr.rs + "," + (addi).ToString("x8") + " R" + instr.rs + "=" + REG[instr.rs].ToString("x8"); ;
|
||||
//Console.WriteLine("ADDI!");
|
||||
} catch (OverflowException) {
|
||||
values = "R" + opcode.rt + "," + REG[opcode.rs].ToString("x8") + " + " + opcode.imm_s.ToString("x8") + " UNHANDLED OVERFLOW";
|
||||
values = "R" + instr.rt + "," + REG[instr.rs].ToString("x8") + " + " + instr.imm_s.ToString("x8") + " UNHANDLED OVERFLOW";
|
||||
}
|
||||
break;
|
||||
case 0b00_1001: //ADDIU();
|
||||
// setReg(opcode.rt, REG[opcode.rs] + opcode.imm_s);
|
||||
// setReg(instr.rt, REG[instr.rs] + instr.imm_s);
|
||||
output = "ADDIU";
|
||||
values = "R" + opcode.rt + "," + (REG[opcode.rs] + opcode.imm_s).ToString("x8");
|
||||
values = "R" + instr.rt + "," + (REG[instr.rs] + instr.imm_s).ToString("x8");
|
||||
break;
|
||||
case 0b00_1010: //SLTI();
|
||||
output = "SLTI";
|
||||
|
|
@ -674,26 +674,26 @@ namespace ProjectPSX {
|
|||
output = "ANDI";
|
||||
break;
|
||||
case 0b00_1101: //ORI();
|
||||
//setReg(opcode.rt, REG[opcode.rs] | opcode.imm);
|
||||
//setReg(instr.rt, REG[instr.rs] | instr.imm);
|
||||
output = "ORI";
|
||||
values = "R" + opcode.rt + "," + (REG[opcode.rs] | opcode.imm).ToString("x8");
|
||||
values = "R" + instr.rt + "," + (REG[instr.rs] | instr.imm).ToString("x8");
|
||||
break;
|
||||
case 0b00_1111: //LUI();
|
||||
//setReg(opcode.rt, opcode.imm << 16);
|
||||
//setReg(instr.rt, instr.imm << 16);
|
||||
output = "LUI";
|
||||
values = "R" + opcode.rt + "," + (opcode.imm << 16).ToString("x8");
|
||||
values = "R" + instr.rt + "," + (instr.imm << 16).ToString("x8");
|
||||
break;
|
||||
|
||||
|
||||
case 0b01_0000: //CoProcessor Instructions
|
||||
switch (opcode.format) {
|
||||
case 0b01_0000: //CoProcessor opcodes
|
||||
switch (instr.format) {
|
||||
case 0b0_0000://MFC0();
|
||||
output = "MFC0";
|
||||
break;
|
||||
case 0b0_0100://MTC0();
|
||||
// Cop0Reg[opcode.fs] = REG[opcode.ft];
|
||||
// Cop0Reg[instr.fs] = REG[instr.ft];
|
||||
output = "MTC0";
|
||||
values = "R" + opcode.fs + "," + "R" + opcode.ft + "["+REG[opcode.ft].ToString("x8")+"]";
|
||||
values = "R" + instr.fs + "," + "R" + instr.ft + "["+REG[instr.ft].ToString("x8")+"]";
|
||||
break;
|
||||
case 0b1_0000: //RFE(); break;
|
||||
output = "RFE";
|
||||
|
|
@ -716,8 +716,8 @@ namespace ProjectPSX {
|
|||
break;
|
||||
case 0b10_0011:// LW(mmu);
|
||||
if ((SR & 0x10000) == 0)
|
||||
values = "R" + opcode.rt + "[" + REG[opcode.rt].ToString("x8") + "], " + opcode.imm_s.ToString("x8") + "(" + REG[opcode.rs].ToString("x8") + ")" + "[" + (opcode.imm_s + REG[opcode.rs]).ToString("x8") + "]";
|
||||
else values = "R" + opcode.rt + "[" + REG[opcode.rt].ToString("x8") + "], " + opcode.imm_s.ToString("x8") + "(" + REG[opcode.rs].ToString("x8") + ")" + "[" + (opcode.imm_s + REG[opcode.rs]).ToString("x8") + "]" + " WARNING IGNORED LOAD";
|
||||
values = "R" + instr.rt + "[" + REG[instr.rt].ToString("x8") + "], " + instr.imm_s.ToString("x8") + "(" + REG[instr.rs].ToString("x8") + ")" + "[" + (instr.imm_s + REG[instr.rs]).ToString("x8") + "]";
|
||||
else values = "R" + instr.rt + "[" + REG[instr.rt].ToString("x8") + "], " + instr.imm_s.ToString("x8") + "(" + REG[instr.rs].ToString("x8") + ")" + "[" + (instr.imm_s + REG[instr.rs]).ToString("x8") + "]" + " WARNING IGNORED LOAD";
|
||||
output = "LW";
|
||||
break;
|
||||
case 0b10_1001:// SH(mmu);
|
||||
|
|
@ -728,11 +728,11 @@ namespace ProjectPSX {
|
|||
break;
|
||||
case 0b10_1011:// SW(mmu);
|
||||
//if ((SR & 0x10000) == 0)
|
||||
// mmu.write32(REG[opcode.rs] + opcode.imm_s, REG[opcode.rt]);
|
||||
// mmu.write32(REG[instr.rs] + instr.imm_s, REG[instr.rt]);
|
||||
output = "SW";
|
||||
if ((SR & 0x10000) == 0)
|
||||
values = "R" + opcode.rt + "["+REG[opcode.rt].ToString("x8") + "], " + opcode.imm_s.ToString("x8") + "(" + REG[opcode.rs].ToString("x8") +")" + "["+ (opcode.imm_s + REG[opcode.rs]).ToString("x8") + "]";
|
||||
else values = "R" + opcode.rt + "[" + REG[opcode.rt].ToString("x8") + "], " + opcode.imm_s.ToString("x8") + "(" + REG[opcode.rs].ToString("x8") + ")" + "[" + (opcode.imm_s + REG[opcode.rs]).ToString("x8") + "]" + " WARNING IGNORED WRITE";
|
||||
values = "R" + instr.rt + "["+REG[instr.rt].ToString("x8") + "], " + instr.imm_s.ToString("x8") + "(" + REG[instr.rs].ToString("x8") +")" + "["+ (instr.imm_s + REG[instr.rs]).ToString("x8") + "]";
|
||||
else values = "R" + instr.rt + "[" + REG[instr.rt].ToString("x8") + "], " + instr.imm_s.ToString("x8") + "(" + REG[instr.rs].ToString("x8") + ")" + "[" + (instr.imm_s + REG[instr.rs]).ToString("x8") + "]" + " WARNING IGNORED WRITE";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue