mirror of
https://github.com/SourMesen/Mesen2.git
synced 2025-04-02 10:21:44 -04:00
4ce300877d
Save ram is not mirrored across the entire 8kb, can only be accessed in the first 2kb This fixes Death Bringer corrupting save ram when trying to start a new game
450 lines
13 KiB
C++
450 lines
13 KiB
C++
#include "pch.h"
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#include "PCE/PceConsole.h"
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#include "PCE/PceMemoryManager.h"
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#include "PCE/PceVpc.h"
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#include "PCE/PceVce.h"
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#include "PCE/PceTimer.h"
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#include "PCE/PcePsg.h"
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#include "PCE/PceCpu.h"
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#include "PCE/PceControlManager.h"
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#include "PCE/CdRom/PceCdRom.h"
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#include "Shared/MessageManager.h"
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#include "Shared/EmuSettings.h"
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#include "Utilities/Serializer.h"
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PceMemoryManager::PceMemoryManager(Emulator* emu, PceConsole* console, PceVpc* vpc, PceVce* vce, PceControlManager* controlManager, PcePsg* psg, PceTimer* timer, IPceMapper* mapper, PceCdRom* cdrom, vector<uint8_t>& romData, uint32_t cardRamSize, bool cdromUnitEnabled)
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{
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_emu = emu;
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_cheatManager = _emu->GetCheatManager();
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_console = console;
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_vpc = vpc;
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_vce = vce;
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_psg = psg;
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_timer = timer;
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_mapper = mapper;
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_cdrom = cdrom;
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_controlManager = controlManager;
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_prgRomSize = (uint32_t)romData.size();
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_prgRom = new uint8_t[_prgRomSize];
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_workRamSize = console->IsSuperGrafx() ? 0x8000 : 0x2000;
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_workRam = new uint8_t[_workRamSize];
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_unmappedBank = new uint8_t[0x2000];
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memset(_unmappedBank, 0xFF, 0x2000);
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memcpy(_prgRom, romData.data(), _prgRomSize);
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_console->InitializeRam(_workRam, _workRamSize);
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_cdromUnitEnabled = cdromUnitEnabled;
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if(cardRamSize > 0) {
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if(cardRamSize == 0x30000) {
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//Super/Arcade CD-ROM
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_cardRamStartBank = 0x68;
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_cardRamEndBank = 0x7F;
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} else if(cardRamSize == 0x8000) {
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//Populous
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_cardRamStartBank = 0x40;
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_cardRamEndBank = 0x5F;
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}
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_cardRamSize = cardRamSize;
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_cardRam = new uint8_t[cardRamSize];
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_console->InitializeRam(_cardRam, _cardRamSize);
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_emu->RegisterMemory(MemoryType::PceCardRam, _cardRam, _cardRamSize);
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}
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_emu->RegisterMemory(MemoryType::PcePrgRom, _prgRom, _prgRomSize);
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_emu->RegisterMemory(MemoryType::PceWorkRam, _workRam, _workRamSize);
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_cdromRam = (uint8_t*)_emu->GetMemory(MemoryType::PceCdromRam).Memory;
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_saveRam = (uint8_t*)_emu->GetMemory(MemoryType::PceSaveRam).Memory;
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//CPU boots up in slow speed
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_state.FastCpuSpeed = false;
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UpdateExecCallback();
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//Set to 0 on power on
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_state.DisabledIrqs = 0;
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//MPR 7 is set to 0 on power on
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_state.Mpr[7] = 0;
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if(_emu->GetSettings()->GetPcEngineConfig().EnableRandomPowerOnState) {
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//Other MPR registers are random
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//Note this appears to break some games?
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for(int i = 0; i < 7; i++) {
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_state.Mpr[i] = RandomHelper::GetValue(0, 255);
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}
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}
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//Map ROM to all 128 banks
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uint32_t bankCount = _prgRomSize / 0x2000;
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if(bankCount == 0x30) {
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//384KB games - Mirrored as 256x2, 128x4
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uint32_t bankOffsets[8] = { 0, 0x10, 0, 0x10, 0x20, 0x20, 0x20, 0x20 };
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UpdateMappings(bankOffsets);
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} else if(bankCount == 0x40) {
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//512KB games - Mirrored as either 256x2 + 256x2, or 512x2
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//Mirror them as 256 + 256x3 for compatibility
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uint32_t bankOffsets[8] = { 0, 0x10, 0x20, 0x30, 0x20, 0x30, 0x20, 0x30 };
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UpdateMappings(bankOffsets);
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} else if(bankCount == 0x60) {
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//768KB games - Mirrored as 512x1 + 256x2
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uint32_t bankOffsets[8] = { 0, 0x10, 0x20, 0x30, 0x40, 0x50, 0x40, 0x50 };
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UpdateMappings(bankOffsets);
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} else {
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//Use default mirroring for anything else
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uint32_t bankOffsets[8] = { 0, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70 };
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UpdateMappings(bankOffsets);
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}
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}
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PceMemoryManager::~PceMemoryManager()
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{
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delete[] _prgRom;
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delete[] _workRam;
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delete[] _cardRam;
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delete[] _unmappedBank;
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}
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void PceMemoryManager::SetSpeed(bool slow)
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{
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_state.FastCpuSpeed = !slow;
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UpdateExecCallback();
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}
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void PceMemoryManager::UpdateMappings(uint32_t bankOffsets[8])
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{
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int bankCount = _prgRomSize / 0x2000;
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for(int i = 0; i <= 0x7F; i++) {
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//00 - 7F
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int bank = (bankOffsets[i >> 4] + (i & 0x0F)) % bankCount;
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_readBanks[i] = _prgRom + (bank * 0x2000);
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_bankMemType[i] = MemoryType::PcePrgRom;
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}
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for(int i = 0x80; i <= 0xFF; i++) {
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//80 - FF
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_readBanks[i] = _unmappedBank;
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_bankMemType[i] = MemoryType::None;
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}
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for(int i = 0; i < 4; i++) {
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//F8 - FB
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_readBanks[0xF8 + i] = _workRam + ((i * 0x2000) % _workRamSize);
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_writeBanks[0xF8 + i] = _workRam + ((i * 0x2000) % _workRamSize);
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_bankMemType[0xF8 + i] = MemoryType::PceWorkRam;
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}
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if(_cardRam) {
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for(uint32_t i = _cardRamStartBank; i <= _cardRamEndBank; i++) {
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//68-7F (cdrom) or 40-5F (populous)
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_readBanks[i] = _cardRam + (((i - _cardRamStartBank) * 0x2000) % _cardRamSize);
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_writeBanks[i] = _cardRam + (((i - _cardRamStartBank) * 0x2000) % _cardRamSize);
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_bankMemType[i] = MemoryType::PceCardRam;
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}
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}
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UpdateCdRomBanks();
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}
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void PceMemoryManager::UpdateCdRomBanks()
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{
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if(_cdrom) {
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_cdrom->InitMemoryBanks(_readBanks, _writeBanks, _bankMemType, _unmappedBank);
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}
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}
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void PceMemoryManager::UpdateExecCallback()
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{
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if(_cdromUnitEnabled) {
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if(_console->IsSuperGrafx()) {
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_exec = &PceMemoryManager::ExecTemplate<true, true>;
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} else {
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_exec = &PceMemoryManager::ExecTemplate<true, false>;
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}
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} else {
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if(_console->IsSuperGrafx()) {
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_exec = &PceMemoryManager::ExecTemplate<false, true>;
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} else {
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_exec = &PceMemoryManager::ExecTemplate<false, false>;
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}
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}
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_fastExec = _exec;
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if(!_state.FastCpuSpeed) {
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_exec = &PceMemoryManager::ExecSlow;
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}
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}
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template<bool hasCdRom, bool isSuperGrafx>
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void PceMemoryManager::ExecTemplate()
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{
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_state.CycleCount += 3;
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_timer->Exec();
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if constexpr(isSuperGrafx) {
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_vpc->ExecSuperGrafx();
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} else {
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_vpc->Exec();
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}
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if constexpr(hasCdRom) {
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_cdrom->Exec();
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}
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}
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void PceMemoryManager::ExecSlow()
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{
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(this->*_fastExec)();
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(this->*_fastExec)();
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(this->*_fastExec)();
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(this->*_fastExec)();
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}
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uint8_t PceMemoryManager::ReadRegister(uint16_t addr)
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{
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if(addr <= 0x3FF) {
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//VDC
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Exec(); //CPU is delayed by 1 CPU cycle when reading/writing to VDC/VCE
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return _vpc->Read(addr);
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} else if(addr <= 0x7FF) {
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//VCE
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Exec(); //CPU is delayed by 1 CPU cycle when reading/writing to VDC/VCE
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_vpc->DrawScanline();
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return _vce->Read(addr);
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} else if(addr <= 0xBFF) {
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//PSG
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return _state.IoBuffer;
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} else if(addr <= 0xFFF) {
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//Timer
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_state.IoBuffer = (_state.IoBuffer & 0x80) | (_timer->Read(addr) & 0x7F);
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return _state.IoBuffer;
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} else if(addr <= 0x13FF) {
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//IO
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//Some NA games crash is bit 6 is not set (region locking) - e.g Order of the Griffon
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//When in Auto mode, pretend this is a turbografx console for compatibilty
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PcEngineConfig& cfg = _emu->GetSettings()->GetPcEngineConfig();
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PceConsoleType consoleType = cfg.ConsoleType;
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bool isTurboGrafx = consoleType == PceConsoleType::Auto || consoleType == PceConsoleType::TurboGrafx;
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//Some games use the CDROM addon's save ram to save data and will check bit 7 for presence of the CDROM
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//Unless the UI option to disable the save ram for hucard games is enabled, always report that the CDROM is connected
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bool cdromConnected = _cdrom != nullptr;
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_state.IoBuffer = (
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(cdromConnected ? 0 : 0x80) |
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(isTurboGrafx ? 0 : 0x40) |
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0x30 |
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_controlManager->ReadInputPort()
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);
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return _state.IoBuffer;
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} else if(addr <= 0x17FF) {
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//IRQ
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switch(addr & 0x03) {
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case 0:
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case 1:
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break;
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case 2: _state.IoBuffer = (_state.IoBuffer & 0xF8) | (_state.DisabledIrqs & 0x07); break;
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case 3: _state.IoBuffer = (_state.IoBuffer & 0xF8) | (_state.ActiveIrqs & 0x07); break;
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}
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return _state.IoBuffer;
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} else if(addr <= 0x1BFF) {
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return _cdrom ? _cdrom->Read(addr) : 0xFF;
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} else if(_console->GetRomFormat() == RomFormat::PceHes && addr <= 0x1C01) {
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//Infinite BRA loop
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return addr & 0x01 ? 0xFE : 0x80;
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}
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LogDebug("[Debug] Read - missing handler: $" + HexUtilities::ToHex(addr));
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return 0xFF;
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}
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void PceMemoryManager::WriteRegister(uint16_t addr, uint8_t value)
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{
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if(addr <= 0x3FF) {
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_console->GetCpu()->RunIdleCpuCycle(); //CPU is delayed by 1 CPU cycle when reading/writing to VDC/VCE
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_vpc->Write(addr, value);
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} else if(addr <= 0x7FF) {
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_console->GetCpu()->RunIdleCpuCycle(); //CPU is delayed by 1 CPU cycle when reading/writing to VDC/VCE
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_vpc->DrawScanline();
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_vce->Write(addr, value);
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} else if(addr <= 0xBFF) {
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//PSG
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_psg->Write(addr, value);
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_state.IoBuffer = value;
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} else if(addr <= 0xFFF) {
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//Timer
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_timer->Write(addr, value);
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_state.IoBuffer = value;
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} else if(addr <= 0x13FF) {
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//IO
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_controlManager->WriteInputPort(value);
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_state.IoBuffer = value;
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} else if(addr <= 0x17FF) {
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//IRQ
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switch(addr & 0x03) {
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case 0:
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case 1:
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LogDebug("[Debug] Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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break;
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case 2: _state.DisabledIrqs = value & 0x07; break;
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case 3: ClearIrqSource(PceIrqSource::TimerIrq); break;
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}
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_state.IoBuffer = value;
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} else if(addr <= 0x1BFF) {
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if(_cdrom) {
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_cdrom->Write(addr, value);
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}
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} else {
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LogDebug("[Debug] Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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}
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}
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void PceMemoryManager::WriteVdc(uint16_t addr, uint8_t value)
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{
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if(_emu->ProcessMemoryWrite<CpuType::Pce>(addr, value, MemoryOperationType::Write)) {
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_console->GetCpu()->RunIdleCpuCycle(); //CPU is delayed by 1 CPU cycle when reading/writing to VDC/VCE
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_vpc->StVdcWrite(addr, value);
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}
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}
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uint8_t PceMemoryManager::DebugRead(uint16_t addr)
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{
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uint8_t bank = _state.Mpr[(addr & 0xE000) >> 13];
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if(bank != 0xFF) {
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return _readBanks[bank][addr & 0x1FFF];
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} else {
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//TODO read registers without side effects
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if(_console->GetRomFormat() == RomFormat::PceHes && addr >= 0x1C00 && addr <= 0x1C01) {
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//Patch to fix trace logger for HES files
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return addr & 0x01 ? 0xFE : 0x80;
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}
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}
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return 0xFF;
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}
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void PceMemoryManager::DebugWrite(uint16_t addr, uint8_t value)
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{
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uint8_t bank = _state.Mpr[(addr & 0xE000) >> 13];
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if(bank == 0xF7) {
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if(_writeBanks[0xF7] && (addr & 0x1FFF) <= 0x7FF) {
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//Only allow writes to the first 2kb - save RAM is not mirrored
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//"Death Bringer" breaks if save RAM is mirrored.
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_writeBanks[0xF7][addr & 0x7FF] = value;
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}
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} else if(bank != 0xFF) {
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uint8_t* data = _writeBanks[bank];
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if(data) {
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data[addr & 0x1FFF] = value;
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}
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} else {
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//TODO write registers
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}
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}
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void PceMemoryManager::SetMprValue(uint8_t regSelect, uint8_t value)
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{
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if(regSelect == 0) {
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return;
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}
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_state.MprReadBuffer = value;
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for(int i = 0; i < 8; i++) {
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if(regSelect & (1 << i)) {
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_state.Mpr[i] = value;
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}
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}
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}
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uint8_t PceMemoryManager::GetMprValue(uint8_t regSelect)
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{
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if(regSelect == 0) {
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//"If an operand of $00 is used, the accumulator is loaded with the last value that was written with TAM"
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return _state.MprReadBuffer;
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}
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uint8_t value = 0;
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for(int i = 0; i < 8; i++) {
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//"If multiple bits are set in the operand to TMA, the values from several MPRs are combined togetherand returned."
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if(regSelect & (1 << i)) {
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value |= _state.Mpr[i];
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}
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}
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_state.MprReadBuffer = value;
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return value;
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}
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AddressInfo PceMemoryManager::GetAbsoluteAddress(uint32_t relAddr)
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{
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uint8_t bank = _state.Mpr[(relAddr & 0xE000) >> 13];
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uint32_t absAddr;
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switch(_bankMemType[bank]) {
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case MemoryType::PcePrgRom: absAddr = (uint32_t)(_readBanks[bank] - _prgRom) + (relAddr & 0x1FFF); break;
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case MemoryType::PceWorkRam: absAddr = (uint32_t)(_readBanks[bank] - _workRam) + (relAddr & 0x1FFF); break;
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case MemoryType::PceSaveRam:
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if((relAddr & 0x1FFF) <= 0x7FF) {
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absAddr = (uint32_t)(_readBanks[bank] - _saveRam) + (relAddr & 0x7FF);
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} else {
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//Unmapped past the first 2kb
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return { -1, MemoryType::None };
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}
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break;
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case MemoryType::PceCdromRam: absAddr = (uint32_t)(_readBanks[bank] - _cdromRam) + (relAddr & 0x1FFF); break;
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case MemoryType::PceCardRam: absAddr = (uint32_t)(_readBanks[bank] - _cardRam) + (relAddr & 0x1FFF); break;
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default: return { -1, MemoryType::None };
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}
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return { (int32_t)absAddr, _bankMemType[bank] };
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}
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AddressInfo PceMemoryManager::GetRelativeAddress(AddressInfo absAddr, uint16_t pc)
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{
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//Start with the bank that the CPU is executing from
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//This is to favor any mirror that exists in the current bank
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//instead of always picking the first mirror, when mirrors exist.
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int startBank = pc >> 13;
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for(int i = 0; i < 8; i++) {
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int bank = (startBank + i) & 0x07;
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AddressInfo bankStart = GetAbsoluteAddress(bank * 0x2000);
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if(bankStart.Type == absAddr.Type && bankStart.Address == (absAddr.Address & ~0x1FFF)) {
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if(bankStart.Type == MemoryType::PceSaveRam && (absAddr.Address & 0x1FFF) >= 0x800) {
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//unmapped
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break;
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}
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return { (bank << 13) | (absAddr.Address & 0x1FFF), MemoryType::PceMemory };
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}
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}
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return { -1, MemoryType::None };
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}
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void PceMemoryManager::Serialize(Serializer& s)
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{
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SVArray(_workRam, _workRamSize);
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SVArray(_cardRam, _cardRamSize);
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SV(_state.ActiveIrqs);
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SV(_state.CycleCount);
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SV(_state.DisabledIrqs);
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SV(_state.FastCpuSpeed);
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SV(_state.IoBuffer);
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for(int i = 0; i < 8; i++) {
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SVI(_state.Mpr[i]);
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}
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SV(_state.MprReadBuffer);
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if(!s.IsSaving()) {
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UpdateExecCallback();
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}
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}
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