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https://github.com/SourMesen/Mesen2.git
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01c65c3549
Both games do CLI followed by LDA $0000 in their IRQ handler. The old logic would prevent an additional IRQ from firing after the LDA, because the LDA acknowledges the IRQ. But at this point, the CPU already processed the IRQ and will execute it anyway (the acknowledge is too late because it occurs on the last cycle of the instruction). Both games rely on this behavior, otherwise the IRQ handler's logic is executed too fast and the shaking occurs depending on the timing of the timer irq vs the rcr irq
443 lines
14 KiB
C++
443 lines
14 KiB
C++
#include "pch.h"
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#include "PceCpu.h"
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#include "Shared/Emulator.h"
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#include "Shared/EmuSettings.h"
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#include "PCE/PceMemoryManager.h"
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#include "PCE/PceConsole.h"
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#include "Utilities/Serializer.h"
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#include "Utilities/RandomHelper.h"
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typedef PceCpu C;
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PceCpu::Func const PceCpu::_opTable[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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&C::BRK, &C::ORA, &C::SXY, &C::ST0, &C::TSB, &C::ORA, &C::ASL_Memory, &C::RMB0, &C::PHP, &C::ORA, &C::ASL_Acc, &C::NOP, &C::TSB, &C::ORA, &C::ASL_Memory, &C::BBR0, //0
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&C::BPL, &C::ORA, &C::ORA, &C::ST1, &C::TRB, &C::ORA, &C::ASL_Memory, &C::RMB1, &C::CLC, &C::ORA, &C::INC_Acc, &C::NOP, &C::TRB, &C::ORA, &C::ASL_Memory, &C::BBR1, //1
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&C::JSR, &C::AND, &C::SAX, &C::ST2, &C::BIT, &C::AND, &C::ROL_Memory, &C::RMB2, &C::PLP, &C::AND, &C::ROL_Acc, &C::NOP, &C::BIT, &C::AND, &C::ROL_Memory, &C::BBR2, //2
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&C::BMI, &C::AND, &C::AND, &C::NOP, &C::BIT, &C::AND, &C::ROL_Memory, &C::RMB3, &C::SEC, &C::AND, &C::DEC_Acc, &C::NOP, &C::BIT, &C::AND, &C::ROL_Memory, &C::BBR3, //3
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&C::RTI, &C::EOR, &C::SAY, &C::TMA, &C::BSR, &C::EOR, &C::LSR_Memory, &C::RMB4, &C::PHA, &C::EOR, &C::LSR_Acc, &C::NOP, &C::JMP_Abs, &C::EOR, &C::LSR_Memory, &C::BBR4, //4
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&C::BVC, &C::EOR, &C::EOR, &C::TAM, &C::CSL, &C::EOR, &C::LSR_Memory, &C::RMB5, &C::CLI, &C::EOR, &C::PHY, &C::NOP, &C::NOP, &C::EOR, &C::LSR_Memory, &C::BBR5, //5
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&C::RTS, &C::ADC, &C::CLA, &C::NOP, &C::STZ, &C::ADC, &C::ROR_Memory, &C::RMB6, &C::PLA, &C::ADC, &C::ROR_Acc, &C::NOP, &C::JMP_Ind, &C::ADC, &C::ROR_Memory, &C::BBR6, //6
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&C::BVS, &C::ADC, &C::ADC, &C::TII, &C::STZ, &C::ADC, &C::ROR_Memory, &C::RMB7, &C::SEI, &C::ADC, &C::PLY, &C::NOP, &C::JMP_AbsX, &C::ADC, &C::ROR_Memory, &C::BBR7, //7
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&C::BRA, &C::STA, &C::CLX, &C::TST, &C::STY, &C::STA, &C::STX, &C::SMB0, &C::DEY, &C::BIT, &C::TXA, &C::NOP, &C::STY, &C::STA, &C::STX, &C::BBS0, //8
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&C::BCC, &C::STA, &C::STA, &C::TST, &C::STY, &C::STA, &C::STX, &C::SMB1, &C::TYA, &C::STA, &C::TXS, &C::NOP, &C::STZ, &C::STA, &C::STZ, &C::BBS1, //9
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&C::LDY, &C::LDA, &C::LDX, &C::TST, &C::LDY, &C::LDA, &C::LDX, &C::SMB2, &C::TAY, &C::LDA, &C::TAX, &C::NOP, &C::LDY, &C::LDA, &C::LDX, &C::BBS2, //A
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&C::BCS, &C::LDA, &C::LDA, &C::TST, &C::LDY, &C::LDA, &C::LDX, &C::SMB3, &C::CLV, &C::LDA, &C::TSX, &C::NOP, &C::LDY, &C::LDA, &C::LDX, &C::BBS3, //B
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&C::CPY, &C::CPA, &C::CLY, &C::TDD, &C::CPY, &C::CPA, &C::DEC, &C::SMB4, &C::INY, &C::CPA, &C::DEX, &C::NOP, &C::CPY, &C::CPA, &C::DEC, &C::BBS4, //C
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&C::BNE, &C::CPA, &C::CPA, &C::TIN, &C::CSH, &C::CPA, &C::DEC, &C::SMB5, &C::CLD, &C::CPA, &C::PHX, &C::NOP, &C::NOP, &C::CPA, &C::DEC, &C::BBS5, //D
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&C::CPX, &C::SBC, &C::NOP, &C::TIA, &C::CPX, &C::SBC, &C::INC, &C::SMB6, &C::INX, &C::SBC, &C::NOP, &C::NOP, &C::CPX, &C::SBC, &C::INC, &C::BBS6, //E
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&C::BEQ, &C::SBC, &C::SBC, &C::TAI, &C::SET, &C::SBC, &C::INC, &C::SMB7, &C::SED, &C::SBC, &C::PLX, &C::NOP, &C::NOP, &C::SBC, &C::INC, &C::BBS7 //F
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};
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typedef PceAddrMode M;
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PceAddrMode const PceCpu::_addrMode[] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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M::Imm, M::IndX, M::Imp, M::Imm, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imp, M::Abs, M::Abs, M::Abs, M::ZeroRel, //0
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M::Rel, M::IndY, M::ZInd, M::Imm, M::Zero, M::ZeroX, M::ZeroX, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::Abs, M::AbsX, M::AbsX, M::ZeroRel,//1
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M::Abs, M::IndX, M::Imp, M::Imm, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imp, M::Abs, M::Abs, M::Abs, M::ZeroRel, //2
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M::Rel, M::IndY, M::ZInd, M::Imp, M::ZeroX, M::ZeroX, M::ZeroX, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::AbsX, M::AbsX, M::AbsX, M::ZeroRel,//3
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M::Imp, M::IndX, M::Imp, M::Imm, M::Rel, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imp, M::Abs, M::Abs, M::Abs, M::ZeroRel, //4
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M::Rel, M::IndY, M::ZInd, M::Imm, M::Imp, M::ZeroX, M::ZeroX, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::Imp, M::AbsX, M::AbsX, M::ZeroRel,//5
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M::Imp, M::IndX, M::Imp, M::Imp, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Acc, M::Imp, M::Ind, M::Abs, M::Abs, M::ZeroRel, //6
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M::Rel, M::IndY, M::ZInd, M::Block, M::ZeroX, M::ZeroX, M::ZeroX, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::AbsXInd, M::AbsX, M::AbsX, M::ZeroRel,//7
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M::Rel, M::IndX, M::Imp, M::ImZero, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imp, M::Abs, M::Abs, M::Abs, M::ZeroRel, //8
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M::Rel, M::IndY, M::ZInd, M::ImAbs, M::ZeroX, M::ZeroX, M::ZeroY, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::Abs, M::AbsX, M::AbsX, M::ZeroRel,//9
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M::Imm, M::IndX, M::Imm, M::ImZeroX, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imp, M::Abs, M::Abs, M::Abs, M::ZeroRel, //A
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M::Rel, M::IndY, M::ZInd, M::ImAbsX, M::ZeroX, M::ZeroX, M::ZeroY, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::AbsX, M::AbsX, M::AbsY, M::ZeroRel, //B
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M::Imm, M::IndX, M::Imp, M::Block, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imp, M::Abs, M::Abs, M::Abs, M::ZeroRel, //C
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M::Rel, M::IndY, M::ZInd, M::Block, M::Imp, M::ZeroX, M::ZeroX, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::Imp, M::AbsX, M::AbsX, M::ZeroRel,//D
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M::Imm, M::IndX, M::Imp, M::Block, M::Zero, M::Zero, M::Zero, M::Zero, M::Imp, M::Imm, M::Imp, M::Imp, M::Abs, M::Abs, M::Abs, M::ZeroRel, //E
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M::Rel, M::IndY, M::ZInd, M::Block, M::Imp, M::ZeroX, M::ZeroX, M::Zero, M::Imp, M::AbsY, M::Imp, M::Imp, M::Imp, M::AbsX, M::AbsX, M::ZeroRel,//F
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};
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#ifndef DUMMYCPU
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PceCpu::PceCpu(Emulator* emu, PceMemoryManager* memoryManager)
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{
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_emu = emu;
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_memoryManager = memoryManager;
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_instAddrMode = PceAddrMode::None;
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_state = {};
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_operand = 0;
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_state.PC = _memoryManager->Read(PceCpu::ResetVector) | _memoryManager->Read(PceCpu::ResetVector + 1) << 8;
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//I is set on power on
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SetFlags(PceCpuFlags::Interrupt);
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//T & M are always cleared on power on
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ClearFlags(PceCpuFlags::Decimal | PceCpuFlags::Memory);
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if(_emu->GetSettings()->GetPcEngineConfig().EnableRandomPowerOnState) {
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//A, X, Y, S are random on power on
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_state.A = RandomHelper::GetValue(0, 255);
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_state.X = RandomHelper::GetValue(0, 255);
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_state.Y = RandomHelper::GetValue(0, 255);
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_state.SP = RandomHelper::GetValue(0, 255);
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//Other flags are random
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if(RandomHelper::GetBool()) {
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SetFlags(PceCpuFlags::Zero);
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}
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if(RandomHelper::GetBool()) {
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SetFlags(PceCpuFlags::Negative);
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}
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if(RandomHelper::GetBool()) {
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SetFlags(PceCpuFlags::Overflow);
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}
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if(RandomHelper::GetBool()) {
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SetFlags(PceCpuFlags::Carry);
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}
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}
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}
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#endif
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void PceCpu::Exec()
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{
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#ifndef DUMMYCPU
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_emu->ProcessInstruction<CpuType::Pce>();
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#endif
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//T flag is reset at the start of each instruction
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_memoryFlag = CheckFlag(PceCpuFlags::Memory);
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ClearFlags(PceCpuFlags::Memory);
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uint8_t opCode = GetOPCode();
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_instAddrMode = _addrMode[opCode];
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FetchOperand();
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(this->*_opTable[opCode])();
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if(_pendingIrqs) {
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ProcessIrq(false);
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}
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}
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void PceCpu::FetchOperand()
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{
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switch(_instAddrMode) {
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case PceAddrMode::Acc:
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case PceAddrMode::Imp: DummyRead(); _operand = 0; break;
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case PceAddrMode::Imm:
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case PceAddrMode::Rel: _operand = GetImmediate(); break;
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case PceAddrMode::Zero: _operand = PceCpu::ZeroPage + GetZeroAddr(); DummyRead(); break;
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case PceAddrMode::ZeroX: _operand = PceCpu::ZeroPage + GetZeroXAddr(); DummyRead(); break;
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case PceAddrMode::ZeroY: _operand = PceCpu::ZeroPage + GetZeroYAddr(); DummyRead(); break;
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case PceAddrMode::Ind: _operand = GetIndAddr(); break;
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case PceAddrMode::IndX: _operand = GetIndXAddr(); break;
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case PceAddrMode::IndY: _operand = GetIndYAddr(); break;
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case PceAddrMode::Abs: _operand = GetAbsAddr(); DummyRead(); break;
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case PceAddrMode::AbsX: _operand = GetAbsXAddr(); DummyRead(); break;
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case PceAddrMode::AbsY: _operand = GetAbsYAddr(); DummyRead(); break;
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case PceAddrMode::ZeroRel: _operand = ReadWord(); break;
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case PceAddrMode::Block:
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_operand = ReadWord();
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_operand2 = ReadWord();
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_operand3 = ReadWord();
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break;
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case PceAddrMode::ZInd: _operand = GetIndZeroAddr(); break;
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case PceAddrMode::ImZero:
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_operand = ReadByte();
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_operand2 = PceCpu::ZeroPage + GetZeroAddr();
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DummyRead();
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break;
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case PceAddrMode::ImZeroX:
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_operand = ReadByte();
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_operand2 = PceCpu::ZeroPage + GetZeroXAddr();
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DummyRead();
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break;
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case PceAddrMode::ImAbs:
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_operand = ReadByte();
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_operand2 = GetAbsAddr();
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DummyRead();
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break;
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case PceAddrMode::ImAbsX:
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_operand = ReadByte();
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_operand2 = GetAbsXAddr();
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DummyRead();
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break;
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case PceAddrMode::AbsXInd:
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_operand = GetAbsXAddr();
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DummyRead();
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break;
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default:
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break;
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}
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}
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void PceCpu::SetRegister(uint8_t& reg, uint8_t value)
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{
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ClearFlags(PceCpuFlags::Zero | PceCpuFlags::Negative);
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SetZeroNegativeFlags(value);
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reg = value;
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}
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void PceCpu::Push(uint8_t value)
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{
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MemoryWrite(PceCpu::StackPage + SP(), value);
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SetSP(SP() - 1);
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}
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void PceCpu::Push(uint16_t value)
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{
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Push((uint8_t)(value >> 8));
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Push((uint8_t)value);
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}
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uint8_t PceCpu::Pop()
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{
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SetSP(SP() + 1);
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return MemoryRead(PceCpu::StackPage + SP());
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}
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uint16_t PceCpu::PopWord()
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{
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uint8_t lo = Pop();
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uint8_t hi = Pop();
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return lo | hi << 8;
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}
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uint8_t PceCpu::GetOPCode()
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{
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uint8_t opCode = MemoryRead(_state.PC, MemoryOperationType::ExecOpCode);
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_state.PC++;
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return opCode;
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}
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uint16_t PceCpu::GetOperand()
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{
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return _operand;
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}
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uint8_t PceCpu::GetOperandValue()
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{
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if(_instAddrMode >= PceAddrMode::Zero) {
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return MemoryRead(GetOperand());
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} else {
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return (uint8_t)GetOperand();
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}
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}
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void PceCpu::DummyRead()
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{
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MemoryRead(_state.PC, MemoryOperationType::DummyRead);
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}
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uint8_t PceCpu::ReadByte()
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{
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uint8_t value = MemoryRead(_state.PC, MemoryOperationType::ExecOperand);
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_state.PC++;
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return value;
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}
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uint16_t PceCpu::ReadWord()
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{
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uint8_t low = ReadByte();
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uint8_t high = ReadByte();
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return (high << 8) | low;
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}
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void PceCpu::ClearFlags(uint8_t flags)
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{
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_state.PS &= ~flags;
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}
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void PceCpu::SetFlags(uint8_t flags)
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{
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_state.PS |= flags;
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}
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bool PceCpu::CheckFlag(uint8_t flag)
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{
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return (_state.PS & flag) == flag;
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}
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void PceCpu::SetZeroNegativeFlags(uint8_t value)
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{
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if(value == 0) {
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SetFlags(PceCpuFlags::Zero);
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} else if(value & 0x80) {
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SetFlags(PceCpuFlags::Negative);
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}
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}
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void PceCpu::ProcessCpuCycle()
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{
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_state.CycleCount++;
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_memoryManager->Exec();
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_pendingIrqs = CheckFlag(PceCpuFlags::Interrupt) ? 0 : _memoryManager->GetPendingIrqs();
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}
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#ifndef DUMMYCPU
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void PceCpu::MemoryWrite(uint16_t addr, uint8_t value, MemoryOperationType operationType)
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{
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ProcessCpuCycle();
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_memoryManager->Write(addr, value, operationType);
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}
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uint8_t PceCpu::MemoryRead(uint16_t addr, MemoryOperationType operationType)
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{
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ProcessCpuCycle();
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uint8_t value = _memoryManager->Read(addr, operationType);
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return value;
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}
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#endif
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uint16_t PceCpu::MemoryReadWord(uint16_t addr, MemoryOperationType operationType)
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{
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uint8_t lo = MemoryRead(addr, operationType);
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uint8_t hi = MemoryRead(addr + 1, operationType);
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return lo | hi << 8;
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}
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uint16_t PceCpu::GetIndAddr()
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{
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return ReadWord();
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}
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uint8_t PceCpu::GetImmediate()
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{
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return ReadByte();
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}
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uint8_t PceCpu::GetZeroAddr()
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{
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return ReadByte();
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}
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uint8_t PceCpu::GetZeroXAddr()
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{
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uint8_t value = ReadByte();
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return value + X();
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}
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uint8_t PceCpu::GetZeroYAddr()
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{
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uint8_t value = ReadByte();
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return value + Y();
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}
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uint16_t PceCpu::GetAbsAddr()
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{
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return ReadWord();
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}
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uint16_t PceCpu::GetAbsXAddr()
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{
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uint16_t baseAddr = ReadWord();
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return baseAddr + X();
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}
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uint16_t PceCpu::GetAbsYAddr()
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{
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uint16_t baseAddr = ReadWord();
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return baseAddr + Y();
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}
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uint16_t PceCpu::ReadZeroPageWrap(uint8_t zero)
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{
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if(zero == 0xFF) {
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uint8_t lo = MemoryRead(PceCpu::ZeroPage + 0xFF);
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uint8_t hi = (MemoryRead(PceCpu::ZeroPage + 0x00) << 8);
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return lo | (hi << 8);
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} else {
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return MemoryReadWord(PceCpu::ZeroPage + zero);
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}
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}
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uint16_t PceCpu::GetIndZeroAddr()
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{
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uint8_t zero = ReadByte();
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DummyRead();
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uint16_t addr = ReadZeroPageWrap(zero);
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DummyRead();
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return addr;
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}
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uint16_t PceCpu::GetIndXAddr()
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{
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uint8_t zero = ReadByte();
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DummyRead();
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zero += X();
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uint16_t addr = ReadZeroPageWrap(zero);
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DummyRead();
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return addr;
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}
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uint16_t PceCpu::GetIndYAddr()
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{
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uint8_t zero = ReadByte();
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DummyRead();
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uint16_t addr = ReadZeroPageWrap(zero);
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DummyRead();
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return addr + Y();
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}
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void PceCpu::ProcessIrq(bool forBrk)
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{
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//Keep a copy of _pendingIrqs here, because its value can change
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//by the cycles the CPU runs before the value is used at the end
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uint8_t pendingIrqs = _pendingIrqs;
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#ifndef DUMMYCPU
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uint16_t originalPc = PC();
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#endif
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if(!forBrk) {
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DummyRead(); //fetch opcode (and discard it - $00 (BRK) is forced into the opcode register instead)
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DummyRead(); //read next instruction byte (actually the same as above, since PC increment is suppressed. Also discarded.)
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}
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DummyRead();
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Push((uint16_t)(PC()));
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DummyRead();
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DummyRead();
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if(forBrk) {
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//B flag is set on the stack for BRK
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Push((uint8_t)(PS() | PceCpuFlags::Break));
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} else {
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//"When an interrupt occurs P is pushed with the current state of D and T"
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//"when an interrupt occurs, [..] the value pushed to the stack has B cleared"
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Push((uint8_t)(PS() & ~PceCpuFlags::Break));
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}
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|
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//"Within the interrupt subroutine, the CPU clears D, T and sets I,"
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ClearFlags(PceCpuFlags::Decimal | PceCpuFlags::Memory);
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SetFlags(PceCpuFlags::Interrupt);
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|
|
|
if(forBrk) {
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SetPC(MemoryReadWord(PceCpu::Irq2Vector));
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} else if(pendingIrqs & (uint8_t)PceIrqSource::TimerIrq) {
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SetPC(MemoryReadWord(PceCpu::TimerIrqVector));
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} else if(pendingIrqs & (uint8_t)PceIrqSource::Irq1) {
|
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SetPC(MemoryReadWord(PceCpu::Irq1Vector));
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} else if(pendingIrqs & (uint8_t)PceIrqSource::Irq2) {
|
|
SetPC(MemoryReadWord(PceCpu::Irq2Vector));
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}
|
|
|
|
if(!forBrk) {
|
|
#ifndef DUMMYCPU
|
|
_emu->ProcessInterrupt<CpuType::Pce>(originalPc, _state.PC, false);
|
|
#endif
|
|
}
|
|
}
|
|
|
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void PceCpu::Serialize(Serializer& s)
|
|
{
|
|
SV(_state.PC);
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|
SV(_state.SP);
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|
SV(_state.PS);
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|
SV(_state.A);
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SV(_state.X);
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|
SV(_state.Y);
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|
SV(_state.CycleCount);
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}
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