mirror of
https://github.com/SourMesen/Mesen2.git
synced 2025-04-02 10:21:44 -04:00
781 lines
No EOL
19 KiB
C#
781 lines
No EOL
19 KiB
C#
using System;
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using System.Runtime.InteropServices;
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namespace Mesen.Interop;
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public enum SnesCpuStopState : byte
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{
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Running = 0,
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Stopped = 1,
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WaitingForIrq = 2
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}
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[Flags]
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public enum SnesCpuFlags : byte
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{
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Carry = 0x01,
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Zero = 0x02,
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IrqDisable = 0x04,
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Decimal = 0x08,
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IndexMode8 = 0x10,
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MemoryMode8 = 0x20,
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Overflow = 0x40,
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Negative = 0x80
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}
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[Flags]
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public enum SpcFlags : byte
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{
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Carry = 0x01,
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Zero = 0x02,
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IrqEnable = 0x04,
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HalfCarry = 0x08,
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Break = 0x10,
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DirectPage = 0x20,
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Overflow = 0x40,
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Negative = 0x80
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}
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public enum SnesIrqSource
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{
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None = 0,
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Ppu = 1,
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Coprocessor = 2
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}
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public struct SnesCpuState : BaseState
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{
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public UInt64 CycleCount;
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public UInt16 A;
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public UInt16 X;
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public UInt16 Y;
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public UInt16 SP;
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public UInt16 D;
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public UInt16 PC;
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public byte K;
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public byte DBR;
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public SnesCpuFlags PS;
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[MarshalAs(UnmanagedType.I1)] public bool EmulationMode;
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[MarshalAs(UnmanagedType.I1)] public byte NmiFlagCounter;
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[MarshalAs(UnmanagedType.I1)] public bool IrqLock;
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[MarshalAs(UnmanagedType.I1)] public bool NeedNmi;
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public byte IrqSource;
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public byte PrevIrqSource;
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public SnesCpuStopState StopState;
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}
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public struct SnesPpuState : BaseState
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{
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public UInt16 Cycle;
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public UInt16 Scanline;
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public UInt16 HClock;
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public UInt32 FrameCount;
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[MarshalAs(UnmanagedType.I1)] public bool ForcedBlank;
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public byte ScreenBrightness;
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public Mode7Config Mode7;
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public byte BgMode;
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[MarshalAs(UnmanagedType.I1)] public bool Mode1Bg3Priority;
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public byte MainScreenLayers;
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public byte SubScreenLayers;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
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public LayerConfig[] Layers;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public WindowConfig[] Window;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 6)]
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public WindowMaskLogic[] MaskLogic;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 5)]
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public byte[] WindowMaskMain;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 5)]
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public byte[] WindowMaskSub;
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public UInt16 VramAddress;
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public byte VramIncrementValue;
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public byte VramAddressRemapping;
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[MarshalAs(UnmanagedType.I1)] public bool VramAddrIncrementOnSecondReg;
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public UInt16 VramReadBuffer;
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public byte Ppu1OpenBus;
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public byte Ppu2OpenBus;
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public byte CgramAddress;
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public byte InternalCgramAddress;
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public byte CgramWriteBuffer;
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[MarshalAs(UnmanagedType.I1)] public bool CgramAddressLatch;
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public byte MosaicSize;
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public byte MosaicEnabled;
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public UInt16 OamRamAddress;
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public UInt16 InternalOamRamAddress;
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public byte OamMode;
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public UInt16 OamBaseAddress;
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public UInt16 OamAddressOffset;
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[MarshalAs(UnmanagedType.I1)] public bool EnableOamPriority;
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[MarshalAs(UnmanagedType.I1)] public bool ExtBgEnabled;
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[MarshalAs(UnmanagedType.I1)] public bool HiResMode;
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[MarshalAs(UnmanagedType.I1)] public bool ScreenInterlace;
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[MarshalAs(UnmanagedType.I1)] public bool ObjInterlace;
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[MarshalAs(UnmanagedType.I1)] public bool OverscanMode;
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[MarshalAs(UnmanagedType.I1)] public bool DirectColorMode;
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public ColorWindowMode ColorMathClipMode;
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public ColorWindowMode ColorMathPreventMode;
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[MarshalAs(UnmanagedType.I1)] public bool ColorMathAddSubscreen;
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public byte ColorMathEnabled;
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[MarshalAs(UnmanagedType.I1)] public bool ColorMathSubtractMode;
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[MarshalAs(UnmanagedType.I1)] public bool ColorMathHalveResult;
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public UInt16 FixedColor;
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}
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public struct LayerConfig
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{
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public UInt16 TilemapAddress;
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public UInt16 ChrAddress;
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public UInt16 HScroll;
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public UInt16 VScroll;
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[MarshalAs(UnmanagedType.I1)] public bool DoubleWidth;
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[MarshalAs(UnmanagedType.I1)] public bool DoubleHeight;
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[MarshalAs(UnmanagedType.I1)] public bool LargeTiles;
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}
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public struct WindowConfig
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{
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 6)]
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public byte[] ActiveLayers;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 6)]
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public byte[] InvertedLayers;
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public Byte Left;
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public Byte Right;
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}
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public struct Mode7Config
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{
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
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public Int16[] Matrix;
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public Int16 HScroll;
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public Int16 VScroll;
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public Int16 CenterX;
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public Int16 CenterY;
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public Byte ValueLatch;
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[MarshalAs(UnmanagedType.I1)] public bool LargeMap;
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[MarshalAs(UnmanagedType.I1)] public bool FillWithTile0;
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[MarshalAs(UnmanagedType.I1)] public bool HorizontalMirroring;
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[MarshalAs(UnmanagedType.I1)] public bool VerticalMirroring;
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public Int16 HScrollLatch;
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public Int16 VScrollLatch;
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}
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public enum WindowMaskLogic
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{
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Or = 0,
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And = 1,
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Xor = 2,
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Xnor = 3
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}
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public enum ColorWindowMode
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{
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Never = 0,
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OutsideWindow = 1,
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InsideWindow = 2,
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Always = 3
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}
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public struct SpcTimer
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{
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[MarshalAs(UnmanagedType.I1)] public bool Enabled;
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[MarshalAs(UnmanagedType.I1)] public bool TimersEnabled;
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public byte Output;
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public byte Stage0;
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public byte Stage1;
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public byte PrevStage1;
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public byte Stage2;
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public byte Target;
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}
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public struct SpcState : BaseState
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{
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public UInt64 Cycle;
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public UInt16 PC;
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public byte A;
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public byte X;
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public byte Y;
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public byte SP;
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public SpcFlags PS;
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[MarshalAs(UnmanagedType.I1)] public bool WriteEnabled;
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[MarshalAs(UnmanagedType.I1)] public bool RomEnabled;
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public byte InternalSpeed;
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public byte ExternalSpeed;
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[MarshalAs(UnmanagedType.I1)] public bool TimersEnabled;
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[MarshalAs(UnmanagedType.I1)] public bool TimersDisabled;
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public SnesCpuStopState StopState;
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public byte DspReg;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
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public byte[] OutputReg;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public byte[] RamReg;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
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public byte[] CpuRegs;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
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public byte[] NewCpuRegs;
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public SpcTimer Timer0;
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public SpcTimer Timer1;
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public SpcTimer Timer2;
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}
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public struct DspState
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{
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 128)]
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public byte[] ExternalRegs;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 128)]
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public byte[] Regs;
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public Int32 NoiseLfsr;
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public UInt16 Counter;
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public byte Step;
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public byte OutRegBuffer;
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public byte EnvRegBuffer;
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public byte VoiceEndBuffer;
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public Int32 VoiceOutput;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public Int32[] OutSamples;
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public Int32 Pitch;
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public UInt16 SampleAddress;
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public UInt16 BrrNextAddress;
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public byte DirSampleTableAddress;
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public byte NoiseOn;
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public byte PitchModulationOn;
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public byte KeyOn;
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public byte NewKeyOn;
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public byte KeyOff;
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public byte EveryOtherSample;
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public byte SourceNumber;
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public byte BrrHeader;
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public byte BrrData;
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public byte Looped;
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public byte Adsr1;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public Int32[] EchoIn;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public Int32[] EchoOut;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8 * 2)]
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public UInt16[] EchoHistory;
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public UInt16 EchoPointer;
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public UInt16 EchoLength;
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public UInt16 EchoOffset;
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public byte EchoHistoryPos;
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public byte EchoRingBufferAddress;
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public byte EchoOn;
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[MarshalAs(UnmanagedType.I1)] public bool EchoEnabled;
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}
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public struct NecDspAccFlags
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{
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[MarshalAs(UnmanagedType.I1)] public bool Carry;
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[MarshalAs(UnmanagedType.I1)] public bool Zero;
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[MarshalAs(UnmanagedType.I1)] public bool Overflow0;
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[MarshalAs(UnmanagedType.I1)] public bool Overflow1;
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[MarshalAs(UnmanagedType.I1)] public bool Sign0;
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[MarshalAs(UnmanagedType.I1)] public bool Sign1;
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}
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public struct NecDspState : BaseState
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{
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public UInt64 CycleCount;
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public UInt16 A;
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public NecDspAccFlags FlagsA;
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public UInt16 B;
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public NecDspAccFlags FlagsB;
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public UInt16 TR;
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public UInt16 TRB;
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public UInt16 PC;
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public UInt16 RP;
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public UInt16 DP;
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public UInt16 DR;
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public UInt16 SR;
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public UInt16 K;
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public UInt16 L;
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public UInt16 M;
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public UInt16 N;
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public UInt16 SerialOut;
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public UInt16 SerialIn;
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public byte SP;
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}
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public enum ArmV3CpuMode : byte
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{
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User = 0b10000,
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Fiq = 0b10001,
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Irq = 0b10010,
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Supervisor = 0b10011,
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Abort = 0b10111,
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Undefined = 0b11011,
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System = 0b11111,
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}
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public struct ArmV3CpuFlags
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{
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public ArmV3CpuMode Mode;
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[MarshalAs(UnmanagedType.I1)] public bool FiqDisable;
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[MarshalAs(UnmanagedType.I1)] public bool IrqDisable;
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[MarshalAs(UnmanagedType.I1)] public bool Overflow;
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[MarshalAs(UnmanagedType.I1)] public bool Carry;
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[MarshalAs(UnmanagedType.I1)] public bool Zero;
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[MarshalAs(UnmanagedType.I1)] public bool Negative;
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}
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public struct ArmV3InstructionData
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{
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public UInt32 Address;
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public UInt32 OpCode;
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}
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public struct ArmV3CpuPipeline
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{
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public ArmV3InstructionData Fetch;
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public ArmV3InstructionData Decode;
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public ArmV3InstructionData Execute;
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[MarshalAs(UnmanagedType.I1)] public bool ReloadRequested;
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public byte Mode;
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}
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public struct ArmV3CpuState : BaseState
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{
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public ArmV3CpuPipeline Pipeline;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 16)]
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public UInt32[] R;
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public ArmV3CpuFlags CPSR;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 7)]
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public UInt32[] UserRegs;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 7)]
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public UInt32[] FiqRegs;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public UInt32[] IrqRegs;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public UInt32[] SupervisorRegs;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public UInt32[] AbortRegs;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public UInt32[] UndefinedRegs;
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public ArmV3CpuFlags FiqSpsr;
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public ArmV3CpuFlags IrqSpsr;
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public ArmV3CpuFlags SupervisorSpsr;
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public ArmV3CpuFlags AbortSpsr;
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public ArmV3CpuFlags UndefinedSpsr;
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public UInt64 CycleCount;
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}
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public struct St018State : BaseState
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{
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[MarshalAs(UnmanagedType.I1)] public bool HasDataForSnes;
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public byte DataSnes;
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[MarshalAs(UnmanagedType.I1)] public bool HasDataForArm;
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public byte DataArm;
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[MarshalAs(UnmanagedType.I1)] public bool ArmReset;
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[MarshalAs(UnmanagedType.I1)] public bool Ack;
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}
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public struct GsuFlags
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{
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[MarshalAs(UnmanagedType.I1)] public bool Zero;
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[MarshalAs(UnmanagedType.I1)] public bool Carry;
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[MarshalAs(UnmanagedType.I1)] public bool Sign;
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[MarshalAs(UnmanagedType.I1)] public bool Overflow;
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[MarshalAs(UnmanagedType.I1)] public bool Running;
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[MarshalAs(UnmanagedType.I1)] public bool RomReadPending;
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[MarshalAs(UnmanagedType.I1)] public bool Alt1;
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[MarshalAs(UnmanagedType.I1)] public bool Alt2;
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[MarshalAs(UnmanagedType.I1)] public bool ImmLow;
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[MarshalAs(UnmanagedType.I1)] public bool ImmHigh;
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[MarshalAs(UnmanagedType.I1)] public bool Prefix;
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[MarshalAs(UnmanagedType.I1)] public bool Irq;
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}
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public struct GsuPixelCache
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{
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public byte X;
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public byte Y;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
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public byte[] Pixels;
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public byte ValidBits;
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}
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public struct GsuState : BaseState
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{
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public UInt64 CycleCount;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 16)]
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public UInt16[] R;
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public GsuFlags SFR;
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public byte RegisterLatch;
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public byte ProgramBank;
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public byte RomBank;
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public byte RamBank;
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[MarshalAs(UnmanagedType.I1)] public bool IrqDisabled;
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[MarshalAs(UnmanagedType.I1)] public bool HighSpeedMode;
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[MarshalAs(UnmanagedType.I1)] public bool ClockSelect;
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[MarshalAs(UnmanagedType.I1)] public bool BackupRamEnabled;
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public byte ScreenBase;
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public byte ColorGradient;
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public byte PlotBpp;
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public byte ScreenHeight;
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[MarshalAs(UnmanagedType.I1)] public bool GsuRamAccess;
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[MarshalAs(UnmanagedType.I1)] public bool GsuRomAccess;
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public UInt16 CacheBase;
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[MarshalAs(UnmanagedType.I1)] public bool PlotTransparent;
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[MarshalAs(UnmanagedType.I1)] public bool PlotDither;
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[MarshalAs(UnmanagedType.I1)] public bool ColorHighNibble;
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[MarshalAs(UnmanagedType.I1)] public bool ColorFreezeHigh;
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[MarshalAs(UnmanagedType.I1)] public bool ObjMode;
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public byte ColorReg;
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public byte SrcReg;
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public byte DestReg;
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public byte RomReadBuffer;
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public byte RomDelay;
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public byte ProgramReadBuffer;
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public UInt16 RamWriteAddress;
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public byte RamWriteValue;
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public byte RamDelay;
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public UInt16 RamAddress;
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public GsuPixelCache PrimaryCache;
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public GsuPixelCache SecondaryCache;
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}
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public struct Cx4Dma
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{
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public UInt32 Source;
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public UInt32 Dest;
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public UInt16 Length;
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public UInt32 Pos;
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[MarshalAs(UnmanagedType.I1)] public bool Enabled;
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}
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public struct Cx4Suspend
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{
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public UInt32 Duration;
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[MarshalAs(UnmanagedType.I1)] public bool Enabled;
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}
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public struct Cx4Cache
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{
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[MarshalAs(UnmanagedType.I1)] public bool Enabled;
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public byte Page;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public byte[] Lock;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 2)]
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public UInt32[] Address;
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public UInt32 Base;
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public UInt16 ProgramBank;
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public byte ProgramCounter;
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public UInt16 Pos;
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}
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public struct Cx4Bus
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{
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[MarshalAs(UnmanagedType.I1)] public bool Enabled;
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[MarshalAs(UnmanagedType.I1)] public bool Reading;
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[MarshalAs(UnmanagedType.I1)] public bool Writing;
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public byte DelayCycles;
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public UInt32 Address;
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}
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public struct Cx4State : BaseState
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{
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public UInt64 CycleCount;
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public UInt16 PB;
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public byte PC;
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public UInt32 A;
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public UInt16 P;
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public byte SP;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
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public UInt32[] Stack;
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public UInt64 Mult;
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public UInt32 RomBuffer;
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[MarshalAs(UnmanagedType.ByValArray, SizeConst = 3)]
|
|
public byte[] RamBuffer;
|
|
|
|
public UInt32 MemoryDataReg;
|
|
public UInt32 MemoryAddressReg;
|
|
public UInt32 DataPointerReg;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 16)]
|
|
public UInt32[] Regs;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool Negative;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Zero;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Carry;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Overflow;
|
|
[MarshalAs(UnmanagedType.I1)] public bool IrqFlag;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool Stopped;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Locked;
|
|
[MarshalAs(UnmanagedType.I1)] public bool IrqDisabled;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool SingleRom;
|
|
|
|
public byte RomAccessDelay;
|
|
public byte RamAccessDelay;
|
|
|
|
public Cx4Bus Bus;
|
|
public Cx4Dma Dma;
|
|
public Cx4Cache Cache;
|
|
public Cx4Suspend Suspend;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 0x20)]
|
|
public byte[] Vectors;
|
|
}
|
|
|
|
public struct Sa1State
|
|
{
|
|
public UInt16 Sa1ResetVector;
|
|
public UInt16 Sa1IrqVector;
|
|
public UInt16 Sa1NmiVector;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool Sa1IrqRequested;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Sa1IrqEnabled;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool Sa1NmiRequested;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Sa1NmiEnabled;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Sa1Wait;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Sa1Reset;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool DmaIrqEnabled;
|
|
[MarshalAs(UnmanagedType.I1)] public bool TimerIrqEnabled;
|
|
|
|
public byte Sa1MessageReceived;
|
|
public byte CpuMessageReceived;
|
|
|
|
public UInt16 CpuIrqVector;
|
|
public UInt16 CpuNmiVector;
|
|
[MarshalAs(UnmanagedType.I1)] public bool UseCpuIrqVector;
|
|
[MarshalAs(UnmanagedType.I1)] public bool UseCpuNmiVector;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool CpuIrqRequested;
|
|
[MarshalAs(UnmanagedType.I1)] public bool CpuIrqEnabled;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool CharConvIrqFlag;
|
|
[MarshalAs(UnmanagedType.I1)] public bool CharConvIrqEnabled;
|
|
[MarshalAs(UnmanagedType.I1)] public bool CharConvDmaActive;
|
|
public byte CharConvBpp;
|
|
public byte CharConvFormat;
|
|
public byte CharConvWidth;
|
|
public byte CharConvCounter;
|
|
|
|
public byte CpuBwBank;
|
|
[MarshalAs(UnmanagedType.I1)] public bool CpuBwWriteEnabled;
|
|
|
|
public byte Sa1BwBank;
|
|
public byte Sa1BwMode;
|
|
[MarshalAs(UnmanagedType.I1)] public bool Sa1BwWriteEnabled;
|
|
public byte BwWriteProtectedArea;
|
|
[MarshalAs(UnmanagedType.I1)] public bool BwRam2BppMode;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
|
|
public byte[] BitmapRegister1;
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
|
|
public byte[] BitmapRegister2;
|
|
|
|
public byte CpuIRamWriteProtect;
|
|
public byte Sa1IRamWriteProtect;
|
|
|
|
public UInt32 DmaSrcAddr;
|
|
public UInt32 DmaDestAddr;
|
|
public UInt16 DmaSize;
|
|
[MarshalAs(UnmanagedType.I1)] public bool DmaEnabled;
|
|
[MarshalAs(UnmanagedType.I1)] public bool DmaPriority;
|
|
[MarshalAs(UnmanagedType.I1)] public bool DmaCharConv;
|
|
[MarshalAs(UnmanagedType.I1)] public bool DmaCharConvAuto;
|
|
public Sa1DmaDestDevice DmaDestDevice;
|
|
public Sa1DmaSrcDevice DmaSrcDevice;
|
|
[MarshalAs(UnmanagedType.I1)] public bool DmaRunning;
|
|
[MarshalAs(UnmanagedType.I1)] public bool DmaIrqFlag;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool HorizontalTimerEnabled;
|
|
[MarshalAs(UnmanagedType.I1)] public bool VerticalTimerEnabled;
|
|
[MarshalAs(UnmanagedType.I1)] public bool UseLinearTimer;
|
|
|
|
public UInt16 HTimer;
|
|
public UInt16 VTimer;
|
|
public UInt32 LinearTimerValue;
|
|
|
|
public Sa1MathOp MathOp;
|
|
public UInt16 MultiplicandDividend;
|
|
public UInt16 MultiplierDivisor;
|
|
public UInt64 MathOpResult;
|
|
public byte MathOverflow;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool VarLenAutoInc;
|
|
public byte VarLenBitCount;
|
|
public UInt32 VarLenAddress;
|
|
public byte VarLenCurrentBit;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
|
|
public byte[] Banks;
|
|
}
|
|
|
|
public enum Sa1MathOp
|
|
{
|
|
Mul = 0,
|
|
Div = 1,
|
|
Sum = 2
|
|
}
|
|
|
|
public enum Sa1DmaSrcDevice
|
|
{
|
|
PrgRom = 0,
|
|
BwRam = 1,
|
|
InternalRam = 2,
|
|
Reserved = 3
|
|
}
|
|
|
|
public enum Sa1DmaDestDevice
|
|
{
|
|
InternalRam = 0,
|
|
BwRam = 1
|
|
}
|
|
|
|
public struct AluState
|
|
{
|
|
public byte MultOperand1;
|
|
public byte MultOperand2;
|
|
public UInt16 MultOrRemainderResult;
|
|
|
|
public UInt16 Dividend;
|
|
public byte Divisor;
|
|
public UInt16 DivResult;
|
|
}
|
|
|
|
public struct InternalRegisterState
|
|
{
|
|
[MarshalAs(UnmanagedType.I1)] public bool EnableAutoJoypadRead;
|
|
[MarshalAs(UnmanagedType.I1)] public bool EnableFastRom;
|
|
|
|
[MarshalAs(UnmanagedType.I1)] public bool EnableNmi;
|
|
[MarshalAs(UnmanagedType.I1)] public bool EnableHorizontalIrq;
|
|
[MarshalAs(UnmanagedType.I1)] public bool EnableVerticalIrq;
|
|
public UInt16 HorizontalTimer;
|
|
public UInt16 VerticalTimer;
|
|
|
|
public byte IoPortOutput;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
|
|
public UInt16[] ControllerData;
|
|
}
|
|
|
|
public struct SnesDmaControllerState
|
|
{
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
|
|
public DmaChannelConfig[] Channels;
|
|
|
|
public byte HdmaChannels;
|
|
}
|
|
|
|
public struct SnesState : BaseState
|
|
{
|
|
public UInt64 MasterClock;
|
|
public SnesCpuState Cpu;
|
|
public SnesPpuState Ppu;
|
|
public SpcState Spc;
|
|
public DspState Dsp;
|
|
public NecDspState NecDsp;
|
|
public Sa1State Sa1;
|
|
public GsuState Gsu;
|
|
public Cx4State Cx4;
|
|
public St018State St018;
|
|
|
|
public SnesDmaControllerState Dma;
|
|
public InternalRegisterState InternalRegs;
|
|
public AluState Alu;
|
|
|
|
public UInt32 WramPosition;
|
|
}
|
|
|
|
public struct SnesPpuToolsState : BaseState
|
|
{
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 239)]
|
|
public byte[] ScanlineBgMode;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 239)]
|
|
public Int32[] Mode7StartX;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 239)]
|
|
public Int32[] Mode7StartY;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 239)]
|
|
public Int32[] Mode7EndX;
|
|
|
|
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 239)]
|
|
public Int32[] Mode7EndY;
|
|
} |