mirror of
https://github.com/SourMesen/Mesen2.git
synced 2025-04-02 10:21:44 -04:00
333 lines
7.3 KiB
C++
333 lines
7.3 KiB
C++
#include "pch.h"
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#include "SNES/SnesConsole.h"
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#include "SNES/SnesMemoryManager.h"
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#include "SNES/MemoryMappings.h"
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#include "SNES/Coprocessors/ST018/St018.h"
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#include "SNES/Coprocessors/ST018/ArmV3Cpu.h"
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#include "SNES/Coprocessors/ST018/ArmV3Types.h"
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#include "SNES/Debugger/DummyArmV3Cpu.h"
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#include "Shared/Emulator.h"
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#include "Shared/FirmwareHelper.h"
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#include "GBA/GbaCpu.h"
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St018::St018(SnesConsole* console)
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{
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_emu = console->GetEmulator();
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_console = console;
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_memoryManager = console->GetMemoryManager();
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_memoryManager->GetMemoryMappings()->RegisterHandler(0x00, 0x3F, 0x3000, 0x3FFF, this);
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_memoryManager->GetMemoryMappings()->RegisterHandler(0x80, 0xBF, 0x3000, 0x3FFF, this);
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ArmV3Cpu::StaticInit();
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DummyArmV3Cpu::StaticInit();
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GbaCpu::StaticInit(); //todo remove
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_prgRom = new uint8_t[St018::PrgRomSize];
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_dataRom = new uint8_t[St018::DataRomSize];
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_workRam = new uint8_t[St018::WorkRamSize];
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_console->InitializeRam(_workRam, St018::WorkRamSize);
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vector<uint8_t> firmwareData;
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FirmwareHelper::LoadSt018Firmware(_emu, firmwareData);
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if(firmwareData.size() == 0x28000) {
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memcpy(_prgRom, firmwareData.data(), St018::PrgRomSize);
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memcpy(_dataRom, firmwareData.data() + St018::PrgRomSize, St018::DataRomSize);
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}
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_emu->RegisterMemory(MemoryType::St018PrgRom, _prgRom, St018::PrgRomSize);
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_emu->RegisterMemory(MemoryType::St018DataRom, _dataRom, St018::DataRomSize);
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_emu->RegisterMemory(MemoryType::St018WorkRam, _workRam, St018::WorkRamSize);
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_cpu.reset(new ArmV3Cpu());
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_cpu->Init(_emu, this);
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_cpu->PowerOn(false);
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}
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St018::~St018()
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{
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delete[] _prgRom;
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delete[] _dataRom;
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delete[] _workRam;
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}
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void St018::Reset()
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{
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}
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void St018::Run()
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{
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ArmV3CpuState& state = _cpu->GetState();
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uint64_t targetCycle = _memoryManager->GetMasterClock();
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if(_state.ArmReset) {
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state.CycleCount = targetCycle;
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}
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while(state.CycleCount < targetCycle) {
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_cpu->Exec();
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}
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}
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void St018::ProcessEndOfFrame()
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{
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Run();
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}
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uint8_t St018::Read(uint32_t addr)
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{
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Run();
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switch(addr & 0xFF06) {
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case 0x3800:
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_state.HasDataForSnes = false;
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return _state.DataSnes;
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case 0x3802:
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_state.Ack = false;
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break;
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case 0x3804:
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return GetStatus();
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}
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return _memoryManager->GetOpenBus();
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}
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uint8_t St018::Peek(uint32_t addr)
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{
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switch(addr & 0xFF06) {
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case 0x3800: return _state.DataSnes;
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case 0x3802: break;
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case 0x3804: return GetStatus();
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}
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return _memoryManager->GetOpenBus();
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}
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void St018::PeekBlock(uint32_t addr, uint8_t* output)
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{
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for(int i = 0; i < 0x1000; i++) {
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output[i] = Peek(i);
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}
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}
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void St018::Write(uint32_t addr, uint8_t value)
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{
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Run();
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switch(addr & 0xFF06) {
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case 0x3802:
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_state.DataArm = value;
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_state.HasDataForArm = true;
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break;
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case 0x3804:
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if(_state.ArmReset && !value) {
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_cpu->PowerOn(true);
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}
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_state.ArmReset = value != 0;
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break;
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}
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}
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AddressInfo St018::GetAbsoluteAddress(uint32_t address)
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{
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return { -1, MemoryType::None };
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}
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AddressInfo St018::GetArmAbsoluteAddress(uint32_t addr)
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{
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switch(addr >> 28) {
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case 0x00: return { (int)(addr & 0x1FFFF), MemoryType::St018PrgRom };
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case 0x0A: return { (int)(addr & 0x7FFF), MemoryType::St018DataRom};
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case 0x0E: return { (int)(addr & 0x3FFF), MemoryType::St018WorkRam };
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}
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return { -1, MemoryType::None };
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}
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int St018::GetArmRelativeAddress(AddressInfo& absoluteAddr)
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{
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switch(absoluteAddr.Type) {
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case MemoryType::St018PrgRom: return absoluteAddr.Address;
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case MemoryType::St018DataRom: return 0xA0000000 | absoluteAddr.Address;
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case MemoryType::St018WorkRam: return 0xE0000000 | absoluteAddr.Address;
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}
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return -1;
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}
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void St018::LoadBattery()
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{
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}
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void St018::SaveBattery()
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{
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}
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St018State& St018::GetState()
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{
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return _state;
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}
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uint32_t St018::ReadCpu(ArmV3AccessModeVal mode, uint32_t addr)
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{
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_cpu->GetState().CycleCount++;
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uint32_t value;
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if(mode & ArmV3AccessMode::Word) {
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uint8_t b0 = ReadCpuByte(addr & ~0x03);
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uint8_t b1 = ReadCpuByte((addr & ~0x03) | 1);
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uint8_t b2 = ReadCpuByte((addr & ~0x03) | 2);
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uint8_t b3 = ReadCpuByte(addr | 3);
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value = b0 | (b1 << 8) | (b2 << 16) | (b3 << 24);
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_emu->ProcessMemoryRead<CpuType::St018, 4>(addr & ~0x03, value, mode & ArmV3AccessMode::Prefetch ? MemoryOperationType::ExecOpCode : MemoryOperationType::Read);
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} else {
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value = ReadCpuByte(addr);
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_emu->ProcessMemoryRead<CpuType::St018, 1>(addr, value, MemoryOperationType::Read);
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}
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return value;
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}
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uint8_t St018::ReadCpuByte(uint32_t addr)
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{
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switch(addr >> 28) {
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case 0x00: return _prgRom[addr & 0x1FFFF];
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case 0x02: return 0;
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case 0x04:
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switch(addr & 0x3F) {
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case 0x10:
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_state.HasDataForArm = false;
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return _state.DataArm;
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case 0x20: return GetStatus();
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}
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return 0;
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case 0x06: return 0;
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case 0x08: return 0;
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case 0x0A: return _dataRom[addr & 0x7FFF];
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case 0x0C: return 0;
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case 0x0E: return _workRam[addr & 0x3FFF];
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}
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return 0;
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}
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uint32_t St018::DebugCpuRead(ArmV3AccessModeVal mode, uint32_t addr)
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{
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if(mode & ArmV3AccessMode::Byte) {
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return DebugRead(addr);
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} else {
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uint8_t b0 = DebugRead(addr & ~0x03);
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uint8_t b1 = DebugRead((addr & ~0x03) | 1);
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uint8_t b2 = DebugRead((addr & ~0x03) | 2);
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uint8_t b3 = DebugRead(addr | 3);
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return b0 | (b1 << 8) | (b2 << 16) | (b3 << 24);
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}
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}
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uint8_t St018::DebugRead(uint32_t addr)
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{
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switch(addr >> 28) {
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case 0x00: return _prgRom[addr & 0x1FFFF];
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case 0x02: return 0;
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case 0x04: return 0;
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case 0x06: return 0;
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case 0x08: return 0;
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case 0x0A: return _dataRom[addr & 0x7FFF];
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case 0x0C: return 0;
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case 0x0E: return _workRam[addr & 0x3FFF];
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}
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return 0;
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}
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void St018::DebugWrite(uint32_t addr, uint8_t value)
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{
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switch(addr >> 28) {
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case 0x00: _prgRom[addr & 0x1FFFF] = value; break;
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case 0x0A: _dataRom[addr & 0x7FFF] = value; break;
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case 0x0E: _workRam[addr & 0x3FFF] = value; break;
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}
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}
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void St018::WriteCpu(ArmV3AccessModeVal mode, uint32_t addr, uint32_t value)
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{
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_cpu->GetState().CycleCount++;
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if(mode & ArmV3AccessMode::Word) {
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if(_emu->ProcessMemoryWrite<CpuType::St018, 4>(addr & ~0x03, value, MemoryOperationType::Write)) {
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WriteCpuByte((addr & ~0x03), (uint8_t)value);
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WriteCpuByte((addr & ~0x03) | 0x01, (uint8_t)(value >> 8));
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WriteCpuByte((addr & ~0x03) | 0x02, (uint8_t)(value >> 16));
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WriteCpuByte((addr & ~0x03) | 0x03, (uint8_t)(value >> 24));
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}
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} else {
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if(_emu->ProcessMemoryWrite<CpuType::St018, 1>(addr, value, MemoryOperationType::Write)) {
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WriteCpuByte(addr, value);
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}
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}
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}
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void St018::WriteCpuByte(uint32_t addr, uint8_t value)
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{
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switch(addr >> 28) {
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case 0x00: break;
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case 0x02: break;
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case 0x04:
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switch(addr & 0x3F) {
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case 0x00:
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_state.HasDataForSnes = true;
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_state.DataSnes = value;
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break;
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case 0x10:
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_state.Ack = true;
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break;
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case 0x20:
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case 0x24:
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case 0x28:
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case 0x2A:
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//??
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break;
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}
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break;
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case 0x06: break;
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case 0x08: break;
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case 0x0A: break;
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case 0x0C: break;
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case 0x0E: _workRam[addr & 0x3FFF] = value; break;
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}
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}
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void St018::ProcessIdleCycle()
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{
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_cpu->GetState().CycleCount++;
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}
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uint8_t St018::GetStatus()
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{
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return (
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(_state.HasDataForSnes ? 0x01 : 0) |
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(_state.Ack ? 0x04 : 0) |
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(_state.HasDataForArm ? 0x08 : 0) |
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(!_state.ArmReset ? 0x80 : 0)
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);
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}
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void St018::Serialize(Serializer& s)
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{
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SV(_state.Ack);
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SV(_state.ArmReset);
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SV(_state.DataArm);
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SV(_state.DataSnes);
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SV(_state.HasDataForArm);
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SV(_state.HasDataForSnes);
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SV(_cpu);
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}
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