mirror of
https://github.com/SourMesen/Mesen2.git
synced 2025-04-02 10:21:44 -04:00
SNES: Fixed NMI/IRQ timing issues
Passes all NMI/IRQ tests: demo_irqtest, demo_nmitest, irq, nmi, test_irq, test_irq4200, test_irq4209, test_irqb, test_nmi, Also fixes timing issues with WAI
This commit is contained in:
Sour
parent
831e177d87
commit
59f106b8cc
16 changed files with 179 additions and 89 deletions
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@ -52,7 +52,7 @@ int64_t ExpressionEvaluator::GetSnesTokenValue(int64_t token, EvalResultType& re
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case EvalValues::RegDB: return s.DBR;
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case EvalValues::RegD: return s.D;
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case EvalValues::RegPC: return (s.K << 16) | s.PC;
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case EvalValues::Nmi: return ReturnBool(s.NmiFlag, resultType);
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case EvalValues::Nmi: return ReturnBool(s.NmiFlagCounter > 0 || s.NeedNmi, resultType);
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case EvalValues::Irq: return ReturnBool(s.IrqSource, resultType);
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case EvalValues::PpuFrameCount: return getPpuState().FrameCount;
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case EvalValues::PpuCycle: return getPpuState().Cycle;
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@ -430,7 +430,9 @@ void Sa1::ProcessInterrupts()
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_cpu->ClearIrqSource(SnesIrqSource::Coprocessor);
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}
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_cpu->SetNmiFlag(_state.Sa1NmiRequested && _state.Sa1NmiEnabled);
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if(_state.Sa1NmiRequested && _state.Sa1NmiEnabled) {
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_cpu->SetNmiFlag(1);
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}
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if((_state.CpuIrqRequested && _state.CpuIrqEnabled) || (_state.CharConvIrqFlag && _state.CharConvIrqEnabled)) {
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_snesCpu->SetIrqSource(SnesIrqSource::Coprocessor);
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@ -41,7 +41,7 @@ void Sa1Cpu::Exec()
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void Sa1Cpu::CheckForInterrupts()
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{
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//Use the state of the IRQ/NMI flags on the previous cycle to determine if an IRQ is processed or not
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if(_state.PrevNeedNmi) {
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if(_state.NeedNmi) {
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_state.NeedNmi = false;
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uint32_t originalPc = GetProgramAddress(_state.PC);
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ProcessInterrupt(_state.EmulationMode ? Sa1Cpu::LegacyNmiVector : Sa1Cpu::NmiVector, true);
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@ -60,10 +60,9 @@ void Sa1Cpu::ProcessHaltedState()
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_state.CycleCount++;
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} else {
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//WAI
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bool over = _waiOver;
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Idle();
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if(_state.IrqSource || _state.NeedNmi) {
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Idle();
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Idle();
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if(over) {
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_state.StopState = SnesCpuStopState::Running;
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CheckForInterrupts();
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}
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@ -75,7 +74,6 @@ void Sa1Cpu::Idle()
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//Do not apply any delay to internal cycles: "internal SA-1 cycles are still 10.74 MHz."
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_state.CycleCount++;
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DetectNmiSignalEdge();
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UpdateIrqNmiFlags();
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_emu->ProcessIdleCycle<CpuType::Sa1>();
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}
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@ -89,7 +87,6 @@ void Sa1Cpu::IdleOrDummyWrite(uint32_t addr, uint8_t value)
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}
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DetectNmiSignalEdge();
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UpdateIrqNmiFlags();
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}
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void Sa1Cpu::IdleEndJump()
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@ -150,7 +147,6 @@ void Sa1Cpu::ProcessCpuCycle(uint32_t addr)
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}
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DetectNmiSignalEdge();
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UpdateIrqNmiFlags();
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}
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uint8_t Sa1Cpu::Read(uint32_t addr, MemoryOperationType type)
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@ -31,6 +31,7 @@ private:
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SnesCpuState _state = {};
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uint32_t _operand = 0;
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bool _waiOver = true;
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uint32_t GetProgramAddress(uint16_t addr);
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uint32_t GetDataAddress(uint16_t addr);
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@ -55,7 +56,6 @@ private:
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void IdleTakeBranch();
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void DetectNmiSignalEdge();
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void UpdateIrqNmiFlags();
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bool IsAccessConflict();
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@ -335,7 +335,7 @@ public:
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template<uint64_t value>
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void IncreaseCycleCount();
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void SetNmiFlag(bool nmiFlag);
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void SetNmiFlag(uint8_t delay);
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void SetIrqSource(SnesIrqSource source);
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bool CheckIrqSource(SnesIrqSource source);
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void ClearIrqSource(SnesIrqSource source);
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@ -62,7 +62,7 @@ void InternalRegisters::ProcessAutoJoypad()
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{
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//Some details/timings may still be incorrect
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//This is based on these test roms: https://github.com/undisbeliever/snes-test-roms/blob/master/src/hardware-tests/
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//As well as the CPU schematics here: https://github.com/rgalland/SNES_S-CPU_Schematics/
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//See CPU schematics here: https://github.com/rgalland/SNES_S-CPU_Schematics/
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uint64_t masterClock = _console->GetMasterClock();
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if(masterClock < _autoReadClockStart) {
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return;
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@ -180,9 +180,7 @@ void InternalRegisters::SetNmiFlag(bool nmiFlag)
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void InternalRegisters::SetIrqFlag(bool irqFlag)
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{
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_irqFlag = irqFlag && (_state.EnableHorizontalIrq || _state.EnableVerticalIrq);
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if(_irqFlag) {
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_cpu->SetIrqSource(SnesIrqSource::Ppu);
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} else {
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if(!_irqFlag) {
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_cpu->ClearIrqSource(SnesIrqSource::Ppu);
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}
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}
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@ -233,10 +231,12 @@ uint8_t InternalRegisters::Read(uint16_t addr)
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uint8_t value = (_nmiFlag ? 0x80 : 0) | cpuRevision;
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//Reading $4210 on any cycle turns the NMI signal off (except presumably on the first PPU cycle (first 4 master clocks) of the NMI scanline.)
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//Reading $4210 on any cycle clears the NMI flag,
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//Except between from cycles 2 to 5 on the NMI scanline, because the CPU forces the
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//flag to remain set for 4 cycles, only allowing it to be cleared starting on cycle 6
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//i.e: reading $4210 at the same it gets set will return it as set, and will keep it set.
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//Without this, Terranigma has corrupted sprites on some frames.
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if(_memoryManager->GetHClock() >= 4 || _ppu->GetScanline() != _ppu->GetNmiScanline()) {
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if(_nmiFlag && (_memoryManager->GetHClock() >= 6 || _ppu->GetScanline() != _ppu->GetNmiScanline())) {
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SetNmiFlag(false);
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}
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@ -245,7 +245,11 @@ uint8_t InternalRegisters::Read(uint16_t addr)
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case 0x4211: {
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uint8_t value = (_irqFlag ? 0x80 : 0);
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SetIrqFlag(false);
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if(_irqFlag && !_needIrq) {
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//Clear IRQ flag, if it wasn't just set within the last 4 cycles
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//Same as the NMI flag, the CPU forces the IRQ flag to be set for at least 4 cycles
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SetIrqFlag(false);
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}
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return value | (_memoryManager->GetOpenBus() & 0x7F);
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}
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@ -305,13 +309,22 @@ void InternalRegisters::Write(uint16_t addr, uint8_t value)
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}
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}
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_state.EnableNmi = (value & 0x80) != 0;
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_state.EnableVerticalIrq = (value & 0x20) != 0;
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_state.EnableHorizontalIrq = (value & 0x10) != 0;
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_state.EnableAutoJoypadRead = autoRead;
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_irqEnabled = _state.EnableHorizontalIrq || _state.EnableVerticalIrq;
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SetNmiFlag(_nmiFlag);
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SetIrqFlag(_irqFlag);
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bool enableNmi = (value & 0x80) != 0;
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if(_nmiFlag && enableNmi && !_state.EnableNmi) {
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//When enabling NMIs in the middle of vblank, trigger an NMI right away
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_cpu->SetNmiFlag(2);
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}
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_state.EnableNmi = enableNmi;
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if(!_irqEnabled) {
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//Clearing both H+V irq enabled flags will immediately clear the IRQ flag
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SetIrqFlag(false);
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}
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break;
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}
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@ -338,12 +351,12 @@ void InternalRegisters::Write(uint16_t addr, uint8_t value)
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case 0x4207:
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_state.HorizontalTimer = (_state.HorizontalTimer & 0x100) | value;
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ProcessIrqCounters();
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UpdateIrqLevel();
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break;
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case 0x4208:
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_state.HorizontalTimer = (_state.HorizontalTimer & 0xFF) | ((value & 0x01) << 8);
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ProcessIrqCounters();
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UpdateIrqLevel();
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break;
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case 0x4209:
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@ -352,12 +365,12 @@ void InternalRegisters::Write(uint16_t addr, uint8_t value)
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//Calling this here fixes flashing issue in "Shin Nihon Pro Wrestling Kounin - '95 Tokyo Dome Battle 7"
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//The write to change from scanline 16 to 17 occurs between both ProcessIrqCounter calls, which causes the IRQ
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//line to always be high (since the previous check is on scanline 16, and the next check on scanline 17)
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ProcessIrqCounters();
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UpdateIrqLevel();
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break;
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case 0x420A:
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_state.VerticalTimer = (_state.VerticalTimer & 0xFF) | ((value & 0x01) << 8);
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ProcessIrqCounters();
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UpdateIrqLevel();
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break;
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case 0x420D: _state.EnableFastRom = (value & 0x01) != 0; break;
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@ -378,7 +391,7 @@ AluState InternalRegisters::GetAluState()
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return _aluMulDiv.GetState();
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}
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void InternalRegisters::Serialize(Serializer &s)
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void InternalRegisters::Serialize(Serializer& s)
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{
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SV(_state.EnableFastRom); SV(_nmiFlag); SV(_state.EnableNmi); SV(_state.EnableHorizontalIrq); SV(_state.EnableVerticalIrq); SV(_state.HorizontalTimer);
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SV(_state.VerticalTimer); SV(_state.IoPortOutput); SV(_state.ControllerData[0]); SV(_state.ControllerData[1]); SV(_state.ControllerData[2]); SV(_state.ControllerData[3]);
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@ -392,4 +405,8 @@ void InternalRegisters::Serialize(Serializer &s)
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SV(_autoReadDisabled);
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SV(_autoReadPort1Value);
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SV(_autoReadPort2Value);
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SV(_hCounter);
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SV(_vCounter);
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SV(_irqEnabled);
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}
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@ -3,6 +3,7 @@
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#include "SNES/AluMulDiv.h"
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#include "SNES/SnesCpu.h"
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#include "SNES/SnesPpu.h"
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#include "SNES/SnesMemoryManager.h"
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#include "SNES/InternalRegisterTypes.h"
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#include "Utilities/ISerializable.h"
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@ -26,6 +27,10 @@ private:
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bool _irqLevel = false;
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uint8_t _needIrq = 0;
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bool _irqFlag = false;
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bool _irqEnabled = false;
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uint16_t _hCounter = 0;
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uint16_t _vCounter = 0;
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uint64_t _autoReadClockStart = 0;
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uint64_t _autoReadNextClock = 0;
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@ -38,6 +43,8 @@ private:
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uint8_t ReadControllerData(uint8_t port, bool getMsb);
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__forceinline void UpdateIrqLevel();
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public:
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InternalRegisters();
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void Initialize(SnesConsole* console);
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@ -69,25 +76,85 @@ public:
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void Serialize(Serializer &s) override;
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};
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void InternalRegisters::ProcessIrqCounters()
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void InternalRegisters::UpdateIrqLevel()
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{
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if(_needIrq > 0) {
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_needIrq--;
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if(_needIrq == 0) {
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SetIrqFlag(true);
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}
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if(!_irqEnabled) {
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_irqLevel = false;
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return;
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}
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bool irqLevel = (
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(_state.EnableHorizontalIrq || _state.EnableVerticalIrq) &&
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(!_state.EnableHorizontalIrq || (_state.HorizontalTimer <= 339 && (_ppu->GetCycle() == _state.HorizontalTimer) && (_ppu->GetLastScanline() != _ppu->GetRealScanline() || _state.HorizontalTimer < 339))) &&
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(!_state.EnableVerticalIrq || _ppu->GetRealScanline() == _state.VerticalTimer)
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(!_state.EnableHorizontalIrq || _state.HorizontalTimer == _hCounter) &&
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(!_state.EnableVerticalIrq || _state.VerticalTimer == _vCounter)
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);
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if(!_irqLevel && irqLevel) {
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//Trigger IRQ signal 16 master clocks later
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_needIrq = 4;
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if(_state.EnableHorizontalIrq && _memoryManager->GetHClock() == 6) {
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_needIrq = 3;
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} else {
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_needIrq = 2;
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}
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}
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_irqLevel = irqLevel;
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_cpu->SetNmiFlag(_state.EnableNmi & _nmiFlag);
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}
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void InternalRegisters::ProcessIrqCounters()
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{
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//This circuit runs at MasterClock/4, and the signal is inverted. This means it ticks at hclock 2, 6, etc. on every scanline.
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//VBLANK is cleared by the PPU at H=0, and which will be picked up on H=2
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//HBLANK however is cleared by the PPU at H=4, and this will only be picked up at H=6, which causes IRQs that depend on the value of H
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//to be delayed by an extra 4 cycles compared to IRQs that trigger only based on V.
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//Once VBLANK is cleared, a 4-cycle reset signal is triggered (from H=2 to H=6) and the V counter is reset to 0 (at H=2)
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//Once HBLANK is cleared (every scanline), a 4-cycle reset signal is triggered and the H counter is reset to 0 (at H=6) and then starts
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//counting again start from H=14+.
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//HBLANK getting cleared also triggers a V counter increment (at H=6).
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//When the H/V counters match the values in $4207-420A (+ the correct IRQ enable flags are turned on), an IRQ is triggered 2 ticks (8 master clocks) later.
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//Some not-quite-figured out edge cases remain:
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// -IRQs for H=0 (i.e when 4207/8 == 0) seem to be delayed by an extra tick (4 master clocks)?
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// -What's causing the 2 ticks/8 master clock delay for the IRQ signal after it was detected?
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// -What's causing the 1 tick/4 master clock delay for the NMI signal after it was detected? (e.g why does the CPU behave like it was set on H=6 instead of H=2?)
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//Notes:
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// -IRQs can't trigger on V=261 H=339 (reg values), because V gets reset to 0 at H=2 at the same time as H increments to 339. This might mean that an IRQ at
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// V=0 and H=339 triggers both on scanline 0 and scanline 1 (at H=2)? (unverified)
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//See CPU schematics here: https://github.com/rgalland/SNES_S-CPU_Schematics/
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if(_needIrq > 0) {
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_needIrq--;
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if(_needIrq == 1) {
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SetIrqFlag(true);
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} else if(_needIrq == 0) {
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if(_irqFlag) {
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_cpu->SetIrqSource(SnesIrqSource::Ppu);
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} else {
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_cpu->ClearIrqSource(SnesIrqSource::Ppu);
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}
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}
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}
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uint16_t hClock = _memoryManager->GetHClock();
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if(hClock > 10) {
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_hCounter++;
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} else if(hClock == 10) {
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_hCounter = 0;
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} else if(hClock == 6) {
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_hCounter = 0;
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if(_ppu->GetScanline() > 0 && !_ppu->IsInOverclockedScanline()) {
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_vCounter++;
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}
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if(_state.EnableNmi && _ppu->GetScanline() == _ppu->GetNmiScanline()) {
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_cpu->SetNmiFlag(1);
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}
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} else if(hClock == 2) {
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_hCounter++;
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if(_ppu->GetScanline() == _ppu->GetNmiScanline()) {
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_nmiFlag = true;
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} else if(_ppu->GetScanline() == 0) {
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_nmiFlag = false;
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_vCounter = 0;
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}
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}
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UpdateIrqLevel();
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}
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@ -1164,6 +1164,7 @@ void SnesCpu::WAI()
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{
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//Wait for interrupt
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_state.StopState = SnesCpuStopState::WaitingForIrq;
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_waiOver = false;
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}
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/****************
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@ -5,8 +5,7 @@ void SnesCpu::PowerOn()
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_state.SP = 0x1FF;
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_state.PS = ProcFlags::IrqDisable;
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_state.EmulationMode = true;
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_state.NmiFlag = false;
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_state.PrevNmiFlag = false;
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_state.NmiFlagCounter = 0;
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_state.StopState = SnesCpuStopState::Running;
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_state.IrqSource = (uint8_t)SnesIrqSource::None;
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_state.PrevIrqSource = (uint8_t)SnesIrqSource::None;
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@ -30,8 +29,7 @@ void SnesCpu::Reset()
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_state.PC = GetResetVector();
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SetSP(_state.SP);
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_state.NmiFlag = false;
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_state.PrevNmiFlag = false;
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_state.NmiFlagCounter = 0;
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_state.StopState = SnesCpuStopState::Running;
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_state.IrqSource = (uint8_t)SnesIrqSource::None;
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_state.PrevIrqSource = (uint8_t)SnesIrqSource::None;
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@ -243,7 +241,7 @@ void SnesCpu::RunOp()
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case 0xC8: AddrMode_Imp(); INY(); break;
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case 0xC9: AddrMode_ImmM(); CMP(); break;
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case 0xCA: AddrMode_Imp(); DEX(); break;
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case 0xCB: AddrMode_Imp(); WAI(); break;
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case 0xCB: WAI(); break;
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case 0xCC: AddrMode_Abs(); CPY(); break;
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case 0xCD: AddrMode_Abs(); CMP(); break;
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case 0xCE: AddrMode_Abs(); DEC(); break;
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@ -309,9 +307,9 @@ uint64_t SnesCpu::GetCycleCount()
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return _state.CycleCount;
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}
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void SnesCpu::SetNmiFlag(bool nmiFlag)
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void SnesCpu::SetNmiFlag(uint8_t delay)
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{
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_state.NmiFlag = nmiFlag;
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_state.NmiFlagCounter = delay;
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}
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void SnesCpu::DetectNmiSignalEdge()
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@ -319,20 +317,33 @@ void SnesCpu::DetectNmiSignalEdge()
|
|||
//"This edge detector polls the status of the NMI line during φ2 of each CPU cycle (i.e., during the
|
||||
//second half of each cycle) and raises an internal signal if the input goes from being high during
|
||||
//one cycle to being low during the next"
|
||||
if(!_state.PrevNmiFlag && _state.NmiFlag) {
|
||||
_state.NeedNmi = true;
|
||||
if(_state.NmiFlagCounter) {
|
||||
_state.NmiFlagCounter--;
|
||||
if(_state.NmiFlagCounter == 0) {
|
||||
if(!_state.IrqLock) {
|
||||
//Trigger an NMI on the next instruction
|
||||
_state.NmiFlagCounter = false;
|
||||
_state.NeedNmi = true;
|
||||
_waiOver = true;
|
||||
} else {
|
||||
//Delay NMI if a DMA/HDMA just finished running
|
||||
_state.NmiFlagCounter = 1;
|
||||
_state.NeedNmi = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
_state.PrevNmiFlag = _state.NmiFlag;
|
||||
}
|
||||
|
||||
void SnesCpu::UpdateIrqNmiFlags()
|
||||
{
|
||||
|
||||
if(!_state.IrqLock) {
|
||||
//"The internal signal goes high during φ1 of the cycle that follows the one where the edge is detected,
|
||||
//and stays high until the NMI has been handled. "
|
||||
_state.PrevNeedNmi = _state.NeedNmi;
|
||||
_state.PrevIrqSource = _state.IrqSource && !CheckFlag(ProcFlags::IrqDisable);
|
||||
_state.PrevIrqSource = _state.IrqSource != 0 && !CheckFlag(ProcFlags::IrqDisable);
|
||||
if(_state.IrqSource != 0) {
|
||||
//WAI ends even if the I flag is set (but execution won't jump to the IRQ handler)
|
||||
_waiOver = true;
|
||||
}
|
||||
} else {
|
||||
//Delay IRQ if a DMA/HDMA just finished running
|
||||
_state.PrevIrqSource = 0;
|
||||
}
|
||||
|
||||
_state.IrqLock = false;
|
||||
}
|
||||
|
||||
|
|
@ -374,7 +385,8 @@ uint8_t SnesCpu::GetOpCode()
|
|||
|
||||
void SnesCpu::IdleOrRead()
|
||||
{
|
||||
if(_state.PrevIrqSource) {
|
||||
if(!_state.IrqLock && ((_state.IrqSource != 0 || _state.PrevIrqSource != 0) && !CheckFlag(ProcFlags::IrqDisable)) || (_state.NmiFlagCounter == 1 || _state.NeedNmi)) {
|
||||
//If an IRQ or NMI will be triggered on the next instruction/cycle, the 6-clock idle cycle turns into a dummy read at the current PC
|
||||
ReadCode(_state.PC);
|
||||
} else {
|
||||
Idle();
|
||||
|
|
@ -614,6 +626,6 @@ bool SnesCpu::CheckFlag(uint8_t flag)
|
|||
void SnesCpu::Serialize(Serializer &s)
|
||||
{
|
||||
SV(_state.A); SV(_state.CycleCount); SV(_state.D); SV(_state.DBR); SV(_state.EmulationMode); SV(_state.IrqSource); SV(_state.K);
|
||||
SV(_state.NmiFlag); SV(_state.PC); SV(_state.PrevIrqSource); SV(_state.PrevNmiFlag); SV(_state.PS); SV(_state.SP); SV(_state.StopState);
|
||||
SV(_state.X); SV(_state.Y); SV(_state.IrqLock); SV(_state.NeedNmi); SV(_state.PrevNeedNmi);
|
||||
SV(_state.NmiFlagCounter); SV(_state.PC); SV(_state.PrevIrqSource); SV(_state.PS); SV(_state.SP); SV(_state.StopState);
|
||||
SV(_state.X); SV(_state.Y); SV(_state.IrqLock); SV(_state.NeedNmi); SV(_waiOver);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ void SnesCpu::CheckForInterrupts()
|
|||
{
|
||||
#ifndef DUMMYCPU
|
||||
//Use the state of the IRQ/NMI flags on the previous cycle to determine if an IRQ is processed or not
|
||||
if(_state.PrevNeedNmi) {
|
||||
if(_state.NeedNmi) {
|
||||
_state.NeedNmi = false;
|
||||
uint32_t originalPc = GetProgramAddress(_state.PC);
|
||||
_emu->GetCheatManager()->RefreshRamCheats(CpuType::Snes);
|
||||
|
|
@ -74,10 +74,9 @@ void SnesCpu::ProcessHaltedState()
|
|||
#endif
|
||||
} else {
|
||||
//WAI
|
||||
bool over = _waiOver;
|
||||
Idle();
|
||||
if(_state.IrqSource || _state.NeedNmi) {
|
||||
Idle();
|
||||
Idle();
|
||||
if(over) {
|
||||
_state.StopState = SnesCpuStopState::Running;
|
||||
CheckForInterrupts();
|
||||
}
|
||||
|
|
@ -91,7 +90,6 @@ void SnesCpu::Idle()
|
|||
ProcessCpuCycle();
|
||||
_memoryManager->IncMasterClock6();
|
||||
_emu->ProcessIdleCycle<CpuType::Snes>();
|
||||
UpdateIrqNmiFlags();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -107,8 +105,6 @@ void SnesCpu::IdleOrDummyWrite(uint32_t addr, uint8_t value)
|
|||
_memoryManager->IncMasterClock6();
|
||||
_emu->ProcessIdleCycle<CpuType::Snes>();
|
||||
}
|
||||
|
||||
UpdateIrqNmiFlags();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -125,8 +121,8 @@ void SnesCpu::IdleTakeBranch()
|
|||
void SnesCpu::ProcessCpuCycle()
|
||||
{
|
||||
_state.CycleCount++;
|
||||
DetectNmiSignalEdge();
|
||||
_state.IrqLock = _dmaController->ProcessPendingTransfers();
|
||||
DetectNmiSignalEdge();
|
||||
}
|
||||
|
||||
uint16_t SnesCpu::ReadVector(uint16_t vector)
|
||||
|
|
@ -145,9 +141,7 @@ uint8_t SnesCpu::Read(uint32_t addr, MemoryOperationType type)
|
|||
{
|
||||
_memoryManager->SetCpuSpeed(_memoryManager->GetCpuSpeed(addr));
|
||||
ProcessCpuCycle();
|
||||
uint8_t value = _memoryManager->Read(addr, type);
|
||||
UpdateIrqNmiFlags();
|
||||
return value;
|
||||
return _memoryManager->Read(addr, type);
|
||||
}
|
||||
|
||||
void SnesCpu::Write(uint32_t addr, uint8_t value, MemoryOperationType type)
|
||||
|
|
@ -155,6 +149,5 @@ void SnesCpu::Write(uint32_t addr, uint8_t value, MemoryOperationType type)
|
|||
_memoryManager->SetCpuSpeed(_memoryManager->GetCpuSpeed(addr));
|
||||
ProcessCpuCycle();
|
||||
_memoryManager->Write(addr, value, type);
|
||||
UpdateIrqNmiFlags();
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ private:
|
|||
|
||||
SnesCpuState _state = {};
|
||||
uint32_t _operand = 0;
|
||||
bool _waiOver = true;
|
||||
|
||||
uint32_t GetProgramAddress(uint16_t addr);
|
||||
uint32_t GetDataAddress(uint16_t addr);
|
||||
|
|
@ -56,7 +57,6 @@ private:
|
|||
|
||||
uint16_t GetResetVector();
|
||||
|
||||
void UpdateIrqNmiFlags();
|
||||
void ProcessCpuCycle();
|
||||
|
||||
void Idle();
|
||||
|
|
@ -347,7 +347,7 @@ public:
|
|||
template<uint64_t value>
|
||||
void IncreaseCycleCount();
|
||||
|
||||
void SetNmiFlag(bool nmiFlag);
|
||||
void SetNmiFlag(uint8_t delay);
|
||||
void DetectNmiSignalEdge();
|
||||
|
||||
void SetIrqSource(SnesIrqSource source);
|
||||
|
|
|
|||
|
|
@ -40,11 +40,9 @@ struct SnesCpuState : BaseState
|
|||
bool EmulationMode;
|
||||
|
||||
/* Misc internal state */
|
||||
bool NmiFlag;
|
||||
bool PrevNmiFlag;
|
||||
uint8_t NmiFlagCounter;
|
||||
|
||||
bool IrqLock;
|
||||
bool PrevNeedNmi;
|
||||
bool NeedNmi;
|
||||
|
||||
uint8_t IrqSource;
|
||||
|
|
|
|||
|
|
@ -184,6 +184,7 @@ void SnesMemoryManager::Exec()
|
|||
|
||||
if((_hClock & 0x03) == 0) {
|
||||
_emu->ProcessPpuCycle<CpuType::Snes>();
|
||||
} else if(_hClock & 0x02) {
|
||||
_regs->ProcessIrqCounters();
|
||||
}
|
||||
|
||||
|
|
@ -201,9 +202,6 @@ void SnesMemoryManager::ProcessEvent()
|
|||
|
||||
case SnesEventType::DramRefresh:
|
||||
IncMasterClock40();
|
||||
//TODOv2?
|
||||
//_cpu->IncreaseCycleCount<5>();
|
||||
|
||||
if(_ppu->GetScanline() < _ppu->GetVblankStart()) {
|
||||
_nextEvent = SnesEventType::HdmaStart;
|
||||
_nextEventClock = 276 * 4;
|
||||
|
|
@ -221,11 +219,11 @@ void SnesMemoryManager::ProcessEvent()
|
|||
|
||||
case SnesEventType::EndOfScanline:
|
||||
if(_ppu->ProcessEndOfScanline(_hClock)) {
|
||||
_dramRefreshPosition = 538 - (_masterClock & 0x07);
|
||||
if(_ppu->GetScanline() == 0) {
|
||||
_nextEvent = SnesEventType::HdmaInit;
|
||||
_nextEventClock = 12 + (_masterClock & 0x07);
|
||||
} else {
|
||||
_dramRefreshPosition = 538 - (_masterClock & 0x07);
|
||||
_nextEvent = SnesEventType::DramRefresh;
|
||||
_nextEventClock = _dramRefreshPosition;
|
||||
}
|
||||
|
|
@ -261,7 +259,6 @@ uint8_t SnesMemoryManager::Read(uint32_t addr, MemoryOperationType type)
|
|||
|
||||
uint8_t SnesMemoryManager::ReadDma(uint32_t addr, bool forBusA)
|
||||
{
|
||||
_cpu->DetectNmiSignalEdge();
|
||||
IncMasterClock4();
|
||||
|
||||
uint8_t value;
|
||||
|
|
@ -329,7 +326,6 @@ void SnesMemoryManager::Write(uint32_t addr, uint8_t value, MemoryOperationType
|
|||
|
||||
void SnesMemoryManager::WriteDma(uint32_t addr, uint8_t value, bool forBusA)
|
||||
{
|
||||
_cpu->DetectNmiSignalEdge();
|
||||
IncMasterClock4();
|
||||
if(_emu->ProcessMemoryWrite<CpuType::Snes>(addr, value, MemoryOperationType::DmaWrite)) {
|
||||
IMemoryHandler* handler = _mappings.GetHandler(addr);
|
||||
|
|
|
|||
|
|
@ -478,14 +478,12 @@ bool SnesPpu::ProcessEndOfScanline(uint16_t& hClock)
|
|||
_emu->ProcessEvent(EventType::EndFrame);
|
||||
|
||||
_frameCount++;
|
||||
_regs->SetNmiFlag(true);
|
||||
SendFrame();
|
||||
|
||||
_console->ProcessEndOfFrame();
|
||||
} else if(_scanline >= _vblankEndScanline + 1) {
|
||||
//"Frames are 262 scanlines in non-interlace mode, while in interlace mode frames with $213f.7=0 are 263 scanlines"
|
||||
_oddFrame ^= 1;
|
||||
_regs->SetNmiFlag(false);
|
||||
_scanline = 0;
|
||||
_rangeOver = false;
|
||||
_timeOver = false;
|
||||
|
|
@ -514,6 +512,11 @@ bool SnesPpu::ProcessEndOfScanline(uint16_t& hClock)
|
|||
return false;
|
||||
}
|
||||
|
||||
bool SnesPpu::IsInOverclockedScanline()
|
||||
{
|
||||
return _inOverclockedScanline;
|
||||
}
|
||||
|
||||
void SnesPpu::UpdateSpcState()
|
||||
{
|
||||
//When using overclocking, turn off the SPC during the extra scanlines
|
||||
|
|
@ -521,13 +524,16 @@ void SnesPpu::UpdateSpcState()
|
|||
if(_scanline > _adjustedVblankEndScanline) {
|
||||
//Disable APU for extra lines after NMI
|
||||
_spc->SetSpcState(false);
|
||||
_inOverclockedScanline = true;
|
||||
} else if(_scanline >= _vblankStartScanline && _scanline < _nmiScanline) {
|
||||
//Disable APU for extra lines before NMI
|
||||
_spc->SetSpcState(false);
|
||||
_inOverclockedScanline = true;
|
||||
} else {
|
||||
_spc->SetSpcState(true);
|
||||
}
|
||||
}
|
||||
_inOverclockedScanline = false;
|
||||
}
|
||||
|
||||
void SnesPpu::UpdateNmiScanline()
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ private:
|
|||
uint16_t _adjustedVblankEndScanline;
|
||||
uint16_t _nmiScanline;
|
||||
bool _overclockEnabled;
|
||||
bool _inOverclockedScanline = false;
|
||||
|
||||
uint8_t _oddFrame = 0;
|
||||
|
||||
|
|
@ -237,6 +238,7 @@ public:
|
|||
void GetState(SnesPpuState &state, bool returnPartialState);
|
||||
|
||||
bool ProcessEndOfScanline(uint16_t& hClock);
|
||||
bool IsInOverclockedScanline();
|
||||
void UpdateSpcState();
|
||||
void UpdateNmiScanline();
|
||||
uint16_t GetLastScanline();
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ namespace Mesen.Debugger.StatusViews
|
|||
RegPS = (byte)cpu.PS;
|
||||
|
||||
FlagE = cpu.EmulationMode;
|
||||
FlagNmi = cpu.NmiFlag;
|
||||
FlagNmi = cpu.NmiFlagCounter > 0 || cpu.NeedNmi;
|
||||
FlagIrqHvCounters = (cpu.IrqSource & (byte)SnesIrqSource.Ppu) != 0;
|
||||
FlagIrqCoprocessor = (cpu.IrqSource & (byte)SnesIrqSource.Coprocessor) != 0;
|
||||
|
||||
|
|
@ -140,7 +140,9 @@ namespace Mesen.Debugger.StatusViews
|
|||
cpu.PS = (SnesCpuFlags)RegPS;
|
||||
|
||||
cpu.EmulationMode = FlagE;
|
||||
cpu.NmiFlag = FlagNmi;
|
||||
if(FlagNmi && cpu.NmiFlagCounter == 0 && !cpu.NeedNmi) {
|
||||
cpu.NmiFlagCounter = (byte)(FlagNmi ? 1 : 0);
|
||||
}
|
||||
cpu.IrqSource = (byte)(
|
||||
(FlagIrqHvCounters ? (byte)SnesIrqSource.Ppu : 0) |
|
||||
(FlagIrqCoprocessor ? (byte)SnesIrqSource.Coprocessor : 0)
|
||||
|
|
|
|||
|
|
@ -60,11 +60,9 @@ public struct SnesCpuState : BaseState
|
|||
public SnesCpuFlags PS;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool EmulationMode;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool NmiFlag;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool PrevNmiFlag;
|
||||
[MarshalAs(UnmanagedType.I1)] public byte NmiFlagCounter;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool IrqLock;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool PrevNeedNmi;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool NeedNmi;
|
||||
|
||||
public byte IrqSource;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue