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Fix for MMC1 - Ignore writes that occur after a dummy write - Fixes Bill & Teds + others

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Souryo 2014-07-28 20:52:47 -04:00
parent 4897f2f6ad
commit 84e54c9b7d
3 changed files with 28 additions and 16 deletions
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5
Core/CPU.cpp
View file

@ -2,6 +2,7 @@
#include "CPU.h"
int32_t CPU::CycleCount = 0;
int32_t CPU::RelativeCycleCount = 0;
uint32_t CPU::CyclePenalty = 0;
bool CPU::NMIFlag = false;
uint32_t CPU::IRQFlag = 0;
@ -96,6 +97,7 @@ void CPU::Reset(bool softReset)
CPU::NMIFlag = false;
CPU::IRQFlag = 0;
CPU::CycleCount = 0;
CPU::RelativeCycleCount = 0;
_state.PC = MemoryReadWord(CPU::ResetVector);
if(softReset) {
@ -160,6 +162,7 @@ uint32_t CPU::Exec()
void CPU::EndFrame()
{
CPU::RelativeCycleCount += CPU::CycleCount;
CPU::CycleCount = 0;
}
@ -178,4 +181,6 @@ void CPU::StreamState(bool saving)
Stream<bool>(_runNMI);
Stream<bool>(_runIRQ);
Stream<int32_t>(CPU::RelativeCycleCount);
}

2
Core/CPU.h
View file

@ -54,6 +54,7 @@ private:
typedef void(CPU::*Func)();
static int32_t CycleCount;
static int32_t RelativeCycleCount;
static uint32_t CyclePenalty;
Func _opTable[256];
@ -628,6 +629,7 @@ public:
CPU(MemoryManager *memoryManager);
static int32_t GetCycleCount() { return CPU::CycleCount; }
static int32_t GetRelativeCycleCount() { return CPU::RelativeCycleCount + CPU::CycleCount; }
static void IncCycleCount(uint32_t cycles) {
CPU::CyclePenalty += cycles;
CPU::CycleCount += cycles;

37
Core/MMC1.h
View file

@ -42,6 +42,8 @@ class MMC1 : public BaseMapper
uint8_t _chrReg1;
uint8_t _prgReg;
int32_t _lastWriteCycle = -1;
struct {
uint8_t Reg8000;
uint8_t RegA000;
@ -73,16 +75,11 @@ class MMC1 : public BaseMapper
_state.Reg8000 |= 0x0C;
return false;
} else {
//std::cout << std::hex << "input value: " << (short)value << std::endl;
_writeBuffer >>= 1;
_writeBuffer |= ((value << 4) & 0x10);
_shiftCount++;
if(_shiftCount == 5) {
//std::cout << std::hex << "value: " << (short)_writeBuffer << std::endl;
}
return _shiftCount == 5;
}
}
@ -142,6 +139,8 @@ class MMC1 : public BaseMapper
Stream<uint8_t>(_writeBuffer);
Stream<uint8_t>(_shiftCount);
Stream<int32_t>(_lastWriteCycle);
BaseMapper::StreamState(saving);
}
@ -160,18 +159,24 @@ class MMC1 : public BaseMapper
void WriteRegister(uint16_t addr, uint8_t value)
{
if(IsBufferFull(value)) {
switch((MMC1Registers)((addr & 0x6000) >> 13)) {
case MMC1Registers::Reg8000: _state.Reg8000 = _writeBuffer; break;
case MMC1Registers::RegA000: _state.RegA000 = _writeBuffer; break;
case MMC1Registers::RegC000: _state.RegC000 = _writeBuffer; break;
case MMC1Registers::RegE000: _state.RegE000 = _writeBuffer; break;
int32_t currentCycle = CPU::GetRelativeCycleCount();
//Ignore write if within 2 cycles of another write (i.e the real write after a dummy write)
if(abs(currentCycle - _lastWriteCycle) >= 2) {
if(IsBufferFull(value)) {
switch((MMC1Registers)((addr & 0x6000) >> 13)) {
case MMC1Registers::Reg8000: _state.Reg8000 = _writeBuffer; break;
case MMC1Registers::RegA000: _state.RegA000 = _writeBuffer; break;
case MMC1Registers::RegC000: _state.RegC000 = _writeBuffer; break;
case MMC1Registers::RegE000: _state.RegE000 = _writeBuffer; break;
}
UpdateState();
//Reset buffer after writing 5 bits
ResetBuffer();
}
UpdateState();
//Reset buffer after writing 5 bits
ResetBuffer();
}
_lastWriteCycle = currentCycle;
}
};