Mesen-SX

926 commits 3 branches 4 tags 19 MiB

Author	SHA1	Message	Date
Sour	1d6253d2e5	SA-1: Fixed SA-1 vector logic Reads done by the code should return the values at the read address, rather than returning the vector register value (fixes Gradius/Contra 3 SA-1 romhacks that are known to work on hardware)	2020-03-01 18:24:24 -05:00
Sour	67b286a16f	SA1: Improved timings (bus conflicts, etc.) -Fixed I-RAM access speed while main CPU is DMAing to I-RAM -Fixed missing extra cycle on BRL -Fixed idle SA-1 cycles (incorrectly) taking more than 1 cycle during bus conflicts -Fixed branch instructions to apply cycle penalties based on the destination address' type (rather than the source address)	2019-11-25 21:01:21 -05:00
Sour	fe470dd87a	SA-1 support (still missing a few rarely used features)	2019-07-25 22:22:09 -04:00

Author

SHA1

Message

Date

Sour

1d6253d2e5

SA-1: Fixed SA-1 vector logic

Reads done by the code should return the values at the read address, rather than returning the vector register value (fixes Gradius/Contra 3 SA-1 romhacks that are known to work on hardware)

2020-03-01 18:24:24 -05:00

Sour

67b286a16f

SA1: Improved timings (bus conflicts, etc.)

-Fixed I-RAM access speed while main CPU is DMAing to I-RAM
-Fixed missing extra cycle on BRL
-Fixed idle SA-1 cycles (incorrectly) taking more than 1 cycle during bus conflicts
-Fixed branch instructions to apply cycle penalties based on the destination address' type (rather than the source address)

2019-11-25 21:01:21 -05:00

Sour

fe470dd87a

SA-1 support (still missing a few rarely used features)

2019-07-25 22:22:09 -04:00

Renamed from Core/Cpu.Instructions.cpp (Browse further)

3 commits