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https://github.com/SourMesen/Mesen-S.git
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6539b92502
Memory handlers did not have the _memoryType value set, which caused some memory accesses to be much faster than expected
121 lines
3.9 KiB
C++
121 lines
3.9 KiB
C++
#include "stdafx.h"
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#include "Sdd1.h"
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#include "Sdd1Mmc.h"
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#include "Console.h"
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#include "BaseCartridge.h"
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#include "MemoryManager.h"
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#include "MemoryMappings.h"
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Sdd1::Sdd1(Console* console) : BaseCoprocessor(SnesMemoryType::Register)
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{
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//This handler is used to dynamically map the ROM based on the banking registers
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_sdd1Mmc.reset(new Sdd1Mmc(_state, console->GetCartridge().get()));
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MemoryMappings *cpuMappings = console->GetMemoryManager()->GetMemoryMappings();
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vector<unique_ptr<IMemoryHandler>> &prgRomHandlers = console->GetCartridge()->GetPrgRomHandlers();
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vector<unique_ptr<IMemoryHandler>> &saveRamHandlers = console->GetCartridge()->GetSaveRamHandlers();
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//Regular A Bus register handler, keep a reference to it, it'll be overwritten below
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_cpuRegisterHandler = cpuMappings->GetHandler(0x4000);
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//Based on forum thread info: https://forums.nesdev.com/viewtopic.php?f=12&t=14156
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cpuMappings->RegisterHandler(0x00, 0x3F, 0x6000, 0x7FFF, saveRamHandlers);
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cpuMappings->RegisterHandler(0x80, 0xBF, 0x6000, 0x7FFF, saveRamHandlers);
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cpuMappings->RegisterHandler(0x70, 0x73, 0x0000, 0xFFFF, saveRamHandlers);
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//S-DD1 registers (0x4800-0x4807)
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cpuMappings->RegisterHandler(0x00, 0x3F, 0x4000, 0x4FFF, this);
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cpuMappings->RegisterHandler(0x80, 0xBF, 0x4000, 0x4FFF, this);
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cpuMappings->RegisterHandler(0x00, 0x3F, 0x8000, 0xFFFF, prgRomHandlers);
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cpuMappings->RegisterHandler(0x80, 0xBF, 0x8000, 0xFFFF, prgRomHandlers);
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//Override these segments to implement the miroring that $4805/$4807 cause
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cpuMappings->RegisterHandler(0x20, 0x3F, 0x8000, 0xFFFF, _sdd1Mmc.get());
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cpuMappings->RegisterHandler(0xA0, 0xBF, 0x8000, 0xFFFF, _sdd1Mmc.get());
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//Regular bank switched mappings
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cpuMappings->RegisterHandler(0xC0, 0xFF, 0x0000, 0xFFFF, _sdd1Mmc.get());
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Reset();
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}
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void Sdd1::Reset()
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{
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_state = {};
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_state.NeedInit = true;
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_state.SelectedBanks[0] = 0;
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_state.SelectedBanks[1] = 1;
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_state.SelectedBanks[2] = 2;
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_state.SelectedBanks[3] = 3;
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}
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uint8_t Sdd1::Read(uint32_t addr)
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{
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if((uint16_t)addr >= 0x4800 && (uint16_t)addr <= 0x4807) {
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switch(addr & 0x07) {
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case 0: return _state.AllowDmaProcessing;
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case 1: return _state.ProcessNextDma;
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case 4: case 5: case 6: case 7:
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return _state.SelectedBanks[addr & 0x03];
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}
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}
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return _cpuRegisterHandler->Read(addr);
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}
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void Sdd1::Write(uint32_t addr, uint8_t value)
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{
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if((uint16_t)addr >= 0x4800 && (uint16_t)addr <= 0x4807) {
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//S-DD1 registers
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switch(addr & 0x07) {
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case 0: _state.AllowDmaProcessing = value; break;
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case 1: _state.ProcessNextDma = value; break;
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case 4: case 5: case 6: case 7:
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_state.SelectedBanks[addr & 0x03] = value;
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break;
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}
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} else {
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if((uint16_t)addr >= 0x4300 && (uint16_t)addr <= 0x437A) {
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//Keep track of writes to the DMA controller to know which address/length the DMAs will use
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uint8_t ch = (addr >> 4) & 0x07;
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switch(addr & 0x0F) {
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case 0x02: _state.DmaAddress[ch] = (_state.DmaAddress[ch] & 0xFFFF00) | value; break;
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case 0x03: _state.DmaAddress[ch] = (_state.DmaAddress[ch] & 0xFF00FF) | (value << 8); break;
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case 0x04: _state.DmaAddress[ch] = (_state.DmaAddress[ch] & 0x00FFFF) | (value << 16); break;
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case 0x05: _state.DmaLength[ch] = (_state.DmaLength[ch] & 0xFF00) | value; break;
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case 0x06: _state.DmaLength[ch] = (_state.DmaLength[ch] & 0x00FF) | (value << 8); break;
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}
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}
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//Forward everything else to the regular handler
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_cpuRegisterHandler->Write(addr, value);
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}
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}
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void Sdd1::Serialize(Serializer &s)
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{
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s.Stream(_state.AllowDmaProcessing, _state.ProcessNextDma, _state.NeedInit);
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s.StreamArray(_state.DmaAddress, 8);
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s.StreamArray(_state.DmaLength, 8);
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s.StreamArray(_state.SelectedBanks, 4);
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s.Stream(_sdd1Mmc.get());
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}
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uint8_t Sdd1::Peek(uint32_t addr)
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{
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return 0;
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}
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void Sdd1::PeekBlock(uint32_t addr, uint8_t* output)
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{
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memset(output, 0, 0x1000);
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}
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AddressInfo Sdd1::GetAbsoluteAddress(uint32_t address)
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{
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return { -1, SnesMemoryType::Register };
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}
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