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115 lines
2 KiB
C
115 lines
2 KiB
C
#pragma once
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#include "stdafx.h"
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#include "CpuTypes.h"
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enum class Sa1MathOp
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{
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Mul = 0,
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Div = 1,
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Sum = 2
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};
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enum class Sa1DmaSrcDevice
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{
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PrgRom = 0,
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BwRam = 1,
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InternalRam = 2,
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Reserved = 3
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};
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enum class Sa1DmaDestDevice
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{
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InternalRam = 0,
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BwRam = 1
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};
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struct Sa1State
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{
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uint16_t Sa1ResetVector;
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uint16_t Sa1IrqVector;
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uint16_t Sa1NmiVector;
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bool Sa1IrqRequested;
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bool Sa1IrqEnabled; //Enables IRQs from S-CPU to SA-1 (SA-1 receives interrupt)
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bool Sa1NmiRequested;
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bool Sa1NmiEnabled; //Enables NMIs from S-CPU to SA-1 (SA-1 receives NMI)
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bool Sa1Wait;
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bool Sa1Reset;
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bool DmaIrqEnabled;
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bool TimerIrqEnabled;
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uint8_t Sa1MessageReceived; //Sent by the S-CPU
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uint8_t CpuMessageReceived; //Sent by the SA-1
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uint16_t CpuIrqVector; //For the S-CPU
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uint16_t CpuNmiVector; //For the S-CPU
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bool UseCpuIrqVector;
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bool UseCpuNmiVector;
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bool CpuIrqRequested;
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bool CpuIrqEnabled; //Enables IRQs from SA-1 to S-CPU
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bool CharConvIrqFlag;
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bool CharConvIrqEnabled;
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bool CharConvDmaActive;
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uint8_t CharConvBpp;
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uint8_t CharConvFormat;
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uint8_t CharConvWidth;
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uint8_t CharConvCounter;
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uint8_t CpuBwBank;
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bool CpuBwWriteEnabled;
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uint8_t Sa1BwBank;
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uint8_t Sa1BwMode;
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bool Sa1BwWriteEnabled;
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uint8_t BwWriteProtectedArea;
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bool BwRam2BppMode;
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uint8_t BitmapRegister1[8];
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uint8_t BitmapRegister2[8];
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uint8_t CpuIRamWriteProtect;
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uint8_t Sa1IRamWriteProtect;
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uint32_t DmaSrcAddr;
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uint32_t DmaDestAddr;
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uint16_t DmaSize;
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bool DmaEnabled;
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bool DmaPriority;
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bool DmaCharConv;
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bool DmaCharConvAuto;
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Sa1DmaDestDevice DmaDestDevice;
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Sa1DmaSrcDevice DmaSrcDevice;
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bool DmaRunning;
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bool DmaIrqFlag;
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bool HorizontalTimerEnabled;
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bool VerticalTimerEnabled;
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bool UseLinearTimer;
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uint16_t HTimer;
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uint16_t VTimer;
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uint32_t LinearTimerValue;
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Sa1MathOp MathOp;
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uint16_t MultiplicandDividend;
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uint16_t MultiplierDivisor;
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uint64_t MathOpResult;
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uint8_t MathOverflow;
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bool VarLenAutoInc;
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uint8_t VarLenBitCount;
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uint32_t VarLenAddress;
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uint8_t VarLenCurrentBit;
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uint8_t Banks[4];
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};
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struct DebugSa1State
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{
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CpuState Cpu;
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Sa1State Sa1;
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}; |