mirror of
https://github.com/SourMesen/Mesen-S.git
synced 2024-06-23 14:52:12 -04:00
425 lines
10 KiB
C++
425 lines
10 KiB
C++
#include "stdafx.h"
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#include "MemoryManager.h"
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#include "Console.h"
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#include "BaseCartridge.h"
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#include "Cpu.h"
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#include "Ppu.h"
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#include "DmaController.h"
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#include "RegisterHandlerA.h"
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#include "RegisterHandlerB.h"
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#include "RamHandler.h"
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#include "MessageManager.h"
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#include "DebugTypes.h"
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#include "EmuSettings.h"
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#include "Sa1.h"
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#include "Gsu.h"
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#include "Cx4.h"
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#include "Gameboy.h"
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#include "BaseCoprocessor.h"
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#include "CheatManager.h"
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#include "../Utilities/Serializer.h"
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#include "../Utilities/HexUtilities.h"
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void MemoryManager::Initialize(Console *console)
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{
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_masterClock = 0;
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_openBus = 0;
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_cpuSpeed = 8;
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_console = console;
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_regs = console->GetInternalRegisters().get();
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_cpu = console->GetCpu().get();
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_ppu = console->GetPpu().get();
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_cart = console->GetCartridge().get();
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_cheatManager = console->GetCheatManager().get();
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_workRam = new uint8_t[MemoryManager::WorkRamSize];
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_console->GetSettings()->InitializeRam(_workRam, MemoryManager::WorkRamSize);
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_registerHandlerA.reset(new RegisterHandlerA(
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console->GetDmaController().get(),
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console->GetInternalRegisters().get(),
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console->GetControlManager().get()
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));
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_registerHandlerB.reset(new RegisterHandlerB(
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_console,
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_ppu,
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console->GetSpc().get(),
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_workRam
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));
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for(uint32_t i = 0; i < 128 * 1024; i += 0x1000) {
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_workRamHandlers.push_back(unique_ptr<RamHandler>(new RamHandler(_workRam, i, MemoryManager::WorkRamSize, SnesMemoryType::WorkRam)));
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}
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_mappings.RegisterHandler(0x7E, 0x7F, 0x0000, 0xFFFF, _workRamHandlers);
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_mappings.RegisterHandler(0x00, 0x3F, 0x2000, 0x2FFF, _registerHandlerB.get());
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_mappings.RegisterHandler(0x80, 0xBF, 0x2000, 0x2FFF, _registerHandlerB.get());
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_mappings.RegisterHandler(0x00, 0x3F, 0x4000, 0x4FFF, _registerHandlerA.get());
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_mappings.RegisterHandler(0x80, 0xBF, 0x4000, 0x4FFF, _registerHandlerA.get());
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_mappings.RegisterHandler(0x00, 0x3F, 0x0000, 0x0FFF, _workRamHandlers[0].get());
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_mappings.RegisterHandler(0x80, 0xBF, 0x0000, 0x0FFF, _workRamHandlers[0].get());
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_mappings.RegisterHandler(0x00, 0x3F, 0x1000, 0x1FFF, _workRamHandlers[1].get());
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_mappings.RegisterHandler(0x80, 0xBF, 0x1000, 0x1FFF, _workRamHandlers[1].get());
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_cart->Init(_mappings);
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GenerateMasterClockTable();
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Reset();
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}
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MemoryManager::~MemoryManager()
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{
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delete[] _workRam;
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}
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void MemoryManager::Reset()
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{
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_masterClock = 0;
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_hClock = 0;
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_dramRefreshPosition = 538 - (_masterClock & 0x07);
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_nextEventClock = _dramRefreshPosition;
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_nextEvent = SnesEventType::DramRefresh;
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}
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void MemoryManager::GenerateMasterClockTable()
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{
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for(int i = 0; i < 0x800; i++) {
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uint8_t bank = (i & 0x300) >> 8;
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if(bank == 1) {
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//Banks $40-$7F - Slow
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_masterClockTable[i] = 8;
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} else if(bank == 3) {
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//Banks $C0-$FF
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//Slow or fast (depending on register)
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_masterClockTable[i] = (i >= 0x400) ? 6 : 8;
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} else {
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//Banks $00-$3F and $80-$BF
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uint8_t page = (i & 0xFF);
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if(page <= 0x1F) {
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//Slow
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_masterClockTable[i] = 8;
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} else if(page >= 0x20 && page <= 0x3F) {
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//Fast
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_masterClockTable[i] = 6;
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} else if(page == 0x40 || page == 0x41) {
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//Extra slow
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_masterClockTable[i] = 12;
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} else if(page >= 0x42 && page <= 0x5F) {
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//Fast
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_masterClockTable[i] = 6;
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} else if(page >= 0x60 && page <= 0x7F) {
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//Slow
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_masterClockTable[i] = 8;
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} else if(bank == 0) {
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//Slow
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_masterClockTable[i] = 8;
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} else {
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//page >= $80
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//Slow or fast (depending on register)
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_masterClockTable[i] = (i >= 0x400) ? 6 : 8;
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}
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}
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}
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}
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void MemoryManager::IncMasterClock4()
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{
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Exec();
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Exec();
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}
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void MemoryManager::IncMasterClock6()
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{
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Exec();
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Exec();
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Exec();
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}
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void MemoryManager::IncMasterClock8()
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{
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Exec();
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Exec();
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Exec();
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Exec();
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}
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void MemoryManager::IncMasterClock40()
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{
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Exec(); Exec(); Exec(); Exec(); Exec();
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Exec(); Exec(); Exec(); Exec(); Exec();
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Exec(); Exec(); Exec(); Exec(); Exec();
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Exec(); Exec(); Exec(); Exec(); Exec();
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}
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void MemoryManager::IncMasterClockStartup()
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{
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for(int i = 0; i < 182 / 2; i++) {
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Exec();
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}
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}
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void MemoryManager::IncrementMasterClockValue(uint16_t cyclesToRun)
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{
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switch(cyclesToRun) {
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case 12: Exec();
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case 10: Exec();
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case 8: Exec();
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case 6: Exec();
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case 4: Exec();
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case 2: Exec();
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}
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}
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void MemoryManager::Exec()
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{
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_masterClock += 2;
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_hClock += 2;
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if(_hClock == _nextEventClock) {
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ProcessEvent();
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}
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if((_hClock & 0x03) == 0) {
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_console->ProcessPpuCycle<CpuType::Cpu>();
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_regs->ProcessIrqCounters();
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}
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_cart->SyncCoprocessors();
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}
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void MemoryManager::ProcessEvent()
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{
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switch(_nextEvent) {
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case SnesEventType::HdmaInit:
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_console->GetDmaController()->BeginHdmaInit();
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_nextEvent = SnesEventType::DramRefresh;
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_nextEventClock = _dramRefreshPosition;
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break;
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case SnesEventType::DramRefresh:
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IncMasterClock40();
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_cpu->IncreaseCycleCount<5>();
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if(_ppu->GetScanline() < _ppu->GetVblankStart()) {
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_nextEvent = SnesEventType::HdmaStart;
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_nextEventClock = 276 * 4;
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} else {
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_nextEvent = SnesEventType::EndOfScanline;
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_nextEventClock = 1360;
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}
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break;
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case SnesEventType::HdmaStart:
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_console->GetDmaController()->BeginHdmaTransfer();
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_nextEvent = SnesEventType::EndOfScanline;
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_nextEventClock = 1360;
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break;
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case SnesEventType::EndOfScanline:
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if(_ppu->ProcessEndOfScanline(_hClock)) {
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_hClock = 0;
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if(_ppu->GetScanline() == 0) {
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_nextEvent = SnesEventType::HdmaInit;
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_nextEventClock = 12 + (_masterClock & 0x07);
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} else {
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_dramRefreshPosition = 538 - (_masterClock & 0x07);
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_nextEvent = SnesEventType::DramRefresh;
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_nextEventClock = _dramRefreshPosition;
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}
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} else {
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_nextEventClock += 2;
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}
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break;
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}
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}
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uint8_t MemoryManager::Read(uint32_t addr, MemoryOperationType type)
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{
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IncrementMasterClockValue(_cpuSpeed - 4);
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uint8_t value;
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IMemoryHandler *handler = _mappings.GetHandler(addr);
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if(handler) {
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value = handler->Read(addr);
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_memTypeBusA = handler->GetMemoryType();
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_openBus = value;
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} else {
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//open bus
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value = _openBus;
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LogDebug("[Debug] Read - missing handler: $" + HexUtilities::ToHex(addr));
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}
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_cheatManager->ApplyCheat(addr, value);
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_console->ProcessMemoryRead<CpuType::Cpu>(addr, value, type);
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IncMasterClock4();
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return value;
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}
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uint8_t MemoryManager::ReadDma(uint32_t addr, bool forBusA)
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{
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_cpu->DetectNmiSignalEdge();
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IncMasterClock4();
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uint8_t value;
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IMemoryHandler* handler = _mappings.GetHandler(addr);
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if(handler) {
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if(forBusA && handler == _registerHandlerB.get() && (addr & 0xFF00) == 0x2100) {
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//Trying to read from bus B using bus A returns open bus
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value = _openBus;
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} else if(handler == _registerHandlerA.get()) {
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uint16_t regAddr = addr & 0xFFFF;
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if(regAddr == 0x420B || regAddr == 0x420C || (regAddr >= 0x4300 && regAddr <= 0x437F)) {
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//Trying to read the DMA controller with DMA returns open bus
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value = _openBus;
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} else {
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value = handler->Read(addr);
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}
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} else {
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value = handler->Read(addr);
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if(handler != _registerHandlerB.get()) {
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_memTypeBusA = handler->GetMemoryType();
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}
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}
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_openBus = value;
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} else {
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//open bus
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value = _openBus;
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LogDebug("[Debug] Read - missing handler: $" + HexUtilities::ToHex(addr));
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}
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_cheatManager->ApplyCheat(addr, value);
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_console->ProcessMemoryRead<CpuType::Cpu>(addr, value, MemoryOperationType::DmaRead);
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return value;
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}
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uint8_t MemoryManager::Peek(uint32_t addr)
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{
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return _mappings.Peek(addr);
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}
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uint16_t MemoryManager::PeekWord(uint32_t addr)
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{
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return _mappings.PeekWord(addr);
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}
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void MemoryManager::PeekBlock(uint32_t addr, uint8_t *dest)
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{
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_mappings.PeekBlock(addr, dest);
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}
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void MemoryManager::Write(uint32_t addr, uint8_t value, MemoryOperationType type)
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{
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IncrementMasterClockValue(_cpuSpeed);
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_console->ProcessMemoryWrite<CpuType::Cpu>(addr, value, type);
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IMemoryHandler* handler = _mappings.GetHandler(addr);
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if(handler) {
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handler->Write(addr, value);
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_memTypeBusA = handler->GetMemoryType();
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} else {
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LogDebug("[Debug] Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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}
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}
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void MemoryManager::WriteDma(uint32_t addr, uint8_t value, bool forBusA)
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{
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_cpu->DetectNmiSignalEdge();
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IncMasterClock4();
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_console->ProcessMemoryWrite<CpuType::Cpu>(addr, value, MemoryOperationType::DmaWrite);
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IMemoryHandler* handler = _mappings.GetHandler(addr);
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if(handler) {
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if(forBusA && handler == _registerHandlerB.get() && (addr & 0xFF00) == 0x2100) {
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//Trying to write to bus B using bus A does nothing
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} else if(handler == _registerHandlerA.get()) {
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uint16_t regAddr = addr & 0xFFFF;
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if(regAddr == 0x420B || regAddr == 0x420C || (regAddr >= 0x4300 && regAddr <= 0x437F)) {
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//Trying to write to the DMA controller with DMA does nothing
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} else {
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handler->Write(addr, value);
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}
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} else {
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handler->Write(addr, value);
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if(handler != _registerHandlerB.get()) {
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_memTypeBusA = handler->GetMemoryType();
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}
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}
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} else {
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LogDebug("[Debug] Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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}
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}
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uint8_t MemoryManager::GetOpenBus()
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{
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return _openBus;
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}
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uint64_t MemoryManager::GetMasterClock()
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{
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return _masterClock;
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}
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uint16_t MemoryManager::GetHClock()
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{
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return _hClock;
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}
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uint8_t * MemoryManager::DebugGetWorkRam()
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{
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return _workRam;
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}
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MemoryMappings* MemoryManager::GetMemoryMappings()
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{
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return &_mappings;
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}
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uint8_t MemoryManager::GetCpuSpeed(uint32_t addr)
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{
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return _masterClockTable[(_regs->IsFastRomEnabled() << 10) | ((addr & 0xC00000) >> 14) | ((addr & 0xFF00) >> 8)];
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}
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uint8_t MemoryManager::GetCpuSpeed()
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{
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return _cpuSpeed;
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}
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void MemoryManager::SetCpuSpeed(uint8_t speed)
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{
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_cpuSpeed = speed;
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}
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SnesMemoryType MemoryManager::GetMemoryTypeBusA()
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{
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return _memTypeBusA;
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}
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bool MemoryManager::IsRegister(uint32_t cpuAddress)
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{
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IMemoryHandler* handler = _mappings.GetHandler(cpuAddress);
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return handler == _registerHandlerA.get() || handler == _registerHandlerB.get();
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}
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bool MemoryManager::IsWorkRam(uint32_t cpuAddress)
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{
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IMemoryHandler* handler = _mappings.GetHandler(cpuAddress);
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return handler && handler->GetMemoryType() == SnesMemoryType::WorkRam;
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}
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void MemoryManager::Serialize(Serializer &s)
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{
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s.Stream(_masterClock, _openBus, _cpuSpeed, _hClock, _dramRefreshPosition);
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s.StreamArray(_workRam, MemoryManager::WorkRamSize);
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if(s.GetVersion() < 8) {
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bool unusedHasEvent[1369];
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s.StreamArray(unusedHasEvent, sizeof(unusedHasEvent));
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}
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s.Stream(_registerHandlerB.get());
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}
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