mirror of
https://github.com/SourMesen/Mesen-S.git
synced 2024-06-23 06:41:55 -04:00
607 lines
18 KiB
C++
607 lines
18 KiB
C++
#include "stdafx.h"
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#include "DmaController.h"
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#include "DmaControllerTypes.h"
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#include "MemoryManager.h"
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#include "MessageManager.h"
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#include "../Utilities/Serializer.h"
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static constexpr uint8_t _transferByteCount[8] = { 1, 2, 2, 4, 4, 4, 2, 4 };
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static constexpr uint8_t _transferOffset[8][4] = {
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{ 0, 0, 0, 0 }, { 0, 1, 0, 1 }, { 0, 0, 0, 0 }, { 0, 0, 1, 1 },
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{ 0, 1, 2, 3 }, { 0, 1, 0, 1 }, { 0, 0, 0, 0 }, { 0, 0, 1, 1 }
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};
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DmaController::DmaController(MemoryManager *memoryManager)
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{
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_memoryManager = memoryManager;
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Reset();
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for(int j = 0; j < 8; j++) {
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for(int i = 0; i <= 0x0A; i++) {
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Write(0x4300 | i | (j << 4), 0xFF);
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}
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}
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}
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void DmaController::Reset()
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{
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_hdmaChannels = 0;
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_hdmaPending = false;
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_hdmaInitPending = false;
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_dmaStartDelay = false;
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_dmaPending = false;
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_needToProcess = false;
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for(int i = 0; i < 8; i++) {
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_channel[i].DmaActive = false;
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}
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}
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void DmaController::CopyDmaByte(uint32_t addressBusA, uint16_t addressBusB, bool fromBtoA)
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{
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if(fromBtoA) {
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if(addressBusB != 0x2180 || !_memoryManager->IsWorkRam(addressBusA)) {
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uint8_t valToWrite = _memoryManager->ReadDma(addressBusB, false);
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_memoryManager->WriteDma(addressBusA, valToWrite, true);
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} else {
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//$2180->WRAM do cause a write to occur (but no read), but the value written is invalid
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_memoryManager->IncMasterClock4();
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_memoryManager->WriteDma(addressBusA, 0xFF, true);
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}
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} else {
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if(addressBusB != 0x2180 || !_memoryManager->IsWorkRam(addressBusA)) {
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uint8_t valToWrite = _memoryManager->ReadDma(addressBusA, true);
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_memoryManager->WriteDma(addressBusB, valToWrite, false);
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} else {
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//WRAM->$2180 does not cause a write to occur
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_memoryManager->IncMasterClock8();
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}
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}
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}
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void DmaController::RunDma(DmaChannelConfig &channel)
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{
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if(!channel.DmaActive) {
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return;
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}
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//"Then perform the DMA: 8 master cycles overhead and 8 master cycles per byte per channel"
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_memoryManager->IncMasterClock8();
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ProcessPendingTransfers();
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const uint8_t *transferOffsets = _transferOffset[channel.TransferMode];
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uint8_t i = 0;
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do {
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//Manual DMA transfers run to the end of the transfer when started
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CopyDmaByte(
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(channel.SrcBank << 16) | channel.SrcAddress,
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0x2100 | (channel.DestAddress + transferOffsets[i & 0x03]),
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channel.InvertDirection
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);
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if(!channel.FixedTransfer) {
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channel.SrcAddress += channel.Decrement ? -1 : 1;
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}
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channel.TransferSize--;
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i++;
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ProcessPendingTransfers();
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} while(channel.TransferSize > 0 && channel.DmaActive);
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channel.DmaActive = false;
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}
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bool DmaController::InitHdmaChannels()
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{
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_hdmaInitPending = false;
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for(int i = 0; i < 8; i++) {
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//Reset internal flags on every frame, whether or not the channels are enabled
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_channel[i].HdmaFinished = false;
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_channel[i].DoTransfer = false; //not resetting this causes graphical glitches in some games (Aladdin, Super Ghouls and Ghosts)
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}
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if(!_hdmaChannels) {
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//No channels are enabled, no more processing needs to be done
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UpdateNeedToProcessFlag();
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return false;
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}
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bool needSync = !HasActiveDmaChannel();
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if(needSync) {
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SyncStartDma();
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}
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_memoryManager->IncMasterClock8();
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for(int i = 0; i < 8; i++) {
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DmaChannelConfig &ch = _channel[i];
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//Set DoTransfer to true for all channels if any HDMA channel is enabled
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ch.DoTransfer = true;
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if(_hdmaChannels & (1 << i)) {
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//"1. Copy AAddress into Address."
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ch.HdmaTableAddress = ch.SrcAddress;
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ch.DmaActive = false;
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//"2. Load $43xA (Line Counter and Repeat) from the table. I believe $00 will terminate this channel immediately."
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ch.HdmaLineCounterAndRepeat = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress, true);
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_memoryManager->IncMasterClock4();
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ch.HdmaTableAddress++;
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if(ch.HdmaLineCounterAndRepeat == 0) {
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ch.HdmaFinished = true;
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}
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//3. Load Indirect Address, if necessary.
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if(ch.HdmaIndirectAddressing) {
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uint8_t lsb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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_memoryManager->IncMasterClock4();
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uint8_t msb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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_memoryManager->IncMasterClock4();
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ch.TransferSize = (msb << 8) | lsb;
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}
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}
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}
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if(needSync) {
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SyncEndDma();
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}
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UpdateNeedToProcessFlag();
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return true;
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}
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void DmaController::RunHdmaTransfer(DmaChannelConfig &channel)
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{
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const uint8_t *transferOffsets = _transferOffset[channel.TransferMode];
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uint8_t transferByteCount = _transferByteCount[channel.TransferMode];
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channel.DmaActive = false;
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uint8_t i = 0;
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if(channel.HdmaIndirectAddressing) {
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do {
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CopyDmaByte(
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(channel.HdmaBank << 16) | channel.TransferSize,
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0x2100 | (channel.DestAddress + transferOffsets[i]),
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channel.InvertDirection
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);
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channel.TransferSize++;
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i++;
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} while(i < transferByteCount);
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} else {
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do {
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CopyDmaByte(
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(channel.SrcBank << 16) | channel.HdmaTableAddress,
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0x2100 | (channel.DestAddress + transferOffsets[i]),
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channel.InvertDirection
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);
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channel.HdmaTableAddress++;
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i++;
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} while(i < transferByteCount);
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}
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}
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void DmaController::SyncStartDma()
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{
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//"after the pause, wait 2-8 master cycles to reach a whole multiple of 8 master cycles since reset"
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_dmaStartClock = _memoryManager->GetMasterClock();
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_memoryManager->IncrementMasterClockValue(8 - (_memoryManager->GetMasterClock() & 0x07));
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}
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void DmaController::SyncEndDma()
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{
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//"Then wait 2-8 master cycles to reach a whole number of CPU Clock cycles since the pause"
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uint8_t cpuSpeed = _memoryManager->GetCpuSpeed();
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_memoryManager->IncrementMasterClockValue(cpuSpeed - ((_memoryManager->GetMasterClock() - _dmaStartClock) % cpuSpeed));
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}
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bool DmaController::HasActiveDmaChannel()
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{
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for(int i = 0; i < 8; i++) {
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if(_channel[i].DmaActive) {
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return true;
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}
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}
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return false;
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}
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bool DmaController::ProcessHdmaChannels()
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{
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_hdmaPending = false;
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if(!_hdmaChannels) {
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UpdateNeedToProcessFlag();
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return false;
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}
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bool needSync = !HasActiveDmaChannel();
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if(needSync) {
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SyncStartDma();
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}
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_memoryManager->IncMasterClock8();
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uint8_t originalActiveChannel = _activeChannel;
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//Run all the DMA transfers for each channel first, before fetching data for the next scanline
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for(int i = 0; i < 8; i++) {
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DmaChannelConfig &ch = _channel[i];
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if((_hdmaChannels & (1 << i)) == 0) {
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continue;
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}
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ch.DmaActive = false;
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if(ch.HdmaFinished) {
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continue;
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}
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//1. If DoTransfer is false, skip to step 3.
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if(ch.DoTransfer) {
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//2. For the number of bytes (1, 2, or 4) required for this Transfer Mode...
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_activeChannel = DmaController::HdmaChannelFlag | i;
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RunHdmaTransfer(ch);
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}
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}
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//Update the channel's state & fetch data for the next scanline
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for(int i = 0; i < 8; i++) {
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DmaChannelConfig &ch = _channel[i];
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if((_hdmaChannels & (1 << i)) == 0 || ch.HdmaFinished) {
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continue;
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}
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//3. Decrement $43xA.
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ch.HdmaLineCounterAndRepeat--;
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//4. Set DoTransfer to the value of Repeat.
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ch.DoTransfer = (ch.HdmaLineCounterAndRepeat & 0x80) != 0;
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//"a. Read the next byte from Address into $43xA (thus, into both Line Counter and Repeat)."
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//This value is discarded if the line counter isn't 0
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uint8_t newCounter = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress, true);
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_memoryManager->IncMasterClock4();
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//5. If Line Counter is zero...
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if((ch.HdmaLineCounterAndRepeat & 0x7F) == 0) {
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ch.HdmaLineCounterAndRepeat = newCounter;
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ch.HdmaTableAddress++;
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//"b. If Addressing Mode is Indirect, read two bytes from Address into Indirect Address(and increment Address by two bytes)."
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if(ch.HdmaIndirectAddressing) {
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if(ch.HdmaLineCounterAndRepeat == 0 && IsLastActiveHdmaChannel(i)) {
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//"One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load one byte for Address,
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//and use the $00 for the low byte.So Address ends up incremented one less than otherwise expected, and one less CPU Cycle is used."
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uint8_t msb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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_memoryManager->IncMasterClock4();
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ch.TransferSize = (msb << 8);
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} else {
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//"If a new indirect address is required, 16 master cycles are taken to load it."
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uint8_t lsb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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_memoryManager->IncMasterClock4();
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uint8_t msb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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_memoryManager->IncMasterClock4();
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ch.TransferSize = (msb << 8) | lsb;
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}
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}
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//"c. If $43xA is zero, terminate this HDMA channel for this frame. The bit in $420c is not cleared, though, so it may be automatically restarted next frame."
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if(ch.HdmaLineCounterAndRepeat == 0) {
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ch.HdmaFinished = true;
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}
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//"d. Set DoTransfer to true."
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ch.DoTransfer = true;
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}
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}
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if(needSync) {
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//If we ran a HDMA transfer, sync
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SyncEndDma();
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}
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_activeChannel = originalActiveChannel;
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UpdateNeedToProcessFlag();
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return true;
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}
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bool DmaController::IsLastActiveHdmaChannel(uint8_t channel)
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{
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for(int i = channel + 1; i < 8; i++) {
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if((_hdmaChannels & (1 << i)) && !_channel[i].HdmaFinished) {
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return false;
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}
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}
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return true;
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}
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void DmaController::UpdateNeedToProcessFlag()
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{
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//Slightly faster execution time by doing this rather than processing all 4 flags on each cycle
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_needToProcess = _hdmaPending || _hdmaInitPending || _dmaStartDelay || _dmaPending;
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}
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void DmaController::BeginHdmaTransfer()
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{
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if(_hdmaChannels) {
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_hdmaPending = true;
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UpdateNeedToProcessFlag();
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}
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}
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void DmaController::BeginHdmaInit()
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{
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_hdmaInitPending = true;
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UpdateNeedToProcessFlag();
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}
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bool DmaController::ProcessPendingTransfers()
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{
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if(!_needToProcess) {
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return false;
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}
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if(_dmaStartDelay) {
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_dmaStartDelay = false;
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return false;
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}
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if(_hdmaPending) {
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return ProcessHdmaChannels();
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} else if(_hdmaInitPending) {
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return InitHdmaChannels();
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} else if(_dmaPending) {
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_dmaPending = false;
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SyncStartDma();
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_memoryManager->IncMasterClock8();
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ProcessPendingTransfers();
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for(int i = 0; i < 8; i++) {
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if(_channel[i].DmaActive) {
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_activeChannel = i;
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RunDma(_channel[i]);
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}
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}
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SyncEndDma();
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UpdateNeedToProcessFlag();
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return true;
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}
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return false;
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}
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void DmaController::Write(uint16_t addr, uint8_t value)
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{
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switch(addr) {
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case 0x420B: {
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//MDMAEN - DMA Enable
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for(int i = 0; i < 8; i++) {
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if(value & (1 << i)) {
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_channel[i].DmaActive = true;
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}
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}
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if(value) {
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_dmaPending = true;
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_dmaStartDelay = true;
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UpdateNeedToProcessFlag();
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}
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break;
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}
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case 0x420C:
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//HDMAEN - HDMA Enable
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_hdmaChannels = value;
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break;
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case 0x4300: case 0x4310: case 0x4320: case 0x4330: case 0x4340: case 0x4350: case 0x4360: case 0x4370:
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{
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//DMAPx - DMA Control for Channel x
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.InvertDirection = (value & 0x80) != 0;
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channel.HdmaIndirectAddressing = (value & 0x40) != 0;
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channel.UnusedFlag = (value & 0x20) != 0;
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channel.Decrement = (value & 0x10) != 0;
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channel.FixedTransfer = (value & 0x08) != 0;
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channel.TransferMode = value & 0x07;
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break;
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}
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case 0x4301: case 0x4311: case 0x4321: case 0x4331: case 0x4341: case 0x4351: case 0x4361: case 0x4371:
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{
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//BBADx - DMA Destination Register for Channel x
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.DestAddress = value;
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break;
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}
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case 0x4302: case 0x4312: case 0x4322: case 0x4332: case 0x4342: case 0x4352: case 0x4362: case 0x4372:
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{
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.SrcAddress = (channel.SrcAddress & 0xFF00) | value;
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break;
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}
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case 0x4303: case 0x4313: case 0x4323: case 0x4333: case 0x4343: case 0x4353: case 0x4363: case 0x4373:
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{
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.SrcAddress = (channel.SrcAddress & 0xFF) | (value << 8);
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break;
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}
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case 0x4304: case 0x4314: case 0x4324: case 0x4334: case 0x4344: case 0x4354: case 0x4364: case 0x4374:
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{
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.SrcBank = value;
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break;
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}
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case 0x4305: case 0x4315: case 0x4325: case 0x4335: case 0x4345: case 0x4355: case 0x4365: case 0x4375:
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{
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//DASxL - DMA Size / HDMA Indirect Address low byte(x = 0 - 7)
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.TransferSize = (channel.TransferSize & 0xFF00) | value;
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break;
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}
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case 0x4306: case 0x4316: case 0x4326: case 0x4336: case 0x4346: case 0x4356: case 0x4366: case 0x4376:
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{
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//DASxL - DMA Size / HDMA Indirect Address low byte(x = 0 - 7)
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.TransferSize = (channel.TransferSize & 0xFF) | (value << 8);
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break;
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}
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case 0x4307: case 0x4317: case 0x4327: case 0x4337: case 0x4347: case 0x4357: case 0x4367: case 0x4377:
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{
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//DASBx - HDMA Indirect Address bank byte (x=0-7)
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.HdmaBank = value;
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break;
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}
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case 0x4308: case 0x4318: case 0x4328: case 0x4338: case 0x4348: case 0x4358: case 0x4368: case 0x4378:
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{
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//A2AxL - HDMA Table Address low byte (x=0-7)
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.HdmaTableAddress = (channel.HdmaTableAddress & 0xFF00) | value;
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break;
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}
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case 0x4309: case 0x4319: case 0x4329: case 0x4339: case 0x4349: case 0x4359: case 0x4369: case 0x4379:
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{
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//A2AxH - HDMA Table Address high byte (x=0-7)
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.HdmaTableAddress = (value << 8) | (channel.HdmaTableAddress & 0xFF);
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break;
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}
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case 0x430A: case 0x431A: case 0x432A: case 0x433A: case 0x434A: case 0x435A: case 0x436A: case 0x437A:
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{
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//DASBx - HDMA Indirect Address bank byte (x=0-7)
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DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
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channel.HdmaLineCounterAndRepeat = value;
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break;
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}
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}
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}
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uint8_t DmaController::Read(uint16_t addr)
|
|
{
|
|
switch(addr) {
|
|
case 0x4300: case 0x4310: case 0x4320: case 0x4330: case 0x4340: case 0x4350: case 0x4360: case 0x4370:
|
|
{
|
|
//DMAPx - DMA Control for Channel x
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return (
|
|
(channel.InvertDirection ? 0x80 : 0) |
|
|
(channel.HdmaIndirectAddressing ? 0x40 : 0) |
|
|
(channel.UnusedFlag ? 0x20 : 0) |
|
|
(channel.Decrement ? 0x10 : 0) |
|
|
(channel.FixedTransfer ? 0x08 : 0) |
|
|
(channel.TransferMode & 0x07)
|
|
);
|
|
}
|
|
|
|
case 0x4301: case 0x4311: case 0x4321: case 0x4331: case 0x4341: case 0x4351: case 0x4361: case 0x4371:
|
|
{
|
|
//BBADx - DMA Destination Register for Channel x
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return channel.DestAddress;
|
|
}
|
|
|
|
case 0x4302: case 0x4312: case 0x4322: case 0x4332: case 0x4342: case 0x4352: case 0x4362: case 0x4372:
|
|
{
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return channel.SrcAddress & 0xFF;
|
|
}
|
|
|
|
case 0x4303: case 0x4313: case 0x4323: case 0x4333: case 0x4343: case 0x4353: case 0x4363: case 0x4373:
|
|
{
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return (channel.SrcAddress >> 8) & 0xFF;
|
|
}
|
|
|
|
case 0x4304: case 0x4314: case 0x4324: case 0x4334: case 0x4344: case 0x4354: case 0x4364: case 0x4374:
|
|
{
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return channel.SrcBank;
|
|
}
|
|
|
|
case 0x4305: case 0x4315: case 0x4325: case 0x4335: case 0x4345: case 0x4355: case 0x4365: case 0x4375:
|
|
{
|
|
//DASxL - DMA Size / HDMA Indirect Address low byte(x = 0 - 7)
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return channel.TransferSize & 0xFF;
|
|
}
|
|
|
|
case 0x4306: case 0x4316: case 0x4326: case 0x4336: case 0x4346: case 0x4356: case 0x4366: case 0x4376:
|
|
{
|
|
//DASxL - DMA Size / HDMA Indirect Address low byte(x = 0 - 7)
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return (channel.TransferSize >> 8) & 0xFF;
|
|
}
|
|
|
|
case 0x4307: case 0x4317: case 0x4327: case 0x4337: case 0x4347: case 0x4357: case 0x4367: case 0x4377:
|
|
{
|
|
//DASBx - HDMA Indirect Address bank byte (x=0-7)
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return channel.HdmaBank;
|
|
}
|
|
|
|
case 0x4308: case 0x4318: case 0x4328: case 0x4338: case 0x4348: case 0x4358: case 0x4368: case 0x4378:
|
|
{
|
|
//A2AxL - HDMA Table Address low byte (x=0-7)
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return channel.HdmaTableAddress & 0xFF;
|
|
}
|
|
|
|
case 0x4309: case 0x4319: case 0x4329: case 0x4339: case 0x4349: case 0x4359: case 0x4369: case 0x4379:
|
|
{
|
|
//A2AxH - HDMA Table Address high byte (x=0-7)
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return (channel.HdmaTableAddress >> 8) & 0xFF;
|
|
}
|
|
|
|
case 0x430A: case 0x431A: case 0x432A: case 0x433A: case 0x434A: case 0x435A: case 0x436A: case 0x437A:
|
|
{
|
|
//DASBx - HDMA Indirect Address bank byte (x=0-7)
|
|
DmaChannelConfig &channel = _channel[(addr & 0x70) >> 4];
|
|
return channel.HdmaLineCounterAndRepeat;
|
|
}
|
|
}
|
|
return _memoryManager->GetOpenBus();
|
|
}
|
|
|
|
uint8_t DmaController::GetActiveChannel()
|
|
{
|
|
return _activeChannel;
|
|
}
|
|
|
|
DmaChannelConfig DmaController::GetChannelConfig(uint8_t channel)
|
|
{
|
|
return _channel[channel];
|
|
}
|
|
|
|
void DmaController::Serialize(Serializer &s)
|
|
{
|
|
s.Stream(_hdmaPending, _hdmaChannels, _dmaPending, _dmaStartClock, _hdmaInitPending, _dmaStartDelay, _needToProcess);
|
|
for(int i = 0; i < 8; i++) {
|
|
s.Stream(
|
|
_channel[i].Decrement, _channel[i].DestAddress, _channel[i].DoTransfer, _channel[i].FixedTransfer,
|
|
_channel[i].HdmaBank, _channel[i].HdmaFinished, _channel[i].HdmaIndirectAddressing,
|
|
_channel[i].HdmaLineCounterAndRepeat, _channel[i].HdmaTableAddress,
|
|
_channel[i].InvertDirection, _channel[i].SrcAddress, _channel[i].SrcBank, _channel[i].TransferMode,
|
|
_channel[i].TransferSize, _channel[i].UnusedFlag, _channel[i].DmaActive
|
|
);
|
|
}
|
|
}
|