mirror of
https://github.com/SourMesen/Mesen-S.git
synced 2024-06-23 14:52:12 -04:00
6539b92502
Memory handlers did not have the _memoryType value set, which caused some memory accesses to be much faster than expected
481 lines
14 KiB
C++
481 lines
14 KiB
C++
#include "stdafx.h"
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#include "Cx4.h"
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#include "Console.h"
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#include "Cpu.h"
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#include "MemoryManager.h"
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#include "MemoryMappings.h"
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#include "BaseCartridge.h"
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#include "EmuSettings.h"
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#include "RamHandler.h"
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#include "../Utilities/HexUtilities.h"
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//TODO: Proper open bus behavior (and return 0s for missing save ram, too)
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//TODO: CPU shouldn't have access to PRG ROM while the CX4 is loading from PRG ROM
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//TODO: Timings are apparently not perfect (desync in MMX2 intro)
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Cx4::Cx4(Console* console) : BaseCoprocessor(SnesMemoryType::Register)
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{
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_console = console;
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_memoryType = SnesMemoryType::Register;
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_memoryManager = console->GetMemoryManager().get();
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_cpu = console->GetCpu().get();
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console->GetSettings()->InitializeRam(_dataRam, Cx4::DataRamSize);
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auto &prgRomHandlers = console->GetCartridge()->GetPrgRomHandlers();
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auto &saveRamHandlers = console->GetCartridge()->GetSaveRamHandlers();
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MemoryMappings* cpuMappings = _memoryManager->GetMemoryMappings();
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//PRG ROM
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uint8_t bankCount = console->GetSettings()->GetEmulationConfig().EnableStrictBoardMappings ? 0x3F : 0x7F;
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cpuMappings->RegisterHandler(0x00, std::min<uint8_t>(0x7D, bankCount), 0x8000, 0xFFFF, prgRomHandlers);
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cpuMappings->RegisterHandler(0x80, 0x80 + bankCount, 0x8000, 0xFFFF, prgRomHandlers);
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_mappings.RegisterHandler(0x00, bankCount, 0x8000, 0xFFFF, prgRomHandlers);
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_mappings.RegisterHandler(0x80, 0x80 + bankCount, 0x8000, 0xFFFF, prgRomHandlers);
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//Save RAM
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cpuMappings->RegisterHandler(0x70, 0x7D, 0x0000, 0x7FFF, saveRamHandlers);
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cpuMappings->RegisterHandler(0xF0, 0xFF, 0x0000, 0x7FFF, saveRamHandlers);
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_mappings.RegisterHandler(0x70, 0x7D, 0x0000, 0x7FFF, saveRamHandlers);
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_mappings.RegisterHandler(0xF0, 0xFF, 0x0000, 0x7FFF, saveRamHandlers);
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//Registers
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cpuMappings->RegisterHandler(0x00, 0x3F, 0x6000, 0x7FFF, this);
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cpuMappings->RegisterHandler(0x80, 0xBF, 0x6000, 0x7FFF, this);
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_mappings.RegisterHandler(0x00, 0x3F, 0x6000, 0x7FFF, this);
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_mappings.RegisterHandler(0x80, 0xBF, 0x6000, 0x7FFF, this);
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_clockRatio = (double)20000000 / console->GetMasterClockRate();
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Reset();
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}
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void Cx4::Reset()
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{
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_state = {};
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_state.Stopped = true;
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_state.SingleRom = true;
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_state.RomAccessDelay = 3;
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_state.RamAccessDelay = 3;
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}
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void Cx4::Run()
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{
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uint64_t targetCycle = (uint64_t)(_memoryManager->GetMasterClock() * _clockRatio);
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while(_state.CycleCount < targetCycle) {
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if(_state.Locked) {
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Step(1);
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} else if(_state.Suspend.Enabled) {
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if(_state.Suspend.Duration == 0) {
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Step(1);
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} else {
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Step(1);
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_state.Suspend.Duration--;
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if(_state.Suspend.Duration == 0) {
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_state.Suspend.Enabled = false;
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}
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}
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} else if(_state.Cache.Enabled) {
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ProcessCache(targetCycle);
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} else if(_state.Dma.Enabled) {
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ProcessDma(targetCycle);
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} else if(_state.Stopped) {
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Step(targetCycle - _state.CycleCount);
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} else if(!ProcessCache(targetCycle)) {
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if(!_state.Cache.Enabled) {
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//Cache operation required, but both caches are locked, stop
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Stop();
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}
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} else {
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uint16_t opCode = _prgRam[_state.Cache.Page][_state.PC];
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_console->ProcessMemoryRead<CpuType::Cx4>(0, 0, MemoryOperationType::ExecOpCode);
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_state.PC++;
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if(_state.PC == 0) {
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//If execution reached the end of the page, start loading the next page
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//This must be done BEFORE running the instruction (otherwise a jump/branch to address 0 will trigger this)
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SwitchCachePage();
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}
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Exec(opCode);
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}
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}
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}
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void Cx4::Step(uint64_t cycles)
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{
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if(_state.Bus.Enabled) {
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if(_state.Bus.DelayCycles > cycles) {
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_state.Bus.DelayCycles -= (uint8_t)cycles;
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} else {
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_state.Bus.Enabled = false;
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_state.Bus.DelayCycles = 0;
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if(_state.Bus.Reading) {
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_state.MemoryDataReg = ReadCx4(_state.Bus.Address);
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_state.Bus.Reading = false;
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}
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if(_state.Bus.Writing) {
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WriteCx4(_state.Bus.Address, _state.MemoryDataReg);
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_state.Bus.Writing = false;
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}
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}
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}
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_state.CycleCount += cycles;
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}
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void Cx4::SwitchCachePage()
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{
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if(_state.Cache.Page == 1) {
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Stop();
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return;
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}
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_state.Cache.Page = 1;
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if(_state.Cache.Lock[1]) {
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Stop();
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return;
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}
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_state.PB = _state.P;
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uint64_t targetCycle = (uint64_t)(_memoryManager->GetMasterClock() * _clockRatio);
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if(!ProcessCache(targetCycle) && !_state.Cache.Enabled) {
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Stop();
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}
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}
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bool Cx4::ProcessCache(uint64_t targetCycle)
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{
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uint32_t address = (_state.Cache.Base + (_state.PB << 9)) & 0xFFFFFF;
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if(_state.Cache.Pos == 0) {
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if(_state.Cache.Address[_state.Cache.Page] == address) {
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//Current cache page matches the needed address, keep using it
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_state.Cache.Enabled = false;
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return true;
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}
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//Check if the other page matches
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_state.Cache.Page ^= 1;
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if(_state.Cache.Address[_state.Cache.Page] == address) {
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//The other cache page matches, use it
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_state.Cache.Enabled = false;
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return true;
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}
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if(_state.Cache.Lock[_state.Cache.Page]) {
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//If it's locked, use the other page
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_state.Cache.Page ^= 1;
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}
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if(_state.Cache.Lock[_state.Cache.Page]) {
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//The both pages are locked, and the cache is invalid, give up.
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_state.Cache.Enabled = false;
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return false;
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}
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_state.Cache.Enabled = true;
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}
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//Populate the cache
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while(_state.Cache.Pos < 256) {
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uint8_t lsb = ReadCx4(address + (_state.Cache.Pos * 2));
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Step(GetAccessDelay(address + (_state.Cache.Pos * 2)));
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uint8_t msb = ReadCx4(address + (_state.Cache.Pos * 2) + 1);
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Step(GetAccessDelay(address + (_state.Cache.Pos * 2) + 1));
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_prgRam[_state.Cache.Page][_state.Cache.Pos] = (msb << 8) | lsb;
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_state.Cache.Pos++;
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if(_state.CycleCount > targetCycle) {
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break;
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}
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}
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if(_state.Cache.Pos >= 256) {
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_state.Cache.Address[_state.Cache.Page] = address;
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_state.Cache.Pos = 0;
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_state.Cache.Enabled = false;
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return true;
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}
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//Cache loading is not finished
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return false;
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}
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void Cx4::ProcessDma(uint64_t targetCycle)
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{
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while(_state.Dma.Pos < _state.Dma.Length) {
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uint32_t src = (_state.Dma.Source + _state.Dma.Pos) & 0xFFFFFF;
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uint32_t dest = (_state.Dma.Dest + _state.Dma.Pos) & 0xFFFFFF;
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IMemoryHandler *srcHandler = _mappings.GetHandler(src);
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IMemoryHandler *destHandler = _mappings.GetHandler(dest);
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if(!srcHandler || !destHandler || srcHandler->GetMemoryType() == destHandler->GetMemoryType() || destHandler->GetMemoryType() == SnesMemoryType::PrgRom) {
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//Invalid DMA, the chip is locked until it gets restarted by a write to $7F53
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_state.Locked = true;
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_state.Dma.Pos = 0;
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_state.Dma.Enabled = false;
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return;
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}
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Step(GetAccessDelay(src));
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uint8_t value = ReadCx4(src);
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Step(GetAccessDelay(dest));
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WriteCx4(dest, value);
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_state.Dma.Pos++;
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if(_state.CycleCount > targetCycle) {
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break;
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}
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}
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if(_state.Dma.Pos >= _state.Dma.Length) {
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_state.Dma.Pos = 0;
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_state.Dma.Enabled = false;
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}
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}
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uint8_t Cx4::GetAccessDelay(uint32_t addr)
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{
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IMemoryHandler* handler = _mappings.GetHandler(addr);
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if(handler->GetMemoryType() == SnesMemoryType::PrgRom) {
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return 1 + _state.RomAccessDelay;
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} else if(handler->GetMemoryType() == SnesMemoryType::SaveRam) {
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return 1 + _state.RamAccessDelay;
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}
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return 1;
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}
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uint8_t Cx4::ReadCx4(uint32_t addr)
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{
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IMemoryHandler* handler = _mappings.GetHandler(addr);
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if(handler) {
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uint8_t value = handler->Read(addr);
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_console->ProcessMemoryRead<CpuType::Cx4>(addr, value, MemoryOperationType::Read);
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return value;
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}
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return 0;
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}
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void Cx4::WriteCx4(uint32_t addr, uint8_t value)
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{
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IMemoryHandler* handler = _mappings.GetHandler(addr);
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if(handler) {
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_console->ProcessMemoryWrite<CpuType::Cx4>(addr, value, MemoryOperationType::Write);
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handler->Write(addr, value);
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}
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}
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uint8_t Cx4::Read(uint32_t addr)
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{
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addr = 0x7000 | (addr & 0xFFF);
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if(addr <= 0x7BFF) {
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return _dataRam[addr & 0xFFF];
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} else if(addr >= 0x7F60 && addr <= 0x7F7F) {
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return _state.Vectors[addr & 0x1F];
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} else if((addr >= 0x7F80 && addr <= 0x7FAF) || (addr >= 0x7FC0 && addr <= 0x7FEF)) {
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addr &= 0x3F;
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uint32_t ® = _state.Regs[addr / 3];
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switch(addr % 3) {
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case 0: return reg;
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case 1: return reg >> 8;
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case 2: return reg >> 16;
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}
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} else if(addr >= 0x7F53 && addr <= 0x7F5F) {
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return (uint8_t)_state.Suspend.Enabled | ((uint8_t)_state.IrqFlag << 1) | ((uint8_t)IsRunning() << 6) | ((uint8_t)IsBusy() << 7);
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}
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switch(addr) {
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case 0x7F40: return _state.Dma.Source;
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case 0x7F41: return _state.Dma.Source >> 8;
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case 0x7F42: return _state.Dma.Source >> 16;
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case 0x7F43: return (uint8_t)_state.Dma.Length;
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case 0x7F44: return _state.Dma.Length >> 8;
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case 0x7F45: return _state.Dma.Dest;
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case 0x7F46: return _state.Dma.Dest >> 8;
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case 0x7F47: return _state.Dma.Dest >> 16;
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case 0x7F48: return _state.Cache.Page;
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case 0x7F49: return _state.Cache.Base;
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case 0x7F4A: return _state.Cache.Base >> 8;
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case 0x7F4B: return _state.Cache.Base >> 16;
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case 0x7F4C: return (uint8_t)_state.Cache.Lock[0] | ((uint8_t)_state.Cache.Lock[1] << 1);
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case 0x7F4D: return (uint8_t)_state.Cache.ProgramBank;
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case 0x7F4E: return _state.Cache.ProgramBank >> 8;
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case 0x7F4F: return _state.Cache.ProgramCounter;
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case 0x7F50: return _state.RamAccessDelay | (_state.RomAccessDelay << 4);
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case 0x7F51: return _state.IrqDisabled;
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case 0x7F52: return _state.SingleRom;
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}
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return 0;
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}
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void Cx4::Write(uint32_t addr, uint8_t value)
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{
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addr = 0x7000 | (addr & 0xFFF);
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if(addr <= 0x7BFF) {
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_dataRam[addr & 0xFFF] = value;
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return;
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}
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if(addr >= 0x7F60 && addr <= 0x7F7F) {
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_state.Vectors[addr & 0x1F] = value;
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} else if((addr >= 0x7F80 && addr <= 0x7FAF) || (addr >= 0x7FC0 && addr <= 0x7FEF)) {
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addr &= 0x3F;
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uint32_t ® = _state.Regs[addr / 3];
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switch(addr % 3) {
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case 0: reg = (reg & 0xFFFF00) | value; break;
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case 1: reg = (reg & 0xFF00FF) | (value << 8); break;
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case 2: reg = (reg & 0x00FFFF) | (value << 16); break;
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}
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} else if(addr >= 0x7F55 && addr <= 0x7F5C) {
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_state.Suspend.Enabled = true;
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_state.Suspend.Duration = (addr - 0x7F55) * 32;
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} else {
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switch(addr) {
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case 0x7F40: _state.Dma.Source = (_state.Dma.Source & 0xFFFF00) | value; break;
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case 0x7F41: _state.Dma.Source = (_state.Dma.Source & 0xFF00FF) | (value << 8); break;
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case 0x7F42: _state.Dma.Source = (_state.Dma.Source & 0x00FFFF) | (value << 16); break;
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case 0x7F43: _state.Dma.Length = (_state.Dma.Length & 0xFF00) | value; break;
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case 0x7F44: _state.Dma.Length = (_state.Dma.Length & 0x00FF) | (value << 8); break;
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case 0x7F45: _state.Dma.Dest = (_state.Dma.Dest & 0xFFFF00) | value; break;
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case 0x7F46: _state.Dma.Dest = (_state.Dma.Dest & 0xFF00FF) | (value << 8); break;
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case 0x7F47:
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_state.Dma.Dest = (_state.Dma.Dest & 0x00FFFF) | (value << 16);
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if(_state.Stopped) {
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_state.Dma.Enabled = true;
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}
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break;
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case 0x7F48:
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_state.Cache.Page = value & 0x01;
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if(_state.Stopped) {
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_state.Cache.Enabled = true;
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}
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break;
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case 0x7F49: _state.Cache.Base = (_state.Cache.Base & 0xFFFF00) | value; break;
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case 0x7F4A: _state.Cache.Base = (_state.Cache.Base & 0xFF00FF) | (value << 8); break;
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case 0x7F4B: _state.Cache.Base = (_state.Cache.Base & 0x00FFFF) | (value << 16); break;
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case 0x7F4C:
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_state.Cache.Lock[0] = (value & 0x01) != 0;
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_state.Cache.Lock[1] = (value & 0x02) != 0;
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break;
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case 0x7F4D: _state.Cache.ProgramBank = (_state.Cache.ProgramBank & 0xFF00) | value; break;
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case 0x7F4E: _state.Cache.ProgramBank = (_state.Cache.ProgramBank & 0x00FF) | ((value & 0x7F) << 8); break;
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case 0x7F4F:
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_state.Cache.ProgramCounter = value;
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if(_state.Stopped) {
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_state.Stopped = false;
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_state.PB = _state.Cache.ProgramBank;
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_state.PC = _state.Cache.ProgramCounter;
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}
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break;
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case 0x7F50:
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_state.RamAccessDelay = value & 0x07;
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_state.RomAccessDelay = (value >> 4) & 0x07;
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break;
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case 0x7F51:
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_state.IrqDisabled = value & 0x01;
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if(_state.IrqDisabled) {
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_state.IrqFlag = true;
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_cpu->ClearIrqSource(IrqSource::Coprocessor);
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}
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break;
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case 0x7F52: _state.SingleRom = (value & 0x01) != 0; break;
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case 0x7F53:
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_state.Locked = false;
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_state.Stopped = true;
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break;
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case 0x7F5D: _state.Suspend.Enabled = false; break;
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case 0x7F5E:
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//Clear IRQ flag in CX4, but keeps IRQ signal high
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_state.IrqFlag = false;
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break;
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}
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}
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}
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bool Cx4::IsRunning()
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{
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return IsBusy() || !_state.Stopped;
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}
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bool Cx4::IsBusy()
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{
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return _state.Cache.Enabled || _state.Dma.Enabled || _state.Bus.DelayCycles > 0;
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}
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void Cx4::Serialize(Serializer &s)
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{
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s.Stream(
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_state.CycleCount, _state.PB, _state.PC, _state.A, _state.P, _state.SP, _state.Mult, _state.RomBuffer,
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_state.RamBuffer[0], _state.RamBuffer[1], _state.RamBuffer[2], _state.MemoryDataReg, _state.MemoryAddressReg,
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_state.DataPointerReg, _state.Negative, _state.Zero, _state.Carry, _state.Overflow, _state.IrqFlag, _state.Stopped,
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_state.Locked, _state.IrqDisabled, _state.SingleRom, _state.RamAccessDelay, _state.RomAccessDelay, _state.Bus.Address,
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_state.Bus.DelayCycles, _state.Bus.Enabled, _state.Bus.Reading, _state.Bus.Writing, _state.Dma.Dest, _state.Dma.Enabled,
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_state.Dma.Length, _state.Dma.Source, _state.Dma.Pos, _state.Suspend.Duration, _state.Suspend.Enabled, _state.Cache.Enabled,
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_state.Cache.Lock[0], _state.Cache.Lock[1], _state.Cache.Address[0], _state.Cache.Address[1], _state.Cache.Base,
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_state.Cache.Page, _state.Cache.ProgramBank, _state.Cache.ProgramCounter, _state.Cache.Pos
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);
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s.StreamArray(_state.Stack, 8);
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s.StreamArray(_state.Regs, 16);
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s.StreamArray(_state.Vectors, 0x20);
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s.StreamArray(_prgRam[0], 256);
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s.StreamArray(_prgRam[1], 256);
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s.StreamArray(_dataRam, Cx4::DataRamSize);
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}
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|
uint8_t Cx4::Peek(uint32_t addr)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void Cx4::PeekBlock(uint32_t addr, uint8_t* output)
|
|
{
|
|
memset(output, 0, 0x1000);
|
|
}
|
|
|
|
AddressInfo Cx4::GetAbsoluteAddress(uint32_t address)
|
|
{
|
|
return { -1, SnesMemoryType::Register };
|
|
}
|
|
|
|
MemoryMappings* Cx4::GetMemoryMappings()
|
|
{
|
|
return &_mappings;
|
|
}
|
|
|
|
uint8_t* Cx4::DebugGetDataRam()
|
|
{
|
|
return _dataRam;
|
|
}
|
|
|
|
uint32_t Cx4::DebugGetDataRamSize()
|
|
{
|
|
return Cx4::DataRamSize;
|
|
}
|
|
|
|
Cx4State Cx4::GetState()
|
|
{
|
|
return _state;
|
|
} |