mirror of
https://github.com/SourMesen/Mesen-S.git
synced 2024-06-23 14:52:12 -04:00
224 lines
11 KiB
C++
224 lines
11 KiB
C++
#include "stdafx.h"
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#include "CpuDisUtils.h"
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#include "CpuTypes.h"
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#include "Cpu.h"
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#include "Console.h"
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#include "EmuSettings.h"
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#include "DisassemblyInfo.h"
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#include "LabelManager.h"
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#include "DummyCpu.h"
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#include "../Utilities/HexUtilities.h"
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#include "../Utilities/FastString.h"
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void CpuDisUtils::GetDisassembly(DisassemblyInfo &info, string &out, uint32_t memoryAddr, LabelManager* labelManager, EmuSettings* settings)
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{
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FastString str(settings->CheckDebuggerFlag(DebuggerFlags::UseLowerCaseDisassembly));
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uint8_t opCode = info.GetOpCode();
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AddrMode addrMode = CpuDisUtils::OpMode[opCode];
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str.Write(CpuDisUtils::OpName[opCode]);
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str.Write(' ');
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uint32_t opAddr = CpuDisUtils::GetOperandAddress(info, memoryAddr);
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uint32_t opSize = info.GetOpSize();
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FastString operand(settings->CheckDebuggerFlag(DebuggerFlags::UseLowerCaseDisassembly));
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if(opSize > 1) {
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if(addrMode == AddrMode::Rel || addrMode == AddrMode::RelLng || opSize == 4) {
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AddressInfo address { (int32_t)opAddr, SnesMemoryType::CpuMemory };
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string label = labelManager ? labelManager->GetLabel(address) : "";
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if(label.size()) {
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operand.Write(label, true);
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} else {
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operand.WriteAll('$', HexUtilities::ToHex24(opAddr));
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}
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} else if(opSize == 2) {
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operand.WriteAll('$', HexUtilities::ToHex((uint8_t)opAddr));
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} else if(opSize == 3) {
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operand.WriteAll('$', HexUtilities::ToHex((uint16_t)opAddr));
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}
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}
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switch(addrMode) {
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case AddrMode::Abs: str.Write(operand); break;
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case AddrMode::AbsJmp: str.Write(operand); break;
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case AddrMode::AbsIdxXInd: str.WriteAll('(', operand, ",X)"); break;
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case AddrMode::AbsIdxX: str.WriteAll(operand, ",X"); break;
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case AddrMode::AbsIdxY: str.WriteAll(operand, ",Y"); break;
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case AddrMode::AbsInd: str.WriteAll('(', operand, ')'); break;
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case AddrMode::AbsIndLng: str.WriteAll('[', operand, ']'); break;
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case AddrMode::AbsLngIdxX: str.WriteAll(operand, ",X"); break;
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case AddrMode::AbsLng: str.Write(operand); break;
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case AddrMode::AbsLngJmp: str.Write(operand); break;
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case AddrMode::Acc: break;
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case AddrMode::BlkMov: str.WriteAll('$', operand[1], operand[2], ','); str.WriteAll('$', operand[3], operand[4]); break;
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case AddrMode::DirIdxIndX: str.WriteAll('(', operand, ",X)"); break;
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case AddrMode::DirIdxX: str.WriteAll(operand, ",X"); break;
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case AddrMode::DirIdxY: str.WriteAll(operand, ",Y"); break;
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case AddrMode::DirIndIdxY: str.WriteAll("(", operand, "),Y"); break;
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case AddrMode::DirIndLngIdxY: str.WriteAll("[", operand, "],Y"); break;
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case AddrMode::DirIndLng: str.WriteAll("[", operand, "]"); break;
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case AddrMode::DirInd: str.WriteAll("(", operand, ")"); break;
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case AddrMode::Dir: str.Write(operand); break;
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case AddrMode::Imm8: case AddrMode::Imm16: case AddrMode::ImmX: case AddrMode::ImmM:
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str.WriteAll('#', operand);
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break;
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case AddrMode::Sig8: str.WriteAll('#', operand); break; //BRK/COP signature
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case AddrMode::Imp: break;
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case AddrMode::RelLng: str.Write(operand); break;
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case AddrMode::Rel: str.Write(operand); break;
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case AddrMode::Stk: break;
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case AddrMode::StkRel: str.WriteAll(operand, ",S"); break;
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case AddrMode::StkRelIndIdxY: str.WriteAll('(', operand, ",S),Y"); break;
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default: throw std::runtime_error("invalid address mode");
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}
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out += str.ToString();
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}
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uint32_t CpuDisUtils::GetOperandAddress(DisassemblyInfo &info, uint32_t memoryAddr)
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{
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uint32_t opSize = info.GetOpSize();
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uint32_t opAddr = 0;
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uint8_t* byteCode = info.GetByteCode();
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if(opSize == 2) {
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opAddr = byteCode[1];
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} else if(opSize == 3) {
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opAddr = byteCode[1] | (byteCode[2] << 8);
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} else if(opSize == 4) {
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opAddr = byteCode[1] | (byteCode[2] << 8) | (byteCode[3] << 16);
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}
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AddrMode addrMode = CpuDisUtils::OpMode[byteCode[0]];
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if(addrMode == AddrMode::Rel || addrMode == AddrMode::RelLng) {
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if(opSize == 2) {
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opAddr = (memoryAddr & 0xFF0000) | (((int8_t)opAddr + memoryAddr + 2) & 0xFFFF);
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} else {
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opAddr = (memoryAddr & 0xFF0000) | (((int16_t)opAddr + memoryAddr + 3) & 0xFFFF);
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}
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}
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return opAddr;
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}
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int32_t CpuDisUtils::GetEffectiveAddress(DisassemblyInfo &info, Console *console, CpuState &state, CpuType type)
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{
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if(HasEffectiveAddress(CpuDisUtils::OpMode[info.GetOpCode()])) {
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DummyCpu cpu(console, type);
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state.PS &= ~(ProcFlags::IndexMode8 | ProcFlags::MemoryMode8);
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state.PS |= info.GetFlags();
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cpu.SetDummyState(state);
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cpu.Exec();
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return cpu.GetLastOperand();
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}
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return -1;
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}
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bool CpuDisUtils::HasEffectiveAddress(AddrMode addrMode)
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{
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switch(addrMode) {
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case AddrMode::Acc:
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case AddrMode::Imp:
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case AddrMode::Stk:
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case AddrMode::Sig8:
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case AddrMode::Imm8:
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case AddrMode::Rel:
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case AddrMode::RelLng:
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case AddrMode::Imm16:
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case AddrMode::BlkMov:
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case AddrMode::AbsLngJmp:
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case AddrMode::AbsLng:
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case AddrMode::ImmX:
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case AddrMode::ImmM:
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case AddrMode::AbsJmp:
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return false;
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case AddrMode::DirIdxIndX:
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case AddrMode::DirIdxX:
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case AddrMode::DirIdxY:
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case AddrMode::DirIndIdxY:
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case AddrMode::DirIndLngIdxY:
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case AddrMode::DirIndLng:
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case AddrMode::DirInd:
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case AddrMode::Dir:
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case AddrMode::StkRel:
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case AddrMode::StkRelIndIdxY:
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case AddrMode::Abs:
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case AddrMode::AbsIdxXInd:
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case AddrMode::AbsIdxX:
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case AddrMode::AbsIdxY:
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case AddrMode::AbsLngIdxX:
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case AddrMode::AbsInd:
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case AddrMode::AbsIndLng:
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return true;
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}
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throw std::runtime_error("Invalid mode");
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}
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uint8_t CpuDisUtils::GetOpSize(AddrMode addrMode, uint8_t flags)
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{
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if(addrMode == AddrMode::ImmX) {
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return (flags & ProcFlags::IndexMode8) ? 2 : 3;
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} else if(addrMode == AddrMode::ImmM) {
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return (flags & ProcFlags::MemoryMode8) ? 2 : 3;
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}
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return CpuDisUtils::OpSize[(int)addrMode];
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}
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uint8_t CpuDisUtils::GetOpSize(uint8_t opCode, uint8_t flags)
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{
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return GetOpSize(CpuDisUtils::OpMode[opCode], flags);
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}
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uint8_t CpuDisUtils::OpSize[0x1F] = {
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2, 2, 3, 0, 0, 3, 3, 3, 3, 3,
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3, 4, 4, 3, 4, 1, 3, 2, 2, 2,
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2, 2, 2, 2, 2, 1, 3, 2, 1, 2,
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2
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};
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string CpuDisUtils::OpName[256] = {
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//0 1 2 3 4 5 6 7 8 9 A B C D E F
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"BRK", "ORA", "COP", "ORA", "TSB", "ORA", "ASL", "ORA", "PHP", "ORA", "ASL", "PHD", "TSB", "ORA", "ASL", "ORA", // 0
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"BPL", "ORA", "ORA", "ORA", "TRB", "ORA", "ASL", "ORA", "CLC", "ORA", "INC", "TCS", "TRB", "ORA", "ASL", "ORA", // 1
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"JSR", "AND", "JSL", "AND", "BIT", "AND", "ROL", "AND", "PLP", "AND", "ROL", "PLD", "BIT", "AND", "ROL", "AND", // 2
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"BMI", "AND", "AND", "AND", "BIT", "AND", "ROL", "AND", "SEC", "AND", "DEC", "TSC", "BIT", "AND", "ROL", "AND", // 3
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"RTI", "EOR", "WDM", "EOR", "MVP", "EOR", "LSR", "EOR", "PHA", "EOR", "LSR", "PHK", "JMP", "EOR", "LSR", "EOR", // 4
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"BVC", "EOR", "EOR", "EOR", "MVN", "EOR", "LSR", "EOR", "CLI", "EOR", "PHY", "TCD", "JMP", "EOR", "LSR", "EOR", // 5
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"RTS", "ADC", "PER", "ADC", "STZ", "ADC", "ROR", "ADC", "PLA", "ADC", "ROR", "RTL", "JMP", "ADC", "ROR", "ADC", // 6
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"BVS", "ADC", "ADC", "ADC", "STZ", "ADC", "ROR", "ADC", "SEI", "ADC", "PLY", "TDC", "JMP", "ADC", "ROR", "ADC", // 7
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"BRA", "STA", "BRL", "STA", "STY", "STA", "STX", "STA", "DEY", "BIT", "TXA", "PHB", "STY", "STA", "STX", "STA", // 8
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"BCC", "STA", "STA", "STA", "STY", "STA", "STX", "STA", "TYA", "STA", "TXS", "TXY", "STZ", "STA", "STZ", "STA", // 9
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"LDY", "LDA", "LDX", "LDA", "LDY", "LDA", "LDX", "LDA", "TAY", "LDA", "TAX", "PLB", "LDY", "LDA", "LDX", "LDA", // A
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"BCS", "LDA", "LDA", "LDA", "LDY", "LDA", "LDX", "LDA", "CLV", "LDA", "TSX", "TYX", "LDY", "LDA", "LDX", "LDA", // B
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"CPY", "CMP", "REP", "CMP", "CPY", "CMP", "DEC", "CMP", "INY", "CMP", "DEX", "WAI", "CPY", "CMP", "DEC", "CMP", // C
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"BNE", "CMP", "CMP", "CMP", "PEI", "CMP", "DEC", "CMP", "CLD", "CMP", "PHX", "STP", "JML", "CMP", "DEC", "CMP", // D
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"CPX", "SBC", "SEP", "SBC", "CPX", "SBC", "INC", "SBC", "INX", "SBC", "NOP", "XBA", "CPX", "SBC", "INC", "SBC", // E
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"BEQ", "SBC", "SBC", "SBC", "PEA", "SBC", "INC", "SBC", "SED", "SBC", "PLX", "XCE", "JSR", "SBC", "INC", "SBC" // F
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};
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typedef AddrMode M;
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AddrMode CpuDisUtils::OpMode[256] = {
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//0 1 2 3 4 5 6 7 8 9 A B C D E F
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M::Sig8, M::DirIdxIndX, M::Sig8, M::StkRel, M::Dir, M::Dir, M::Dir, M::DirIndLng, M::Stk, M::ImmM, M::Acc, M::Stk, M::Abs, M::Abs, M::Abs, M::AbsLng, // 0
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::Dir, M::DirIdxX, M::DirIdxX, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Acc, M::Imp, M::Abs, M::AbsIdxX, M::AbsIdxX, M::AbsLngIdxX, // 1
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M::Abs, M::DirIdxIndX, M::AbsLng, M::StkRel, M::Dir, M::Dir, M::Dir, M::DirIndLng, M::Stk, M::ImmM, M::Acc, M::Stk, M::Abs, M::Abs, M::Abs, M::AbsLng, // 2
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::DirIdxX, M::DirIdxX, M::DirIdxX, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Acc, M::Imp, M::AbsIdxX, M::AbsIdxX, M::AbsIdxX, M::AbsLngIdxX, // 3
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M::Stk, M::DirIdxIndX, M::Imm8, M::StkRel, M::BlkMov, M::Dir, M::Dir, M::DirIndLng, M::Stk, M::ImmM, M::Acc, M::Stk, M::Abs, M::Abs, M::Abs, M::AbsLng, // 4
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::BlkMov, M::DirIdxX, M::DirIdxX, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Stk, M::Imp, M::AbsLng, M::AbsIdxX, M::AbsIdxX, M::AbsLngIdxX, // 5
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M::Stk, M::DirIdxIndX, M::RelLng, M::StkRel, M::Dir, M::Dir, M::Dir, M::DirIndLng, M::Stk, M::ImmM, M::Acc, M::Stk, M::AbsInd, M::Abs, M::Abs, M::AbsLng, // 6
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::DirIdxX, M::DirIdxX, M::DirIdxX, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Stk, M::Imp, M::AbsIdxXInd, M::AbsIdxX, M::AbsIdxX, M::AbsLngIdxX, // 7
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M::Rel, M::DirIdxIndX, M::RelLng, M::StkRel, M::Dir, M::Dir, M::Dir, M::DirIndLng, M::Imp, M::ImmM, M::Imp, M::Stk, M::Abs, M::Abs, M::Abs, M::AbsLng, // 8
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::DirIdxX, M::DirIdxX, M::DirIdxY, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Imp, M::Imp, M::Abs, M::AbsIdxX, M::AbsIdxX, M::AbsLngIdxX, // 9
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M::ImmX, M::DirIdxIndX, M::ImmX, M::StkRel, M::Dir, M::Dir, M::Dir, M::DirIndLng, M::Imp, M::ImmM, M::Imp, M::Stk, M::Abs, M::Abs, M::Abs, M::AbsLng, // A
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::DirIdxX, M::DirIdxX, M::DirIdxY, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Imp, M::Imp, M::AbsIdxX, M::AbsIdxX, M::AbsIdxY, M::AbsLngIdxX, // B
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M::ImmX, M::DirIdxIndX, M::Imm8, M::StkRel, M::Dir, M::Dir, M::Dir, M::DirIndLng, M::Imp, M::ImmM, M::Imp, M::Imp, M::Abs, M::Abs, M::Abs, M::AbsLng, // C
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::Dir, M::DirIdxX, M::DirIdxX, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Stk, M::Imp, M::AbsIndLng, M::AbsIdxX, M::AbsIdxX, M::AbsLngIdxX, // D
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M::ImmX, M::DirIdxIndX, M::Imm8, M::StkRel, M::Dir, M::Dir, M::Dir, M::DirIndLng, M::Imp, M::ImmM, M::Imp, M::Imp, M::Abs, M::Abs, M::Abs, M::AbsLng, // E
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M::Rel, M::DirIndIdxY, M::DirInd, M::StkRelIndIdxY, M::Imm16, M::DirIdxX, M::DirIdxX, M::DirIndLngIdxY, M::Imp, M::AbsIdxY, M::Stk, M::Imp, M::AbsIdxXInd, M::AbsIdxX, M::AbsIdxX, M::AbsLngIdxX // F
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}; |