From 04a71f1da60e51f277d4979c698e52cacb028666 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Mon, 14 Sep 2020 15:06:35 +0800 Subject: [PATCH 10/49] MLK-24770: drm: mhdp: Sync DPTX capability with Cadence sample code Sync the max vswing and pre-emphasis setting with Cadence sample code. The max vswing is VOLTAGE_LEVEL_3 and the max pre-emphasis is PRE_EMPHASIS_LEVEL_2 now. Signed-off-by: Sandor Yu Reviewed-by: Robby Cai --- drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c index 890add9b7c67..2043016f176b 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c @@ -445,8 +445,8 @@ int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp) msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate); msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN; - msg[2] = VOLTAGE_LEVEL_2; - msg[3] = PRE_EMPHASIS_LEVEL_3; + msg[2] = VOLTAGE_LEVEL_3; + msg[3] = PRE_EMPHASIS_LEVEL_2; msg[4] = PTS1 | PTS2 | PTS3 | PTS4; msg[5] = FAST_LT_NOT_SUPPORT; msg[6] = mhdp->lane_mapping; -- 2.29.2