From c50c4f565797ac47544e1f0a2669d9cf1cb9d1c7 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Mon, 20 Apr 2020 23:01:50 +0800 Subject: [PATCH 01/49] drm: bridge: mhdp: Add cdns mhdp driver bridge driver Base on rockchip cdn-dp-reg.c code, create cdns mhdp DP API functions driver. Move the driver to a separate directory. Added HDMI/Audio/CEC API functions. Signed-off-by: Sandor Yu [ Aisheng: fix conflict due to below commit 611e22b1d9f6 ("drm/rockchip: Remove unneeded semicolon") ] Signed-off-by: Dong Aisheng --- drivers/gpu/drm/bridge/cadence/Kconfig | 26 + drivers/gpu/drm/bridge/cadence/Makefile | 9 + drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 574 +++++++++++ .../gpu/drm/bridge/cadence/cdns-hdmi-core.c | 690 +++++++++++++ .../gpu/drm/bridge/cadence/cdns-mhdp-audio.c | 395 +++++++ .../gpu/drm/bridge/cadence/cdns-mhdp-cec.c | 341 +++++++ .../gpu/drm/bridge/cadence/cdns-mhdp-common.c | 795 +++++++++++++++ drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c | 172 ++++ .../gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c | 332 ++++++ drivers/gpu/drm/bridge/cadence/cdns-mhdp.h | 209 ++++ drivers/gpu/drm/rockchip/Makefile | 2 +- drivers/gpu/drm/rockchip/cdn-dp-core.c | 241 ++--- drivers/gpu/drm/rockchip/cdn-dp-core.h | 44 +- drivers/gpu/drm/rockchip/cdn-dp-reg.c | 960 ------------------ .../drm/bridge/cdns-mhdp.h | 389 ++++++- 15 files changed, 4034 insertions(+), 1145 deletions(-) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp.h delete mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c rename drivers/gpu/drm/rockchip/cdn-dp-reg.h => include/drm/bridge/cdns-mhdp.h (53%) diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig index ef8c230e0f62..bb1865b15aca 100644 --- a/drivers/gpu/drm/bridge/cadence/Kconfig +++ b/drivers/gpu/drm/bridge/cadence/Kconfig @@ -22,3 +22,31 @@ config DRM_CDNS_MHDP8546_J721E initializes the J721E Display Port and sets up the clock and data muxes. endif + +config DRM_CDNS_MHDP + tristate "Cadence MHDP COMMON API driver" + select DRM_KMS_HELPER + select DRM_PANEL_BRIDGE + depends on OF + help + Support Cadence MHDP API library. + +config DRM_CDNS_HDMI + tristate "Cadence HDMI DRM driver" + depends on DRM_CDNS_MHDP + select DRM_DISPLAY_HDCP_HELPER + select DRM_DISPLAY_HDMI_HELPER + +config DRM_CDNS_DP + tristate "Cadence DP DRM driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_AUDIO + tristate "Cadence MHDP Audio driver" + depends on DRM_CDNS_MHDP + +config DRM_CDNS_HDMI_CEC + tristate "Cadence MHDP HDMI CEC driver" + depends on DRM_CDNS_HDMI + select CEC_CORE + select CEC_NOTIFIER diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile index 8f647991b374..618290870ba5 100644 --- a/drivers/gpu/drm/bridge/cadence/Makefile +++ b/drivers/gpu/drm/bridge/cadence/Makefile @@ -1,4 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o + +cdns_mhdp_drmcore-y := cdns-mhdp-common.o cdns-mhdp-dp.o cdns-mhdp-hdmi.o + +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI) += cdns-hdmi-core.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_DP) += cdns-dp-core.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_AUDIO) += cdns-mhdp-audio.o +cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI_CEC) += cdns-mhdp-cec.o + +obj-$(CONFIG_DRM_CDNS_MHDP) += cdns_mhdp_drmcore.o diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c new file mode 100644 index 000000000000..acb5c860da73 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c @@ -0,0 +1,574 @@ +/* + * Cadence Display Port Interface (DP) driver + * + * Copyright (C) 2019 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This function only implements native DPDC reads and writes + */ +static ssize_t dp_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(aux->dev); + bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); + int ret; + + /* Ignore address only message */ + if ((msg->size == 0) || (msg->buffer == NULL)) { + msg->reply = native ? + DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; + return msg->size; + } + + if (!native) { + dev_err(mhdp->dev, "%s: only native messages supported\n", __func__); + return -EINVAL; + } + + /* msg sanity check */ + if (msg->size > DP_AUX_MAX_PAYLOAD_BYTES) { + dev_err(mhdp->dev, "%s: invalid msg: size(%zu), request(%x)\n", + __func__, msg->size, (unsigned int)msg->request); + return -EINVAL; + } + + if (msg->request == DP_AUX_NATIVE_WRITE) { + const u8 *buf = msg->buffer; + int i; + for (i = 0; i < msg->size; ++i) { + ret = cdns_mhdp_dpcd_write(mhdp, + msg->address + i, buf[i]); + if (!ret) + continue; + + DRM_DEV_ERROR(mhdp->dev, "Failed to write DPCD\n"); + + return ret; + } + } + + if (msg->request == DP_AUX_NATIVE_READ) { + ret = cdns_mhdp_dpcd_read(mhdp, msg->address, msg->buffer, msg->size); + if (ret < 0) + return -EIO; + msg->reply = DP_AUX_NATIVE_REPLY_ACK; + return msg->size; + } + return 0; +} + +static int dp_aux_init(struct cdns_mhdp_device *mhdp, + struct device *dev) +{ + int ret; + + mhdp->dp.aux.name = "imx_dp_aux"; + mhdp->dp.aux.dev = dev; + mhdp->dp.aux.transfer = dp_aux_transfer; + + ret = drm_dp_aux_register(&mhdp->dp.aux); + + return ret; +} + +static int dp_aux_destroy(struct cdns_mhdp_device *mhdp) +{ + drm_dp_aux_unregister(&mhdp->dp.aux); + return 0; +} + +static void dp_pixel_clk_reset(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + /* reset pixel clk */ + val = cdns_mhdp_reg_read(mhdp, SOURCE_HDTX_CAR); + cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val & 0xFD); + cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val); +} + +static void cdns_dp_mode_set(struct cdns_mhdp_device *mhdp) +{ + u32 lane_mapping = mhdp->lane_mapping; + int ret; + + cdns_mhdp_plat_call(mhdp, pclk_rate); + + /* delay for DP FW stable after pixel clock relock */ + msleep(50); + + dp_pixel_clk_reset(mhdp); + + /* Get DP Caps */ + ret = drm_dp_dpcd_read(&mhdp->dp.aux, DP_DPCD_REV, mhdp->dp.dpcd, + DP_RECEIVER_CAP_SIZE); + if (ret < 0) { + DRM_ERROR("Failed to get caps %d\n", ret); + return; + } + + mhdp->dp.rate = drm_dp_max_link_rate(mhdp->dp.dpcd); + mhdp->dp.num_lanes = drm_dp_max_lane_count(mhdp->dp.dpcd); + + /* check the max link rate */ + if (mhdp->dp.rate > CDNS_DP_MAX_LINK_RATE) + mhdp->dp.rate = CDNS_DP_MAX_LINK_RATE; + + /* Initialize link rate/num_lanes as panel max link rate/max_num_lanes */ + cdns_mhdp_plat_call(mhdp, phy_set); + + /* Video off */ + ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); + return; + } + + /* Line swaping */ + cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | lane_mapping); + + /* Set DP host capability */ + ret = cdns_mhdp_set_host_cap(mhdp, false); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to set host cap %d\n", ret); + return; + } + + ret = cdns_mhdp_config_video(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to config video %d\n", ret); + return; + } + + return; +} + +/* ----------------------------------------------------------------------------- + * dp TX Setup + */ +static enum drm_connector_status +cdns_dp_connector_detect(struct drm_connector *connector, bool force) +{ + struct cdns_mhdp_device *mhdp = container_of(connector, + struct cdns_mhdp_device, connector.base); + u8 hpd = 0xf; + + hpd = cdns_mhdp_read_hpd(mhdp); + if (hpd == 1) + /* Cable Connected */ + return connector_status_connected; + else if (hpd == 0) + /* Cable Disconnedted */ + return connector_status_disconnected; + else { + /* Cable status unknown */ + DRM_INFO("Unknow cable status, hdp=%u\n", hpd); + return connector_status_unknown; + } +} + +static int cdns_dp_connector_get_modes(struct drm_connector *connector) +{ + struct cdns_mhdp_device *mhdp = container_of(connector, + struct cdns_mhdp_device, connector.base); + int num_modes = 0; + struct edid *edid; + + edid = drm_do_get_edid(&mhdp->connector.base, + cdns_mhdp_get_edid_block, mhdp); + if (edid) { + dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", + edid->header[0], edid->header[1], + edid->header[2], edid->header[3], + edid->header[4], edid->header[5], + edid->header[6], edid->header[7]); + drm_connector_update_edid_property(connector, edid); + num_modes = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + if (num_modes == 0) + DRM_ERROR("Invalid edid\n"); + return num_modes; +} + +static const struct drm_connector_funcs cdns_dp_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = cdns_dp_connector_detect, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs cdns_dp_connector_helper_funcs = { + .get_modes = cdns_dp_connector_get_modes, +}; + +static int cdns_dp_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_encoder *encoder = bridge->encoder; + struct drm_connector *connector = &mhdp->connector.base; + + connector->interlace_allowed = 1; + + if (mhdp->is_hpd) + connector->polled = DRM_CONNECTOR_POLL_HPD; + else + connector->polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + + drm_connector_helper_add(connector, &cdns_dp_connector_helper_funcs); + + drm_connector_init(bridge->dev, connector, &cdns_dp_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort); + + drm_connector_attach_encoder(connector, encoder); + + return 0; +} + +static enum drm_mode_status +cdns_dp_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + enum drm_mode_status mode_status = MODE_OK; + + /* We don't support double-clocked modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK || + mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_BAD; + + /* MAX support pixel clock rate 594MHz */ + if (mode->clock > 594000) + return MODE_CLOCK_HIGH; + + /* 4096x2160 is not supported now */ + if (mode->hdisplay > 3840) + return MODE_BAD_HVALUE; + + if (mode->vdisplay > 2160) + return MODE_BAD_VVALUE; + + return mode_status; +} + +static void cdns_dp_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *orig_mode, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_display_info *display_info = &mhdp->connector.base.display_info; + struct video_info *video = &mhdp->video_info; + + switch (display_info->bpc) { + case 10: + video->color_depth = 10; + break; + case 6: + video->color_depth = 6; + break; + default: + video->color_depth = 8; + break; + } + + video->color_fmt = PXL_RGB; + video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode->clock); + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); + + mutex_lock(&mhdp->lock); + cdns_dp_mode_set(mhdp); + mutex_unlock(&mhdp->lock); + + /* reset force mode set flag */ + mhdp->force_mode_set = false; +} + +static void cdn_dp_bridge_enable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + int ret; + + /* Link trainning */ + ret = cdns_mhdp_train_link(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed link train %d\n", ret); + return; + } + + ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_VALID); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); + return; + } +} + +static void cdn_dp_bridge_disable(struct drm_bridge *bridge) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + + cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); +} + +static const struct drm_bridge_funcs cdns_dp_bridge_funcs = { + .attach = cdns_dp_bridge_attach, + .enable = cdn_dp_bridge_enable, + .disable = cdn_dp_bridge_disable, + .mode_set = cdns_dp_bridge_mode_set, + .mode_valid = cdns_dp_bridge_mode_valid, +}; + +static void hotplug_work_func(struct work_struct *work) +{ + struct cdns_mhdp_device *mhdp = container_of(work, + struct cdns_mhdp_device, hotplug_work.work); + struct drm_connector *connector = &mhdp->connector.base; + + drm_helper_hpd_irq_event(connector->dev); + + if (connector->status == connector_status_connected) { + /* Cable connedted */ + DRM_INFO("HDMI/DP Cable Plug In\n"); + enable_irq(mhdp->irq[IRQ_OUT]); + } else if (connector->status == connector_status_disconnected) { + /* Cable Disconnedted */ + DRM_INFO("HDMI/DP Cable Plug Out\n"); + /* force mode set for cable replugin to recovery DP video modes */ + mhdp->force_mode_set = true; + enable_irq(mhdp->irq[IRQ_IN]); + } +} + +static irqreturn_t cdns_dp_irq_thread(int irq, void *data) +{ + struct cdns_mhdp_device *mhdp = data; + + disable_irq_nosync(irq); + + mod_delayed_work(system_wq, &mhdp->hotplug_work, + msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); + + return IRQ_HANDLED; +} + +static void cdns_dp_parse_dt(struct cdns_mhdp_device *mhdp) +{ + struct device_node *of_node = mhdp->dev->of_node; + int ret; + + ret = of_property_read_u32(of_node, "lane-mapping", + &mhdp->lane_mapping); + if (ret) { + mhdp->lane_mapping = 0xc6; + dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); + } + dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); +} + +static int __cdns_dp_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + struct device *dev = &pdev->dev; + struct resource *iores = NULL; + int ret; + + mutex_init(&mhdp->lock); + mutex_init(&mhdp->iolock); + + INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (iores) { + mhdp->regs_base = devm_ioremap(dev, iores->start, + resource_size(iores)); + if (IS_ERR(mhdp->regs_base)) + return -ENOMEM; + } + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (iores) { + mhdp->regs_sec = devm_ioremap(dev, iores->start, + resource_size(iores)); + if (IS_ERR(mhdp->regs_sec)) + return -ENOMEM; + } + + mhdp->is_hpd = true; + mhdp->is_ls1028a = false; + + mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); + if (mhdp->irq[IRQ_IN] < 0) { + mhdp->is_hpd = false; + dev_info(dev, "No plug_in irq number\n"); + } + + mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); + if (mhdp->irq[IRQ_OUT] < 0) { + mhdp->is_hpd = false; + dev_info(dev, "No plug_out irq number\n"); + } + + cdns_dp_parse_dt(mhdp); + + if (of_device_is_compatible(dev->of_node, "cdn,ls1028a-dp")) + mhdp->is_ls1028a = true; + + cdns_mhdp_plat_call(mhdp, power_on); + + cdns_mhdp_plat_call(mhdp, firmware_init); + + /* DP FW alive check */ + ret = cdns_mhdp_check_alive(mhdp); + if (ret == false) { + DRM_ERROR("NO dp FW running\n"); + return -ENXIO; + } + + /* DP PHY init before AUX init */ + cdns_mhdp_plat_call(mhdp, phy_set); + + /* Enable Hotplug Detect IRQ thread */ + if (mhdp->is_hpd) { + irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], + NULL, cdns_dp_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + + if (ret) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_IN]); + return -EINVAL; + } + + irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], + NULL, cdns_dp_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + + if (ret) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_OUT]); + return -EINVAL; + } + + if (cdns_mhdp_read_hpd(mhdp)) + enable_irq(mhdp->irq[IRQ_OUT]); + else + enable_irq(mhdp->irq[IRQ_IN]); + } + + mhdp->bridge.base.driver_private = mhdp; + mhdp->bridge.base.funcs = &cdns_dp_bridge_funcs; +#ifdef CONFIG_OF + mhdp->bridge.base.of_node = dev->of_node; +#endif + + dev_set_drvdata(dev, mhdp); + + /* register audio driver */ + cdns_mhdp_register_audio_driver(dev); + + dp_aux_init(mhdp, dev); + + return 0; +} + +static void __cdns_dp_remove(struct cdns_mhdp_device *mhdp) +{ + dp_aux_destroy(mhdp); + cdns_mhdp_unregister_audio_driver(mhdp->dev); +} + +/* ----------------------------------------------------------------------------- + * Probe/remove API, used from platforms based on the DRM bridge API. + */ +int cdns_dp_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_dp_probe(pdev, mhdp); + if (ret) + return ret; + + drm_bridge_add(&mhdp->bridge.base); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_dp_probe); + +void cdns_dp_remove(struct platform_device *pdev) +{ + struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); + + drm_bridge_remove(&mhdp->bridge.base); + + __cdns_dp_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_dp_remove); + +/* ----------------------------------------------------------------------------- + * Bind/unbind API, used from platforms based on the component framework. + */ +int cdns_dp_bind(struct platform_device *pdev, struct drm_encoder *encoder, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_dp_probe(pdev, mhdp); + if (ret < 0) + return ret; + + ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL, 0); + if (ret) { + cdns_dp_remove(pdev); + DRM_ERROR("Failed to initialize bridge with drm\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_dp_bind); + +void cdns_dp_unbind(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + __cdns_dp_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_dp_unbind); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("Cadence Display Port transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cdn-dp"); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file mode 100644 index 000000000000..da40f62617ef --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c @@ -0,0 +1,690 @@ +/* + * Cadence High-Definition Multimedia Interface (HDMI) driver + * + * Copyright (C) 2019 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void hdmi_sink_config(struct cdns_mhdp_device *mhdp) +{ + struct drm_scdc *scdc = &mhdp->connector.base.display_info.hdmi.scdc; + u8 buff = 0; + + /* Default work in HDMI1.4 */ + mhdp->hdmi.hdmi_type = MODE_HDMI_1_4; + + /* check sink support SCDC or not */ + if (scdc->supported != true) { + DRM_INFO("Sink Not Support SCDC\n"); + return; + } + + if (mhdp->hdmi.char_rate > 340000) { + /* + * TMDS Character Rate above 340MHz should working in HDMI2.0 + * Enable scrambling and TMDS_Bit_Clock_Ratio + */ + buff = SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE; + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; + } else if (scdc->scrambling.low_rates) { + /* + * Enable scrambling and HDMI2.0 when scrambling capability of sink + * be indicated in the HF-VSDB LTE_340Mcsc_scramble bit + */ + buff = SCDC_SCRAMBLING_ENABLE; + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; + } + + /* TMDS config */ + cdns_hdmi_scdc_write(mhdp, 0x20, buff); +} + +static void hdmi_lanes_config(struct cdns_mhdp_device *mhdp) +{ + /* Line swaping */ + cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | mhdp->lane_mapping); +} + +static int hdmi_avi_info_set(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode) +{ + struct hdmi_avi_infoframe frame; + int format = mhdp->video_info.color_fmt; + struct drm_connector_state *conn_state = mhdp->connector.base.state; + struct drm_display_mode *adj_mode; + enum hdmi_quantization_range qr; + u8 buf[32]; + int ret; + + /* Initialise info frame from DRM mode */ + drm_hdmi_avi_infoframe_from_display_mode(&frame, &mhdp->connector.base, + mode); + + switch (format) { + case YCBCR_4_4_4: + frame.colorspace = HDMI_COLORSPACE_YUV444; + break; + case YCBCR_4_2_2: + frame.colorspace = HDMI_COLORSPACE_YUV422; + break; + case YCBCR_4_2_0: + frame.colorspace = HDMI_COLORSPACE_YUV420; + break; + default: + frame.colorspace = HDMI_COLORSPACE_RGB; + break; + } + + drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state); + + adj_mode = &mhdp->bridge.base.encoder->crtc->state->adjusted_mode; + + qr = drm_default_rgb_quant_range(adj_mode); + + drm_hdmi_avi_infoframe_quant_range(&frame, &mhdp->connector.base, + adj_mode, qr); + + ret = hdmi_avi_infoframe_check(&frame); + if (WARN_ON(ret)) + return false; + + ret = hdmi_avi_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); + return -1; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 0, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AVI); + return 0; +} + +static void hdmi_vendor_info_set(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode) +{ + struct hdmi_vendor_infoframe frame; + u8 buf[32]; + int ret; + + /* Initialise vendor frame from DRM mode */ + ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, &mhdp->connector.base, mode); + if (ret < 0) { + DRM_INFO("No vendor infoframe\n"); + return; + } + + ret = hdmi_vendor_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_WARN("Unable to pack vendor infoframe: %d\n", ret); + return; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_VENDOR); +} + +static void hdmi_drm_info_set(struct cdns_mhdp_device *mhdp) +{ + struct drm_connector_state *conn_state; + struct hdmi_drm_infoframe frame; + u8 buf[32]; + int ret; + + conn_state = mhdp->connector.base.state; + + if (!conn_state->hdr_output_metadata) + return; + + ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); + if (ret < 0) { + DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); + return; + } + + ret = hdmi_drm_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_DEBUG_KMS("couldn't pack HDR infoframe\n"); + return; + } + + buf[0] = 0; + cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), + buf, HDMI_INFOFRAME_TYPE_DRM); +} + +void cdns_hdmi_mode_set(struct cdns_mhdp_device *mhdp) +{ + struct drm_display_mode *mode = &mhdp->mode; + int ret; + + /* video mode valid check */ + if (mode->clock == 0 || mode->hdisplay == 0 || mode->vdisplay == 0) + return; + + hdmi_lanes_config(mhdp); + + cdns_mhdp_plat_call(mhdp, pclk_rate); + + /* delay for HDMI FW stable after pixel clock relock */ + msleep(20); + + cdns_mhdp_plat_call(mhdp, phy_set); + + hdmi_sink_config(mhdp); + + ret = cdns_hdmi_ctrl_init(mhdp, mhdp->hdmi.hdmi_type, mhdp->hdmi.char_rate); + if (ret < 0) { + DRM_ERROR("%s, ret = %d\n", __func__, ret); + return; + } + + /* Config GCP */ + if (mhdp->video_info.color_depth == 8) + cdns_hdmi_disable_gcp(mhdp); + else + cdns_hdmi_enable_gcp(mhdp); + + ret = hdmi_avi_info_set(mhdp, mode); + if (ret < 0) { + DRM_ERROR("%s ret = %d\n", __func__, ret); + return; + } + + /* vendor info frame is enable only when HDMI1.4 4K mode */ + hdmi_vendor_info_set(mhdp, mode); + + hdmi_drm_info_set(mhdp); + + ret = cdns_hdmi_mode_config(mhdp, mode, &mhdp->video_info); + if (ret < 0) { + DRM_ERROR("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret); + return; + } +} + +static enum drm_connector_status +cdns_hdmi_connector_detect(struct drm_connector *connector, bool force) +{ + struct cdns_mhdp_device *mhdp = + container_of(connector, struct cdns_mhdp_device, connector.base); + + u8 hpd = 0xf; + + hpd = cdns_mhdp_read_hpd(mhdp); + + if (hpd == 1) + /* Cable Connected */ + return connector_status_connected; + else if (hpd == 0) + /* Cable Disconnedted */ + return connector_status_disconnected; + else { + /* Cable status unknown */ + DRM_INFO("Unknow cable status, hdp=%u\n", hpd); + return connector_status_unknown; + } +} + +static int cdns_hdmi_connector_get_modes(struct drm_connector *connector) +{ + struct cdns_mhdp_device *mhdp = + container_of(connector, struct cdns_mhdp_device, connector.base); + int num_modes = 0; + struct edid *edid; + + edid = drm_do_get_edid(&mhdp->connector.base, + cdns_hdmi_get_edid_block, mhdp); + if (edid) { + dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", + edid->header[0], edid->header[1], + edid->header[2], edid->header[3], + edid->header[4], edid->header[5], + edid->header[6], edid->header[7]); + drm_connector_update_edid_property(connector, edid); + num_modes = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + if (num_modes == 0) + DRM_ERROR("Invalid edid\n"); + return num_modes; +} + +static bool blob_equal(const struct drm_property_blob *a, + const struct drm_property_blob *b) +{ + if (a && b) + return a->length == b->length && + !memcmp(a->data, b->data, a->length); + + return !a == !b; +} + +static int cdns_hdmi_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_connector_state *new_con_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_con_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc *crtc = new_con_state->crtc; + struct drm_crtc_state *new_crtc_state; + + if (!blob_equal(new_con_state->hdr_output_metadata, + old_con_state->hdr_output_metadata) || + new_con_state->colorspace != old_con_state->colorspace) { + new_crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + new_crtc_state->mode_changed = + !new_con_state->hdr_output_metadata || + !old_con_state->hdr_output_metadata || + new_con_state->colorspace != old_con_state->colorspace; + } + + return 0; +} + +static const struct drm_connector_funcs cdns_hdmi_connector_funcs = { + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = cdns_hdmi_connector_detect, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs cdns_hdmi_connector_helper_funcs = { + .get_modes = cdns_hdmi_connector_get_modes, + .atomic_check = cdns_hdmi_connector_atomic_check, +}; + +static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_mode_config *config = &bridge->dev->mode_config; + struct drm_encoder *encoder = bridge->encoder; + struct drm_connector *connector = &mhdp->connector.base; + + connector->interlace_allowed = 1; + connector->polled = DRM_CONNECTOR_POLL_HPD; + + drm_connector_helper_add(connector, &cdns_hdmi_connector_helper_funcs); + + drm_connector_init(bridge->dev, connector, &cdns_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + + if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + drm_object_attach_property(&connector->base, + config->hdr_output_metadata_property, + 0); + + if (!drm_mode_create_hdmi_colorspace_property(connector)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, + 0); + } + + drm_connector_attach_encoder(connector, encoder); + + return 0; +} + +static enum drm_mode_status +cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + enum drm_mode_status mode_status = MODE_OK; + int ret; + + /* We don't support double-clocked and Interlaced modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK || + mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_BAD; + + /* MAX support pixel clock rate 594MHz */ + if (mode->clock > 594000) + return MODE_CLOCK_HIGH; + + /* 4096x2160 is not supported */ + if (mode->hdisplay > 3840 || mode->vdisplay > 2160) + return MODE_BAD_HVALUE; + + mhdp->valid_mode = mode; + ret = cdns_mhdp_plat_call(mhdp, phy_video_valid); + if (ret == false) + return MODE_CLOCK_RANGE; + + return mode_status; +} + +static void cdns_hdmi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *orig_mode, + const struct drm_display_mode *mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct video_info *video = &mhdp->video_info; + + video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode->clock); + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); + + mutex_lock(&mhdp->lock); + cdns_hdmi_mode_set(mhdp); + mutex_unlock(&mhdp->lock); + /* reset force mode set flag */ + mhdp->force_mode_set = false; +} + +bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct cdns_mhdp_device *mhdp = bridge->driver_private; + struct drm_display_info *di = &mhdp->connector.base.display_info; + struct video_info *video = &mhdp->video_info; + int vic = drm_match_cea_mode(mode); + + video->color_depth = 8; + video->color_fmt = PXL_RGB; + + /* for all other platforms, other than imx8mq */ + if (strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { + if (di->bpc == 10 || di->bpc == 6) + video->color_depth = di->bpc; + + return true; + } + + /* imx8mq */ + if (vic == 97 || vic == 96) { + if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) + video->color_depth = 12; + else if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) + video->color_depth = 10; + + if (drm_mode_is_420_only(di, mode) || + (drm_mode_is_420_also(di, mode) && + video->color_depth > 8)) { + video->color_fmt = YCBCR_4_2_0; + + adjusted_mode->private_flags = 1; + return true; + } + + video->color_depth = 8; + return true; + } + + /* Any defined maximum tmds clock limit we must not exceed*/ + if ((di->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36) && + (mode->clock * 3 / 2 <= di->max_tmds_clock)) + video->color_depth = 12; + else if ((di->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && + (mode->clock * 5 / 4 <= di->max_tmds_clock)) + video->color_depth = 10; + + /* 10-bit color depth for the following modes is not supported */ + if ((vic == 95 || vic == 94 || vic == 93) && video->color_depth == 10) + video->color_depth = 8; + + return true; +} + +static const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = { + .attach = cdns_hdmi_bridge_attach, + .mode_set = cdns_hdmi_bridge_mode_set, + .mode_valid = cdns_hdmi_bridge_mode_valid, + .mode_fixup = cdns_hdmi_bridge_mode_fixup, +}; + +static void hotplug_work_func(struct work_struct *work) +{ + struct cdns_mhdp_device *mhdp = container_of(work, + struct cdns_mhdp_device, hotplug_work.work); + struct drm_connector *connector = &mhdp->connector.base; + + drm_helper_hpd_irq_event(connector->dev); + + if (connector->status == connector_status_connected) { + DRM_INFO("HDMI Cable Plug In\n"); + mhdp->force_mode_set = true; + enable_irq(mhdp->irq[IRQ_OUT]); + } else if (connector->status == connector_status_disconnected) { + /* Cable Disconnedted */ + DRM_INFO("HDMI Cable Plug Out\n"); + /* force mode set for cable replugin to recovery HDMI2.0 video modes */ + mhdp->force_mode_set = true; + enable_irq(mhdp->irq[IRQ_IN]); + } +} + +static irqreturn_t cdns_hdmi_irq_thread(int irq, void *data) +{ + struct cdns_mhdp_device *mhdp = data; + + disable_irq_nosync(irq); + + mod_delayed_work(system_wq, &mhdp->hotplug_work, + msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); + + return IRQ_HANDLED; +} + +static void cdns_hdmi_parse_dt(struct cdns_mhdp_device *mhdp) +{ + struct device_node *of_node = mhdp->dev->of_node; + int ret; + + ret = of_property_read_u32(of_node, "lane-mapping", &mhdp->lane_mapping); + if (ret) { + mhdp->lane_mapping = 0xc6; + dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); + } + dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); +} + +static int __cdns_hdmi_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + struct device *dev = &pdev->dev; + struct platform_device_info pdevinfo; + struct resource *iores = NULL; + int ret; + + mutex_init(&mhdp->lock); + mutex_init(&mhdp->iolock); + + INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mhdp->regs_base = devm_ioremap(dev, iores->start, resource_size(iores)); + if (IS_ERR(mhdp->regs_base)) { + dev_err(dev, "No regs_base memory\n"); + return -ENOMEM; + } + + /* sec register base */ + iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); + mhdp->regs_sec = devm_ioremap(dev, iores->start, resource_size(iores)); + if (IS_ERR(mhdp->regs_sec)) { + dev_err(dev, "No regs_sec memory\n"); + return -ENOMEM; + } + + mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); + if (mhdp->irq[IRQ_IN] < 0) { + dev_info(dev, "No plug_in irq number\n"); + return -EPROBE_DEFER; + } + + mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); + if (mhdp->irq[IRQ_OUT] < 0) { + dev_info(dev, "No plug_out irq number\n"); + return -EPROBE_DEFER; + } + + cdns_mhdp_plat_call(mhdp, power_on); + + /* Initialize FW */ + cdns_mhdp_plat_call(mhdp, firmware_init); + + /* HDMI FW alive check */ + ret = cdns_mhdp_check_alive(mhdp); + if (ret == false) { + dev_err(dev, "NO HDMI FW running\n"); + return -ENXIO; + } + + /* Enable Hotplug Detect thread */ + irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], + NULL, cdns_hdmi_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + if (ret < 0) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_IN]); + return -EINVAL; + } + + irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], + NULL, cdns_hdmi_irq_thread, + IRQF_ONESHOT, dev_name(dev), + mhdp); + if (ret < 0) { + dev_err(dev, "can't claim irq %d\n", + mhdp->irq[IRQ_OUT]); + return -EINVAL; + } + + cdns_hdmi_parse_dt(mhdp); + + if (cdns_mhdp_read_hpd(mhdp)) + enable_irq(mhdp->irq[IRQ_OUT]); + else + enable_irq(mhdp->irq[IRQ_IN]); + + mhdp->bridge.base.driver_private = mhdp; + mhdp->bridge.base.funcs = &cdns_hdmi_bridge_funcs; +#ifdef CONFIG_OF + mhdp->bridge.base.of_node = dev->of_node; +#endif + + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.parent = dev; + pdevinfo.id = PLATFORM_DEVID_AUTO; + + dev_set_drvdata(dev, mhdp); + + /* register audio driver */ + cdns_mhdp_register_audio_driver(dev); + + /* register cec driver */ +#ifdef CONFIG_DRM_CDNS_HDMI_CEC + cdns_mhdp_register_cec_driver(dev); +#endif + + return 0; +} + +static void __cdns_hdmi_remove(struct cdns_mhdp_device *mhdp) +{ + /* unregister cec driver */ +#ifdef CONFIG_DRM_CDNS_HDMI_CEC + cdns_mhdp_unregister_cec_driver(mhdp->dev); +#endif + cdns_mhdp_unregister_audio_driver(mhdp->dev); +} + +/* ----------------------------------------------------------------------------- + * Probe/remove API, used from platforms based on the DRM bridge API. + */ +int cdns_hdmi_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_hdmi_probe(pdev, mhdp); + if (ret < 0) + return ret; + + drm_bridge_add(&mhdp->bridge.base); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdmi_probe); + +void cdns_hdmi_remove(struct platform_device *pdev) +{ + struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); + + drm_bridge_remove(&mhdp->bridge.base); + + __cdns_hdmi_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_hdmi_remove); + +/* ----------------------------------------------------------------------------- + * Bind/unbind API, used from platforms based on the component framework. + */ +int cdns_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, + struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = __cdns_hdmi_probe(pdev, mhdp); + if (ret) + return ret; + + ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL, 0); + if (ret) { + cdns_hdmi_remove(pdev); + DRM_ERROR("Failed to initialize bridge with drm\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_hdmi_bind); + +void cdns_hdmi_unbind(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + __cdns_hdmi_remove(mhdp); +} +EXPORT_SYMBOL_GPL(cdns_hdmi_unbind); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("Cadence HDMI transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cdn-hdmi"); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c new file mode 100644 index 000000000000..86174fb633bc --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Chris Zhong + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include + +#define CDNS_DP_SPDIF_CLK 200000000 + +static u32 TMDS_rate_table[7] = { + 25200, 27000, 54000, 74250, 148500, 297000, 594000, +}; + +static u32 N_table_32k[7] = { +/* 25200/27000/54000/74250/148500/297000/594000 */ + 4096, 4096, 4096, 4096, 4096, 3072, 3072, +}; + +static u32 N_table_44k[7] = { + 6272, 6272, 6272, 6272, 6272, 4704, 9408, +}; + +static u32 N_table_48k[7] = { + 6144, 6144, 6144, 6144, 6144, 5120, 6144, +}; + +static int select_N_index(u32 pclk) +{ + int num = sizeof(TMDS_rate_table)/sizeof(int); + int i = 0; + + for (i = 0; i < num ; i++) + if (pclk == TMDS_rate_table[i]) + break; + + if (i == num) { + DRM_WARN("pclkc %d is not supported!\n", pclk); + return num-1; + } + + return i; +} + +static void hdmi_audio_avi_set(struct cdns_mhdp_device *mhdp, + u32 channels) +{ + struct hdmi_audio_infoframe frame; + u8 buf[32]; + int ret; + + hdmi_audio_infoframe_init(&frame); + + frame.channels = channels; + frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; + + if (channels == 2) + frame.channel_allocation = 0; + else if (channels == 4) + frame.channel_allocation = 0x3; + else if (channels == 8) + frame.channel_allocation = 0x13; + + ret = hdmi_audio_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); + if (ret < 0) { + DRM_ERROR("failed to pack audio infoframe: %d\n", ret); + return; + } + + buf[0] = 0; + + cdns_mhdp_infoframe_set(mhdp, 1, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AUDIO); +} + +int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int ret; + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, 0); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "audio stop failed: %d\n", ret); + return ret; + } + } + + cdns_mhdp_bus_write(0, mhdp, SPDIF_CTRL_ADDR); + + /* clearn the audio config and reset */ + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNFG); + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, AUDIO_SRC_CNTL); + cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); + + /* reset smpl2pckt component */ + cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); + + /* reset FIFO */ + cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, FIFO_CNTL); + cdns_mhdp_bus_write(0, mhdp, FIFO_CNTL); + + if (audio->format == AFMT_SPDIF_INT) + clk_disable_unprepare(mhdp->spdif_clk); + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_audio_stop); + +int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable) +{ + struct audio_info *audio = &mhdp->audio_info; + int ret = true; + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 4, 1, enable); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "audio mute failed: %d\n", ret); + } + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_audio_mute); + +static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int sub_pckt_num = 1, i2s_port_en_val = 0xf, i; + int idx = select_N_index(mhdp->mode.clock); + u32 val, ncts; + + if (audio->channels == 2) { + if (mhdp->dp.num_lanes == 1) + sub_pckt_num = 2; + else + sub_pckt_num = 4; + + i2s_port_en_val = 1; + } else if (audio->channels == 4) { + i2s_port_en_val = 3; + } + + cdns_mhdp_bus_write(0x0, mhdp, SPDIF_CTRL_ADDR); + + cdns_mhdp_bus_write(SYNC_WR_TO_CH_ZERO, mhdp, FIFO_CNTL); + + val = MAX_NUM_CH(audio->channels); + val |= NUM_OF_I2S_PORTS(audio->channels); + val |= AUDIO_TYPE_LPCM; + val |= CFG_SUB_PCKT_NUM(sub_pckt_num); + cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); + + if (audio->sample_width == 16) + val = 0; + else if (audio->sample_width == 24) + val = 1 << 9; + else + val = 2 << 9; + + val |= AUDIO_CH_NUM(audio->channels); + val |= I2S_DEC_PORT_EN(i2s_port_en_val); + val |= TRANS_SMPL_WIDTH_32; + cdns_mhdp_bus_write(val, mhdp, AUDIO_SRC_CNFG); + + for (i = 0; i < (audio->channels + 1) / 2; i++) { + if (audio->sample_width == 16) + val = (0x02 << 8) | (0x02 << 20); + else if (audio->sample_width == 24) + val = (0x0b << 8) | (0x0b << 20); + + val |= ((2 * i) << 4) | ((2 * i + 1) << 16); + cdns_mhdp_bus_write(val, mhdp, STTS_BIT_CH(i)); + } + + switch (audio->sample_rate) { + case 32000: + val = SAMPLING_FREQ(3) | + ORIGINAL_SAMP_FREQ(0xc); + ncts = N_table_32k[idx]; + break; + case 44100: + val = SAMPLING_FREQ(0) | + ORIGINAL_SAMP_FREQ(0xf); + ncts = N_table_44k[idx]; + break; + case 48000: + val = SAMPLING_FREQ(2) | + ORIGINAL_SAMP_FREQ(0xd); + ncts = N_table_48k[idx]; + break; + case 88200: + val = SAMPLING_FREQ(8) | + ORIGINAL_SAMP_FREQ(0x7); + ncts = N_table_44k[idx] * 2; + break; + case 96000: + val = SAMPLING_FREQ(0xa) | + ORIGINAL_SAMP_FREQ(5); + ncts = N_table_48k[idx] * 2; + break; + case 176400: + val = SAMPLING_FREQ(0xc) | + ORIGINAL_SAMP_FREQ(3); + ncts = N_table_44k[idx] * 4; + break; + case 192000: + default: + val = SAMPLING_FREQ(0xe) | + ORIGINAL_SAMP_FREQ(1); + ncts = N_table_48k[idx] * 4; + break; + } + val |= 4; + cdns_mhdp_bus_write(val, mhdp, COM_CH_STTS_BITS); + + if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) + cdns_mhdp_reg_write(mhdp, CM_I2S_CTRL, ncts | 0x4000000); + + cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); + cdns_mhdp_bus_write(I2S_DEC_START, mhdp, AUDIO_SRC_CNTL); +} + +static void cdns_mhdp_audio_config_spdif(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + cdns_mhdp_bus_write(SYNC_WR_TO_CH_ZERO, mhdp, FIFO_CNTL); + + val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4); + cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); + cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); + + val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS; + cdns_mhdp_bus_write(val, mhdp, SPDIF_CTRL_ADDR); + + clk_prepare_enable(mhdp->spdif_clk); + clk_set_rate(mhdp->spdif_clk, CDNS_DP_SPDIF_CLK); +} + +int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp, + struct audio_info *audio) +{ + int ret; + + /* reset the spdif clk before config */ + if (audio->format == AFMT_SPDIF_INT) { + reset_control_assert(mhdp->spdif_rst); + reset_control_deassert(mhdp->spdif_rst); + } + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + ret = cdns_mhdp_reg_write(mhdp, CM_LANE_CTRL, LANE_REF_CYC); + if (ret) + goto err_audio_config; + + ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 0); + if (ret) + goto err_audio_config; + } else { + /* HDMI Mode */ + ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 8); + if (ret) + goto err_audio_config; + } + + if (audio->format == AFMT_I2S) + cdns_mhdp_audio_config_i2s(mhdp, audio); + else if (audio->format == AFMT_SPDIF_INT) + cdns_mhdp_audio_config_spdif(mhdp); + + if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) + ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN); + + if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) + hdmi_audio_avi_set(mhdp, audio->channels); + +err_audio_config: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "audio config failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_audio_config); + +static int audio_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct audio_info audio = { + .sample_width = params->sample_width, + .sample_rate = params->sample_rate, + .channels = params->channels, + .connector_type = mhdp->connector.base.connector_type, + }; + int ret; + + switch (daifmt->fmt) { + case HDMI_I2S: + audio.format = AFMT_I2S; + break; + case HDMI_SPDIF: + audio.format = AFMT_SPDIF_EXT; + break; + default: + DRM_DEV_ERROR(dev, "Invalid format %d\n", daifmt->fmt); + ret = -EINVAL; + goto out; + } + + ret = cdns_mhdp_audio_config(mhdp, &audio); + if (!ret) + mhdp->audio_info = audio; + +out: + return ret; +} + +static void audio_shutdown(struct device *dev, void *data) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int ret; + + ret = cdns_mhdp_audio_stop(mhdp, &mhdp->audio_info); + if (!ret) + mhdp->audio_info.format = AFMT_UNUSED; +} + +static int audio_digital_mute(struct device *dev, void *data, + bool enable) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + int ret; + + ret = cdns_mhdp_audio_mute(mhdp, enable); + + return ret; +} + +static int audio_get_eld(struct device *dev, void *data, + u8 *buf, size_t len) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + memcpy(buf, mhdp->connector.base.eld, + min(sizeof(mhdp->connector.base.eld), len)); + + return 0; +} + +static const struct hdmi_codec_ops audio_codec_ops = { + .hw_params = audio_hw_params, + .audio_shutdown = audio_shutdown, + .digital_mute = audio_digital_mute, + .get_eld = audio_get_eld, +}; + +int cdns_mhdp_register_audio_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct hdmi_codec_pdata codec_data = { + .i2s = 1, + .spdif = 1, + .ops = &audio_codec_ops, + .max_i2s_channels = 8, + }; + + mhdp->audio_pdev = platform_device_register_data( + dev, HDMI_CODEC_DRV_NAME, 1, + &codec_data, sizeof(codec_data)); + + return PTR_ERR_OR_ZERO(mhdp->audio_pdev); +} + +void cdns_mhdp_unregister_audio_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + + platform_device_unregister(mhdp->audio_pdev); +} diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c new file mode 100644 index 000000000000..5717bb0bcb75 --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c @@ -0,0 +1,341 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +#define CEC_NAME "cdns-mhdp-cec" + +#define REG_ADDR_OFF 4 + +/* regsiter define */ +#define TX_MSG_HEADER 0x33800 +#define TX_MSG_LENGTH 0x33840 +#define TX_MSG_CMD 0x33844 +#define RX_MSG_CMD 0x33850 +#define RX_CLEAR_BUF 0x33854 +#define LOGICAL_ADDRESS_LA0 0x33858 + +#define CLK_DIV_MSB 0x3386c +#define CLK_DIV_LSB 0x33870 +#define RX_MSG_DATA1 0x33900 +#define RX_MSG_LENGTH 0x33940 +#define RX_MSG_STATUS 0x33944 +#define NUM_OF_MSG_RX_BUF 0x33948 +#define TX_MSG_STATUS 0x3394c +#define DB_L_TIMER 0x33980 + +/** + * CEC Transceiver operation. + */ +enum { + CEC_TX_STOP, + CEC_TX_TRANSMIT, + CEC_TX_ABORT, + CEC_TX_ABORT_AND_TRANSMIT +}; + +/** + * CEC Transceiver status. + */ +enum { + CEC_STS_IDLE, + CEC_STS_BUSY, + CEC_STS_SUCCESS, + CEC_STS_ERROR +}; + +/** + * CEC Receiver operation. + */ +enum { + CEC_RX_STOP, + CEC_RX_READ, + CEC_RX_DISABLE, + CEC_RX_ABORT_AND_CLR_FIFO +}; +/** + * Maximum number of Messages in the RX Buffers. + */ +#define CEC_MAX_RX_MSGS 2 + +static u32 mhdp_cec_read(struct cdns_mhdp_cec *cec, u32 offset) +{ + struct cdns_mhdp_device *mhdp = + container_of(cec, struct cdns_mhdp_device, hdmi.cec); + return cdns_mhdp_bus_read(mhdp, offset); +} + +static void mhdp_cec_write(struct cdns_mhdp_cec *cec, u32 offset, u32 val) +{ + struct cdns_mhdp_device *mhdp = + container_of(cec, struct cdns_mhdp_device, hdmi.cec); + cdns_mhdp_bus_write(val, mhdp, offset); +} + +static void mhdp_cec_clear_rx_buffer(struct cdns_mhdp_cec *cec) +{ + mhdp_cec_write(cec, RX_CLEAR_BUF, 1); + mhdp_cec_write(cec, RX_CLEAR_BUF, 0); +} + +static void mhdp_cec_set_divider(struct cdns_mhdp_cec *cec) +{ + struct cdns_mhdp_device *mhdp = + container_of(cec, struct cdns_mhdp_device, hdmi.cec); + u32 clk_div; + + /* Set clock divider */ + clk_div = cdns_mhdp_get_fw_clk(mhdp) * 10; + + mhdp_cec_write(cec, CLK_DIV_MSB, + (clk_div >> 8) & 0xFF); + mhdp_cec_write(cec, CLK_DIV_LSB, clk_div & 0xFF); +} + +static u32 mhdp_cec_read_message(struct cdns_mhdp_cec *cec) +{ + struct cec_msg *msg = &cec->msg; + int len; + int i; + + mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_READ); + + len = mhdp_cec_read(cec, RX_MSG_LENGTH); + msg->len = len + 1; + dev_dbg(cec->dev, "RX MSG len =%d\n", len); + + /* Read RX MSG bytes */ + for (i = 0; i < msg->len; ++i) { + msg->msg[i] = (u8) mhdp_cec_read(cec, RX_MSG_DATA1 + (i * REG_ADDR_OFF)); + dev_dbg(cec->dev, "RX MSG[%d]=0x%x\n", i, msg->msg[i]); + } + + mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_STOP); + + return true; +} + +static u32 mhdp_cec_write_message(struct cdns_mhdp_cec *cec, struct cec_msg *msg) +{ + u8 i; + + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + + if (msg->len > CEC_MAX_MSG_SIZE) { + dev_err(cec->dev, "Invalid MSG size!\n"); + return -EINVAL; + } + + for (i = 0; i < msg->len; ++i) + printk("msg[%d]=0x%x\n",i, msg->msg[i]); + + /* Write Message to register */ + for (i = 0; i < msg->len; ++i) { + mhdp_cec_write(cec, TX_MSG_HEADER + (i * REG_ADDR_OFF), + msg->msg[i]); + } + /* Write Message Length (payload + opcode) */ + mhdp_cec_write(cec, TX_MSG_LENGTH, msg->len - 1); + + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_TRANSMIT); + + return true; +} + +static int mhdp_cec_set_logical_addr(struct cdns_mhdp_cec *cec, u32 la) +{ + u8 la_reg; + u8 i; + + if (la == CEC_LOG_ADDR_INVALID) + /* invalid all LA address */ + for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) { + mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), 0); + return 0; + } + + /* In fact cdns mhdp cec could support max 5 La address */ + for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) { + la_reg = mhdp_cec_read(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF)); + /* Check LA already used */ + if (la_reg & 0x10) + continue; + + if ((la_reg & 0xF) == la) { + dev_warn(cec->dev, "Warning. LA already in use.\n"); + return 0; + } + + la = (la & 0xF) | (1 << 4); + + mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), la); + return 0; + } + + dev_warn(cec->dev, "All LA in use\n"); + + return -ENXIO; +} + +static int mhdp_cec_poll_worker(void *_cec) +{ + struct cdns_mhdp_cec *cec = (struct cdns_mhdp_cec *)_cec; + int num_rx_msgs, i; + int sts; + + set_freezable(); + + for (;;) { + if (kthread_freezable_should_stop(NULL)) + break; + + /* Check TX State */ + sts = mhdp_cec_read(cec, TX_MSG_STATUS); + switch (sts) { + case CEC_STS_SUCCESS: + cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, + 0); + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + break; + case CEC_STS_ERROR: + mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); + cec_transmit_done(cec->adap, + CEC_TX_STATUS_MAX_RETRIES | + CEC_TX_STATUS_NACK, 0, 1, 0, 0); + break; + case CEC_STS_BUSY: + default: + break; + } + + /* Check RX State */ + sts = mhdp_cec_read(cec, RX_MSG_STATUS); + num_rx_msgs = mhdp_cec_read(cec, NUM_OF_MSG_RX_BUF); + switch (sts) { + case CEC_STS_SUCCESS: + if (num_rx_msgs == 0xf) + num_rx_msgs = CEC_MAX_RX_MSGS; + + if (num_rx_msgs > CEC_MAX_RX_MSGS) { + dev_err(cec->dev, "Error rx msg num %d\n", + num_rx_msgs); + mhdp_cec_clear_rx_buffer(cec); + break; + } + + /* Rx FIFO Depth 2 RX MSG */ + for (i = 0; i < num_rx_msgs; i++) { + mhdp_cec_read_message(cec); + cec->msg.rx_status = CEC_RX_STATUS_OK; + cec_received_msg(cec->adap, &cec->msg); + } + break; + default: + break; + } + + if (!kthread_should_stop()) + schedule_timeout_idle(20); + } + + return 0; +} + +static int mhdp_cec_adap_enable(struct cec_adapter *adap, bool enable) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + if (enable) { + mhdp_cec_write(cec, DB_L_TIMER, 0x10); + mhdp_cec_set_divider(cec); + } else + mhdp_cec_set_divider(cec); + + return 0; +} + +static int mhdp_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + return mhdp_cec_set_logical_addr(cec, addr); +} + +static int mhdp_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); + + mhdp_cec_write_message(cec, msg); + + return 0; +} + +static const struct cec_adap_ops cdns_mhdp_cec_adap_ops = { + .adap_enable = mhdp_cec_adap_enable, + .adap_log_addr = mhdp_cec_adap_log_addr, + .adap_transmit = mhdp_cec_adap_transmit, +}; + +int cdns_mhdp_register_cec_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec; + int ret; + + cec->adap = cec_allocate_adapter(&cdns_mhdp_cec_adap_ops, cec, + CEC_NAME, + CEC_CAP_PHYS_ADDR | CEC_CAP_LOG_ADDRS | + CEC_CAP_TRANSMIT | CEC_CAP_PASSTHROUGH + | CEC_CAP_RC, CEC_MAX_LOG_ADDRS); + ret = PTR_ERR_OR_ZERO(cec->adap); + if (ret) + return ret; + ret = cec_register_adapter(cec->adap, dev); + if (ret) { + cec_delete_adapter(cec->adap); + return ret; + } + + cec->dev = dev; + + cec->cec_worker = kthread_create(mhdp_cec_poll_worker, cec, "cdns-mhdp-cec"); + if (IS_ERR(cec->cec_worker)) + dev_err(cec->dev, "failed create hdp cec thread\n"); + + wake_up_process(cec->cec_worker); + + dev_dbg(dev, "CEC successfuly probed\n"); + return 0; +} + +int cdns_mhdp_unregister_cec_driver(struct device *dev) +{ + struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); + struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec; + + if (cec->cec_worker) { + kthread_stop(cec->cec_worker); + cec->cec_worker = NULL; + } + cec_unregister_adapter(cec->adap); + return 0; +} + +MODULE_AUTHOR("Sandor.Yu@NXP.com"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("NXP CDNS MHDP HDMI CEC driver"); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c new file mode 100644 index 000000000000..91d1cfd4b2af --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c @@ -0,0 +1,795 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Author: Chris Zhong + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define CDNS_DP_SPDIF_CLK 200000000 +#define FW_ALIVE_TIMEOUT_US 1000000 +#define MAILBOX_RETRY_US 1000 +#define MAILBOX_TIMEOUT_US 5000000 + +#define mhdp_readx_poll_timeout(op, addr, offset, val, cond, sleep_us, timeout_us) \ +({ \ + u64 __timeout_us = (timeout_us); \ + unsigned long __sleep_us = (sleep_us); \ + ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \ + might_sleep_if((__sleep_us) != 0); \ + for (;;) { \ + (val) = op(addr, offset); \ + if (cond) \ + break; \ + if (__timeout_us && \ + ktime_compare(ktime_get(), __timeout) > 0) { \ + (val) = op(addr, offset); \ + break; \ + } \ + if (__sleep_us) \ + usleep_range((__sleep_us >> 2) + 1, __sleep_us); \ + } \ + (cond) ? 0 : -ETIMEDOUT; \ +}) + +u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset) +{ + u32 val; + + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { + /* Remap address to low 4K SAPB bus */ + writel(offset >> 12, mhdp->regs_sec + 0xc); + val = readl((offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, mhdp->regs_sec + 8); + val = readl((offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) + val = readl(mhdp->regs_sec + offset); + else + val = readl(mhdp->regs_base + offset); + + mutex_unlock(&mhdp->iolock); + + return val; +} +EXPORT_SYMBOL(cdns_mhdp_bus_read); + +void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset) +{ + mutex_lock(&mhdp->iolock); + + if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { + /* Remap address to low 4K SAPB bus */ + writel(offset >> 12, mhdp->regs_sec + 0xc); + writel(val, (offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { + /* Remap address to low 4K memory */ + writel(offset >> 12, mhdp->regs_sec + 8); + writel(val, (offset & 0xfff) + mhdp->regs_base); + } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) + writel(val, mhdp->regs_sec + offset); + else + writel(val, mhdp->regs_base + offset); + + mutex_unlock(&mhdp->iolock); +} +EXPORT_SYMBOL(cdns_mhdp_bus_write); + +u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp) +{ + return cdns_mhdp_bus_read(mhdp, SW_CLK_H); +} +EXPORT_SYMBOL(cdns_mhdp_get_fw_clk); + +void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk) +{ + cdns_mhdp_bus_write(clk / 1000000, mhdp, SW_CLK_H); +} +EXPORT_SYMBOL(cdns_mhdp_set_fw_clk); + +void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = DPTX_FRMR_DATA_CLK_RSTN_EN | + DPTX_FRMR_DATA_CLK_EN | + DPTX_PHY_DATA_RSTN_EN | + DPTX_PHY_DATA_CLK_EN | + DPTX_PHY_CHAR_RSTN_EN | + DPTX_PHY_CHAR_CLK_EN | + SOURCE_AUX_SYS_CLK_RSTN_EN | + SOURCE_AUX_SYS_CLK_EN | + DPTX_SYS_CLK_RSTN_EN | + DPTX_SYS_CLK_EN | + CFG_DPTX_VIF_CLK_RSTN_EN | + CFG_DPTX_VIF_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_DPTX_CAR); + + val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_PHY_CAR); + + val = SOURCE_PKT_SYS_RSTN_EN | + SOURCE_PKT_SYS_CLK_EN | + SOURCE_PKT_DATA_RSTN_EN | + SOURCE_PKT_DATA_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_PKT_CAR); + + val = SPDIF_CDR_CLK_RSTN_EN | + SPDIF_CDR_CLK_EN | + SOURCE_AIF_SYS_RSTN_EN | + SOURCE_AIF_SYS_CLK_EN | + SOURCE_AIF_CLK_RSTN_EN | + SOURCE_AIF_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_AIF_CAR); + + val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | + SOURCE_CIPHER_SYS_CLK_EN | + SOURCE_CIPHER_CHAR_CLK_RSTN_EN | + SOURCE_CIPHER_CHAR_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_CIPHER_CAR); + + val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN | + SOURCE_CRYPTO_SYS_CLK_EN; + cdns_mhdp_bus_write(val, mhdp, SOURCE_CRYPTO_CAR); + + /* enable Mailbox and PIF interrupt */ + cdns_mhdp_bus_write(0, mhdp, APB_INT_MASK); +} +EXPORT_SYMBOL(cdns_mhdp_clock_reset); + +bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp) +{ + u32 alive, newalive; + u8 retries_left = 50; + + alive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); + + while (retries_left--) { + udelay(2); + + newalive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); + if (alive == newalive) + continue; + return true; + } + return false; +} +EXPORT_SYMBOL(cdns_mhdp_check_alive); + +static int mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) +{ + int val, ret; + + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_EMPTY_ADDR, + val, !val, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + return cdns_mhdp_bus_read(mhdp, MAILBOX0_RD_DATA) & 0xff; +} + +static int mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val) +{ + int ret, full; + + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_FULL_ADDR, + full, !full, MAILBOX_RETRY_US, + MAILBOX_TIMEOUT_US); + if (ret < 0) + return ret; + + cdns_mhdp_bus_write(val, mhdp, MAILBOX0_WR_DATA); + + return 0; +} + +int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, + u8 module_id, u8 opcode, + u16 req_size) +{ + u32 mbox_size, i; + u8 header[4]; + int ret; + + /* read the header of the message */ + for (i = 0; i < 4; i++) { + ret = mhdp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + header[i] = ret; + } + + mbox_size = get_unaligned_be16(header + 2); + + if (opcode != header[0] || module_id != header[1] || + req_size != mbox_size) { + /* + * If the message in mailbox is not what we want, we need to + * clear the mailbox by reading its contents. + */ + for (i = 0; i < mbox_size; i++) + if (mhdp_mailbox_read(mhdp) < 0) + break; + + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_validate_receive); + +int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, + u8 *buff, u16 buff_size) +{ + u32 i; + int ret; + + for (i = 0; i < buff_size; i++) { + ret = mhdp_mailbox_read(mhdp); + if (ret < 0) + return ret; + + buff[i] = ret; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_read_receive); + +int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, + u8 opcode, u16 size, u8 *message) +{ + u8 header[4]; + int ret, i; + + header[0] = opcode; + header[1] = module_id; + put_unaligned_be16(size, header + 2); + + for (i = 0; i < 4; i++) { + ret = mhdp_mailbox_write(mhdp, header[i]); + if (ret) + return ret; + } + + for (i = 0; i < size; i++) { + ret = mhdp_mailbox_write(mhdp, message[i]); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_mailbox_send); + +int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) +{ + u8 msg[4], resp[8]; + u32 val; + int ret; + + if (addr == 0) { + ret = -EINVAL; + goto err_reg_read; + } + + put_unaligned_be32(addr, msg); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, + sizeof(msg), msg); + if (ret) + goto err_reg_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, + sizeof(resp)); + if (ret) + goto err_reg_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, resp, sizeof(resp)); + if (ret) + goto err_reg_read; + + /* Returned address value should be the same as requested */ + if (memcmp(msg, resp, sizeof(msg))) { + ret = -EINVAL; + goto err_reg_read; + } + + val = get_unaligned_be32(resp + 4); + + return val; +err_reg_read: + DRM_DEV_ERROR(mhdp->dev, "Failed to read register.\n"); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_reg_read); + +int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) +{ + u8 msg[8]; + + put_unaligned_be32(addr, msg); + put_unaligned_be32(val, msg + 4); + + return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_WRITE_REGISTER, sizeof(msg), msg); +} +EXPORT_SYMBOL(cdns_mhdp_reg_write); + +int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr, + u8 start_bit, u8 bits_no, u32 val) +{ + u8 field[8]; + + put_unaligned_be16(addr, field); + field[2] = start_bit; + field[3] = bits_no; + put_unaligned_be32(val, field + 4); + + return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_FIELD, sizeof(field), field); +} +EXPORT_SYMBOL(cdns_mhdp_reg_write_bit); + +int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem, + u32 i_size, const u32 *d_mem, u32 d_size) +{ + u32 reg; + int i, ret; + + /* reset ucpu before load firmware*/ + cdns_mhdp_bus_write(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET, + mhdp, APB_CTRL); + + for (i = 0; i < i_size; i += 4) + cdns_mhdp_bus_write(*i_mem++, mhdp, ADDR_IMEM + i); + + for (i = 0; i < d_size; i += 4) + cdns_mhdp_bus_write(*d_mem++, mhdp, ADDR_DMEM + i); + + /* un-reset ucpu */ + cdns_mhdp_bus_write(0, mhdp, APB_CTRL); + + /* check the keep alive register to make sure fw working */ + ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, KEEP_ALIVE, + reg, reg, 2000, FW_ALIVE_TIMEOUT_US); + if (ret < 0) { + DRM_DEV_ERROR(mhdp->dev, "failed to loaded the FW reg = %x\n", + reg); + return -EINVAL; + } + + reg = cdns_mhdp_bus_read(mhdp, VER_L) & 0xff; + mhdp->fw_version = reg; + reg = cdns_mhdp_bus_read(mhdp, VER_H) & 0xff; + mhdp->fw_version |= reg << 8; + reg = cdns_mhdp_bus_read(mhdp, VER_LIB_L_ADDR) & 0xff; + mhdp->fw_version |= reg << 16; + reg = cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) & 0xff; + mhdp->fw_version |= reg << 24; + + DRM_DEV_DEBUG(mhdp->dev, "firmware version: %x\n", mhdp->fw_version); + + return 0; +} +EXPORT_SYMBOL(cdns_mhdp_load_firmware); + +int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable) +{ + u8 msg[5]; + int ret, i; + + msg[0] = GENERAL_MAIN_CONTROL; + msg[1] = MB_MODULE_ID_GENERAL; + msg[2] = 0; + msg[3] = 1; + msg[4] = enable ? FW_ACTIVE : FW_STANDBY; + + for (i = 0; i < sizeof(msg); i++) { + ret = mhdp_mailbox_write(mhdp, msg[i]); + if (ret) + goto err_set_firmware_active; + } + + /* read the firmware state */ + for (i = 0; i < sizeof(msg); i++) { + ret = mhdp_mailbox_read(mhdp); + if (ret < 0) + goto err_set_firmware_active; + + msg[i] = ret; + } + + ret = 0; + +err_set_firmware_active: + if (ret < 0) + DRM_DEV_ERROR(mhdp->dev, "set firmware active failed\n"); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_firmware_active); + +int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip) +{ + u8 msg[8]; + int ret; + + msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate); + msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN; + msg[2] = VOLTAGE_LEVEL_2; + msg[3] = PRE_EMPHASIS_LEVEL_3; + msg[4] = PTS1 | PTS2 | PTS3 | PTS4; + msg[5] = FAST_LT_NOT_SUPPORT; + msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL; + msg[7] = ENHANCED; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_SET_HOST_CAPABILITIES, + sizeof(msg), msg); + if (ret) + goto err_set_host_cap; + +/* TODO Sandor */ +// ret = cdns_mhdp_reg_write(mhdp, DP_AUX_SWAP_INVERSION_CONTROL, +// AUX_HOST_INVERT); + +err_set_host_cap: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set host cap failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_host_cap); + +int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp) +{ + u8 msg[5]; + int ret; + + memset(msg, 0, sizeof(msg)); + + msg[0] = MHDP_EVENT_ENABLE_HPD | MHDP_EVENT_ENABLE_TRAINING; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_ENABLE_EVENT, sizeof(msg), msg); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set event config failed: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_event_config); + +u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp) +{ + return cdns_mhdp_bus_read(mhdp, SW_EVENTS0); +} +EXPORT_SYMBOL(cdns_mhdp_get_event); + +int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp) +{ + u8 status; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, + 0, NULL); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, + GENERAL_GET_HPD_STATE, sizeof(status)); + if (ret) + goto err_get_hpd; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); + if (ret) + goto err_get_hpd; + + return status; + +err_get_hpd: + DRM_ERROR("read hpd failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_read_hpd); + +int cdns_mhdp_get_edid_block(void *data, u8 *edid, + unsigned int block, size_t length) +{ + struct cdns_mhdp_device *mhdp = data; + u8 msg[2], reg[2], i; + int ret; + + for (i = 0; i < 4; i++) { + msg[0] = block / 2; + msg[1] = block % 2; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_GET_EDID, sizeof(msg), msg); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, + MB_MODULE_ID_DP_TX, + DPTX_GET_EDID, + sizeof(reg) + length); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); + if (ret) + continue; + + if (reg[0] == length && reg[1] == block / 2) + break; + } + + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed: %d\n", + block, ret); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_get_edid_block); + +int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active) +{ + u8 msg; + int ret; + + msg = !!active; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_SET_VIDEO, sizeof(msg), &msg); + if (ret) + DRM_DEV_ERROR(mhdp->dev, "set video status failed: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_set_video_status); + +static int mhdp_get_msa_misc(struct video_info *video, + struct drm_display_mode *mode) +{ + u32 msa_misc; + u8 val[2] = {0}; + + switch (video->color_fmt) { + case PXL_RGB: + case Y_ONLY: + val[0] = 0; + break; + /* set YUV default color space conversion to BT601 */ + case YCBCR_4_4_4: + val[0] = 6 + BT_601 * 8; + break; + case YCBCR_4_2_2: + val[0] = 5 + BT_601 * 8; + break; + case YCBCR_4_2_0: + val[0] = 5; + break; + } + + switch (video->color_depth) { + case 6: + val[1] = 0; + break; + case 8: + val[1] = 1; + break; + case 10: + val[1] = 2; + break; + case 12: + val[1] = 3; + break; + case 16: + val[1] = 4; + break; + } + + msa_misc = 2 * val[0] + 32 * val[1] + + ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0); + + return msa_misc; +} + +int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp) +{ + struct video_info *video = &mhdp->video_info; + struct drm_display_mode *mode = &mhdp->mode; + u64 symbol; + u32 val, link_rate, rem; + u8 bit_per_pix, tu_size_reg = TU_SIZE; + int ret; + + bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? + (video->color_depth * 2) : (video->color_depth * 3); + + link_rate = mhdp->dp.rate / 1000; + + ret = cdns_mhdp_reg_write(mhdp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, 0); + if (ret) + goto err_config_video; + + /* + * get a best tu_size and valid symbol: + * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32 + * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes) + * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set + * TU += 2 and repeat 2nd step. + */ + do { + tu_size_reg += 2; + symbol = tu_size_reg * mode->clock * bit_per_pix; + do_div(symbol, mhdp->dp.num_lanes * link_rate * 8); + rem = do_div(symbol, 1000); + if (tu_size_reg > 64) { + ret = -EINVAL; + DRM_DEV_ERROR(mhdp->dev, + "tu error, clk:%d, lanes:%d, rate:%d\n", + mode->clock, mhdp->dp.num_lanes, + link_rate); + goto err_config_video; + } + } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || + (rem > 850) || (rem < 100)); + + val = symbol + (tu_size_reg << 8); + val |= TU_CNT_RST_EN; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_TU, val); + if (ret) + goto err_config_video; + + /* set the FIFO Buffer size */ + val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; + val /= (mhdp->dp.num_lanes * link_rate); + val = div_u64(8 * (symbol + 1), bit_per_pix) - val; + val += 2; + ret = cdns_mhdp_reg_write(mhdp, DP_VC_TABLE(15), val); + + switch (video->color_depth) { + case 6: + val = BCS_6; + break; + case 8: + val = BCS_8; + break; + case 10: + val = BCS_10; + break; + case 12: + val = BCS_12; + break; + case 16: + val = BCS_16; + break; + } + + val += video->color_fmt << 8; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_PXL_REPR, val); + if (ret) + goto err_config_video; + + val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; + val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; + ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_SP, val); + if (ret) + goto err_config_video; + + val = (mode->hsync_start - mode->hdisplay) << 16; + val |= mode->htotal - mode->hsync_end; + ret = cdns_mhdp_reg_write(mhdp, DP_FRONT_BACK_PORCH, val); + if (ret) + goto err_config_video; + + val = mode->hdisplay * bit_per_pix / 8; + ret = cdns_mhdp_reg_write(mhdp, DP_BYTE_COUNT, val); + if (ret) + goto err_config_video; + + val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); + ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_0, val); + if (ret) + goto err_config_video; + + val = mode->hsync_end - mode->hsync_start; + val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); + ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_1, val); + if (ret) + goto err_config_video; + + val = mode->vtotal; + val |= (mode->vtotal - mode->vsync_start) << 16; + ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_0, val); + if (ret) + goto err_config_video; + + val = mode->vsync_end - mode->vsync_start; + val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); + ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_1, val); + if (ret) + goto err_config_video; + + val = mhdp_get_msa_misc(video, mode); + ret = cdns_mhdp_reg_write(mhdp, MSA_MISC, val); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write(mhdp, STREAM_CONFIG, 1); + if (ret) + goto err_config_video; + + val = mode->hsync_end - mode->hsync_start; + val |= mode->hdisplay << 16; + ret = cdns_mhdp_reg_write(mhdp, DP_HORIZONTAL, val); + if (ret) + goto err_config_video; + + val = mode->vdisplay; + val |= (mode->vtotal - mode->vsync_start) << 16; + ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_0, val); + if (ret) + goto err_config_video; + + val = mode->vtotal; + ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_1, val); + if (ret) + goto err_config_video; + + ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 2, 1, 0); + +err_config_video: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "config video failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_config_video); + +int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) +{ + return cdns_mhdp_reg_write(mhdp, ADDR_PHY_AFE + (addr << 2), val); +} +EXPORT_SYMBOL(cdns_phy_reg_write); + +u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) +{ + return cdns_mhdp_reg_read(mhdp, ADDR_PHY_AFE + (addr << 2)); +} +EXPORT_SYMBOL(cdns_phy_reg_read); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c new file mode 100644 index 000000000000..f025c39d12ea --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include + +#define LINK_TRAINING_TIMEOUT_MS 500 +#define LINK_TRAINING_RETRY_MS 20 + +int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, + u32 addr, u8 *data, u16 len) +{ + u8 msg[5], reg[5]; + int ret; + + put_unaligned_be16(len, msg); + put_unaligned_be24(addr, msg + 2); + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_DPCD, sizeof(msg), msg); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_DPCD, + sizeof(reg) + len); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_dpcd_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); + +err_dpcd_read: + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_dpcd_read); + +int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value) +{ + u8 msg[6], reg[5]; + int ret; + + put_unaligned_be16(1, msg); + put_unaligned_be24(addr, msg + 2); + msg[5] = value; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_DPCD, sizeof(msg), msg); + if (ret) + goto err_dpcd_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_WRITE_DPCD, sizeof(reg)); + if (ret) + goto err_dpcd_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_dpcd_write; + + if (addr != get_unaligned_be24(reg + 2)) + ret = -EINVAL; + +err_dpcd_write: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "dpcd write failed: %d\n", ret); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_dpcd_write); + +static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp) +{ + unsigned long timeout; + u8 msg, event[2]; + int ret; + + msg = LINK_TRAINING_RUN; + + /* start training */ + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_TRAINING_CONTROL, sizeof(msg), &msg); + if (ret) + goto err_training_start; + + timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS); + while (time_before(jiffies, timeout)) { + msleep(LINK_TRAINING_RETRY_MS); + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_EVENT, 0, NULL); + if (ret) + goto err_training_start; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, + MB_MODULE_ID_DP_TX, + DPTX_READ_EVENT, + sizeof(event)); + if (ret) + goto err_training_start; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, event, + sizeof(event)); + if (ret) + goto err_training_start; + + if (event[1] & EQ_PHASE_FINISHED) + return 0; + } + + ret = -ETIMEDOUT; + +err_training_start: + DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret); + return ret; +} + +static int cdns_mhdp_get_training_status(struct cdns_mhdp_device *mhdp) +{ + u8 status[10]; + int ret; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_LINK_STAT, 0, NULL); + if (ret) + goto err_get_training_status; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, + DPTX_READ_LINK_STAT, + sizeof(status)); + if (ret) + goto err_get_training_status; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); + if (ret) + goto err_get_training_status; + + mhdp->dp.rate = drm_dp_bw_code_to_link_rate(status[0]); + mhdp->dp.num_lanes = status[1]; + +err_get_training_status: + if (ret) + DRM_DEV_ERROR(mhdp->dev, "get training status failed: %d\n", + ret); + return ret; +} + +int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp) +{ + int ret; + + ret = cdns_mhdp_training_start(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to start training %d\n", + ret); + return ret; + } + + ret = cdns_mhdp_get_training_status(mhdp); + if (ret) { + DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat %d\n", + ret); + return ret; + } + + DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->dp.rate, + mhdp->dp.num_lanes); + return ret; +} +EXPORT_SYMBOL(cdns_mhdp_train_link); diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c new file mode 100644 index 000000000000..c37a7ac6af9b --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2019 NXP Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp, + u8 entry_id, u8 packet_len, u8 *packet, u8 packet_type) +{ + u32 *packet32, len32; + u32 val, i; + + /* invalidate entry */ + val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id); + cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); + cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); + + /* flush fifo 1 */ + cdns_mhdp_bus_write(F_FIFO1_FLUSH(1), mhdp, SOURCE_PIF_FIFO1_FLUSH); + + /* write packet into memory */ + packet32 = (u32 *)packet; + len32 = packet_len / 4; + for (i = 0; i < len32; i++) + cdns_mhdp_bus_write(F_DATA_WR(packet32[i]), mhdp, SOURCE_PIF_DATA_WR); + + /* write entry id */ + cdns_mhdp_bus_write(F_WR_ADDR(entry_id), mhdp, SOURCE_PIF_WR_ADDR); + + /* write request */ + cdns_mhdp_bus_write(F_HOST_WR(1), mhdp, SOURCE_PIF_WR_REQ); + + /* update entry */ + val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) | + F_PACKET_TYPE(packet_type) | F_PKT_ALLOC_ADDRESS(entry_id); + cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); + + cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); +} + +int cdns_hdmi_get_edid_block(void *data, u8 *edid, + u32 block, size_t length) +{ + struct cdns_mhdp_device *mhdp = data; + u8 msg[2], reg[5], i; + int ret; + + for (i = 0; i < 4; i++) { + msg[0] = block / 2; + msg[1] = block % 2; + + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID, + sizeof(msg), msg); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_EDID, sizeof(reg) + length); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + continue; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); + if (ret) + continue; + + if ((reg[3] << 8 | reg[4]) == length) + break; + } + + if (ret) + DRM_ERROR("get block[%d] edid failed: %d\n", block, ret); + return ret; +} + +int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data) +{ + u8 msg[4], reg[6]; + int ret; + + msg[0] = 0x54; + msg[1] = addr; + msg[2] = 0; + msg[3] = 1; + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_READ, + sizeof(msg), msg); + if (ret) + goto err_scdc_read; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_READ, sizeof(reg)); + if (ret) + goto err_scdc_read; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_scdc_read; + + *data = reg[5]; + +err_scdc_read: + if (ret) + DRM_ERROR("scdc read failed: %d\n", ret); + return ret; +} + +int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value) +{ + u8 msg[5], reg[5]; + int ret; + + msg[0] = 0x54; + msg[1] = addr; + msg[2] = 0; + msg[3] = 1; + msg[4] = value; + ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE, + sizeof(msg), msg); + if (ret) + goto err_scdc_write; + + ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, + HDMI_TX_WRITE, sizeof(reg)); + if (ret) + goto err_scdc_write; + + ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); + if (ret) + goto err_scdc_write; + + if (reg[0] != 0) + ret = -EINVAL; + +err_scdc_write: + if (ret) + DRM_ERROR("scdc write failed: %d\n", ret); + return ret; +} + +int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, + int protocol, + u32 char_rate) +{ + u32 reg0; + u32 reg1; + u32 val; + int ret; + + /* Set PHY to HDMI data */ + ret = cdns_mhdp_reg_write(mhdp, PHY_DATA_SEL, F_SOURCE_PHY_MHDP_SEL(1)); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_HPD, + F_HPD_VALID_WIDTH(4) | F_HPD_GLITCH_WIDTH(0)); + if (ret < 0) + return ret; + + /* open CARS */ + ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3); + if (ret < 0) + return ret; + + reg0 = reg1 = 0x7c1f; + if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) { + reg0 = 0; + reg1 = 0xFFFFF; + } + ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_0, reg0); + if (ret < 0) + return ret; + ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_1, reg1); + if (ret < 0) + return ret; + + /* set hdmi mode and preemble mode data enable */ + val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) | F_DATA_EN(1) | + F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + + return ret; +} + +int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, + struct drm_display_mode *mode, + struct video_info *video_info) +{ + int ret; + u32 val; + u32 vsync_lines = mode->vsync_end - mode->vsync_start; + u32 eof_lines = mode->vsync_start - mode->vdisplay; + u32 sof_lines = mode->vtotal - mode->vsync_end; + u32 hblank = mode->htotal - mode->hdisplay; + u32 hactive = mode->hdisplay; + u32 vblank = mode->vtotal - mode->vdisplay; + u32 vactive = mode->vdisplay; + u32 hfront = mode->hsync_start - mode->hdisplay; + u32 hback = mode->htotal - mode->hsync_end; + u32 vfront = eof_lines; + u32 hsync = hblank - hfront - hback; + u32 vsync = vsync_lines; + u32 vback = sof_lines; + u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) + + ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2); + + ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_H_SIZE, (hactive << 16) + hblank); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_V_SIZE, (vactive << 16) + vblank); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_FRONT_WIDTH, (vfront << 16) + hfront); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_SYNC_WIDTH, (vsync << 16) + hsync); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_BACK_WIDTH, (vback << 16) + hback); + if (ret < 0) + return ret; + + ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, v_h_polarity); + if (ret < 0) + return ret; + + /* Reset Data Enable */ + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val &= ~F_DATA_EN(1); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + if (ret < 0) + return ret; + + /* Set bpc */ + val &= ~F_VIF_DATA_WIDTH(3); + switch (video_info->color_depth) { + case 10: + val |= F_VIF_DATA_WIDTH(1); + break; + case 12: + val |= F_VIF_DATA_WIDTH(2); + break; + case 16: + val |= F_VIF_DATA_WIDTH(3); + break; + case 8: + default: + val |= F_VIF_DATA_WIDTH(0); + break; + } + + /* select color encoding */ + val &= ~F_HDMI_ENCODING(3); + switch (video_info->color_fmt) { + case YCBCR_4_4_4: + val |= F_HDMI_ENCODING(2); + break; + case YCBCR_4_2_2: + val |= F_HDMI_ENCODING(1); + break; + case YCBCR_4_2_0: + val |= F_HDMI_ENCODING(3); + break; + case PXL_RGB: + default: + val |= F_HDMI_ENCODING(0); + break; + } + + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + if (ret < 0) + return ret; + + /* set data enable */ + val |= F_DATA_EN(1); + ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); + + return ret; +} + +int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val &= ~F_GCP_EN(1); + + return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); +} + +int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp) +{ + u32 val; + + val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); + val |= F_GCP_EN(1); + + return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); +} diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h new file mode 100644 index 000000000000..399c3f6f86ad --- /dev/null +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Cadence MHDP DP MST bridge driver. + * + * Copyright: 2018 Cadence Design Systems, Inc. + * + * Author: Quentin Schulz + */ + + +#ifndef CDNS_MHDP_H +#define CDNS_MHDP_H + +#include + +#define CDNS_APB_CFG 0x00000 +#define CDNS_APB_CTRL (CDNS_APB_CFG + 0x00) +#define CDNS_MAILBOX_FULL (CDNS_APB_CFG + 0x08) +#define CDNS_MAILBOX_EMPTY (CDNS_APB_CFG + 0x0c) +#define CDNS_MAILBOX_TX_DATA (CDNS_APB_CFG + 0x10) +#define CDNS_MAILBOX_RX_DATA (CDNS_APB_CFG + 0x14) +#define CDNS_KEEP_ALIVE (CDNS_APB_CFG + 0x18) +#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0) + +#define CDNS_MB_INT_MASK (CDNS_APB_CFG + 0x34) + +#define CDNS_SW_CLK_L (CDNS_APB_CFG + 0x3c) +#define CDNS_SW_CLK_H (CDNS_APB_CFG + 0x40) +#define CDNS_SW_EVENT0 (CDNS_APB_CFG + 0x44) +#define CDNS_DPTX_HPD BIT(0) + +#define CDNS_SW_EVENT1 (CDNS_APB_CFG + 0x48) +#define CDNS_SW_EVENT2 (CDNS_APB_CFG + 0x4c) +#define CDNS_SW_EVENT3 (CDNS_APB_CFG + 0x50) + +#define CDNS_APB_INT_MASK (CDNS_APB_CFG + 0x6C) +#define CDNS_APB_INT_MASK_MAILBOX_INT BIT(0) +#define CDNS_APB_INT_MASK_SW_EVENT_INT BIT(1) + +#define CDNS_DPTX_CAR (CDNS_APB_CFG + 0x904) +#define CDNS_VIF_CLK_EN BIT(0) +#define CDNS_VIF_CLK_RSTN BIT(1) + +#define CDNS_SOURCE_VIDEO_IF(s) (0x00b00 + (s * 0x20)) +#define CDNS_BND_HSYNC2VSYNC(s) (CDNS_SOURCE_VIDEO_IF(s) + \ + 0x00) +#define CDNS_IP_DTCT_WIN GENMASK(11, 0) +#define CDNS_IP_DET_INTERLACE_FORMAT BIT(12) +#define CDNS_IP_BYPASS_V_INTERFACE BIT(13) + +#define CDNS_HSYNC2VSYNC_POL_CTRL(s) (CDNS_SOURCE_VIDEO_IF(s) + \ + 0x10) +#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW BIT(1) +#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW BIT(2) + +#define CDNS_DPTX_PHY_CONFIG 0x02000 +#define CDNS_PHY_TRAINING_EN BIT(0) +#define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1) +#define CDNS_PHY_SCRAMBLER_BYPASS BIT(5) +#define CDNS_PHY_ENCODER_BYPASS BIT(6) +#define CDNS_PHY_SKEW_BYPASS BIT(7) +#define CDNS_PHY_TRAINING_AUTO BIT(8) +#define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9) +#define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12) +#define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15) +#define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18) +#define CDNS_PHY_COMMON_CONFIG (CDNS_PHY_LANE1_SKEW(1) | \ + CDNS_PHY_LANE2_SKEW(2) | \ + CDNS_PHY_LANE3_SKEW(3)) +#define CDNS_PHY_10BIT_EN BIT(21) + +#define CDNS_DPTX_FRAMER 0x02200 +#define CDNS_DP_FRAMER_GLOBAL_CONFIG (CDNS_DPTX_FRAMER + 0x00) +#define CDNS_DP_NUM_LANES(x) (x - 1) +#define CDNS_DP_MST_EN BIT(2) +#define CDNS_DP_FRAMER_EN BIT(3) +#define CDNS_DP_RATE_GOVERNOR_EN BIT(4) +#define CDNS_DP_NO_VIDEO_MODE BIT(5) +#define CDNS_DP_DISABLE_PHY_RST BIT(6) +#define CDNS_DP_WR_FAILING_EDGE_VSYNC BIT(7) + +#define CDNS_DP_SW_RESET (CDNS_DPTX_FRAMER + 0x04) +#define CDNS_DP_FRAMER_TU (CDNS_DPTX_FRAMER + 0x08) +#define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8) +#define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0)) +#define CDNS_DP_FRAMER_TU_CNT_RST_EN BIT(15) + +#define CDNS_DPTX_STREAM(s) (0x03000 + s * 0x80) +#define CDNS_DP_MSA_HORIZONTAL_0(s) (CDNS_DPTX_STREAM(s) + 0x00) +#define CDNS_DP_MSAH0_H_TOTAL(x) (x) +#define CDNS_DP_MSAH0_HSYNC_START(x) ((x) << 16) + +#define CDNS_DP_MSA_HORIZONTAL_1(s) (CDNS_DPTX_STREAM(s) + 0x04) +#define CDNS_DP_MSAH1_HSYNC_WIDTH(x) (x) +#define CDNS_DP_MSAH1_HSYNC_POL_LOW BIT(15) +#define CDNS_DP_MSAH1_HDISP_WIDTH(x) ((x) << 16) + +#define CDNS_DP_MSA_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x08) +#define CDNS_DP_MSAV0_V_TOTAL(x) (x) +#define CDNS_DP_MSAV0_VSYNC_START(x) ((x) << 16) + +#define CDNS_DP_MSA_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x0c) +#define CDNS_DP_MSAV1_VSYNC_WIDTH(x) (x) +#define CDNS_DP_MSAV1_VSYNC_POL_LOW BIT(15) +#define CDNS_DP_MSAV1_VDISP_WIDTH(x) ((x) << 16) + +#define CDNS_DP_MSA_MISC(s) (CDNS_DPTX_STREAM(s) + 0x10) +#define CDNS_DP_STREAM_CONFIGs(s) (CDNS_DPTX_STREAM(s) + 0x14) +#define CDNS_DP_STREAM_CONFIG_2(s) (CDNS_DPTX_STREAM(s) + 0x2c) +#define CDNS_DP_SC2_TU_VS_DIFF(x) ((x) << 8) + +#define CDNS_DP_HORIZONTAL(s) (CDNS_DPTX_STREAM(s) + 0x30) +#define CDNS_DP_H_HSYNC_WIDTH(x) (x) +#define CDNS_DP_H_H_TOTAL(x) ((x) << 16) + +#define CDNS_DP_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x34) +#define CDNS_DP_V0_VHEIGHT(x) (x) +#define CDNS_DP_V0_VSTART(x) ((x) << 16) + +#define CDNS_DP_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x38) +#define CDNS_DP_V1_VTOTAL(x) (x) +#define CDNS_DP_V1_VTOTAL_EVEN BIT(16) + +#define CDNS_DP_FRAMER_PXL_REPR(s) (CDNS_DPTX_STREAM(s) + 0x4c) +#define CDNS_DP_FRAMER_6_BPC BIT(0) +#define CDNS_DP_FRAMER_8_BPC BIT(1) +#define CDNS_DP_FRAMER_10_BPC BIT(2) +#define CDNS_DP_FRAMER_12_BPC BIT(3) +#define CDNS_DP_FRAMER_16_BPC BIT(4) +#define CDNS_DP_FRAMER_PXL_FORMAT 0x8 +#define CDNS_DP_FRAMER_RGB BIT(0) +#define CDNS_DP_FRAMER_YCBCR444 BIT(1) +#define CDNS_DP_FRAMER_YCBCR422 BIT(2) +#define CDNS_DP_FRAMER_YCBCR420 BIT(3) +#define CDNS_DP_FRAMER_Y_ONLY BIT(4) + +#define CDNS_DP_FRAMER_SP(s) (CDNS_DPTX_STREAM(s) + 0x10) +#define CDNS_DP_FRAMER_VSYNC_POL_LOW BIT(0) +#define CDNS_DP_FRAMER_HSYNC_POL_LOW BIT(1) +#define CDNS_DP_FRAMER_INTERLACE BIT(2) + +#define CDNS_DP_LINE_THRESH(s) (CDNS_DPTX_STREAM(s) + 0x64) +#define CDNS_DP_ACTIVE_LINE_THRESH(x) (x) + +#define CDNS_DP_VB_ID(s) (CDNS_DPTX_STREAM(s) + 0x68) +#define CDNS_DP_VB_ID_INTERLACED BIT(2) +#define CDNS_DP_VB_ID_COMPRESSED BIT(6) + +#define CDNS_DP_FRONT_BACK_PORCH(s) (CDNS_DPTX_STREAM(s) + 0x78) +#define CDNS_DP_BACK_PORCH(x) (x) +#define CDNS_DP_FRONT_PORCH(x) ((x) << 16) + +#define CDNS_DP_BYTE_COUNT(s) (CDNS_DPTX_STREAM(s) + 0x7c) +#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16 + +#define CDNS_DP_MST_STREAM_CONFIG(s) (CDNS_DPTX_STREAM(s) + 0x14) +#define CDNS_DP_MST_STRM_CFG_STREAM_EN BIT(0) +#define CDNS_DP_MST_STRM_CFG_NO_VIDEO BIT(1) + +#define CDNS_DP_MST_SLOT_ALLOCATE(s) (CDNS_DPTX_STREAM(s) + 0x44) +#define CDNS_DP_S_ALLOC_START_SLOT(x) (x) +#define CDNS_DP_S_ALLOC_END_SLOT(x) ((x) << 8) + +#define CDNS_DP_RATE_GOVERNING(s) (CDNS_DPTX_STREAM(s) + 0x48) +#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x) (x) +#define CDNS_DP_RG_TARG_AV_SLOTS_X(x) (x << 4) +#define CDNS_DP_RG_ENABLE BIT(10) + +#define CDNS_DP_MTPH_CONTROL 0x2264 +#define CDNS_DP_MTPH_ECF_EN BIT(0) +#define CDNS_DP_MTPH_ACT_EN BIT(1) +#define CDNS_DP_MTPH_LVP_EN BIT(2) + +#define CDNS_DP_MTPH_STATUS 0x226C +#define CDNS_DP_MTPH_ACT_STATUS BIT(0) + + +#define CDNS_DPTX_GLOBAL 0x02300 +#define CDNS_DP_LANE_EN (CDNS_DPTX_GLOBAL + 0x00) +#define CDNS_DP_LANE_EN_LANES(x) GENMASK(x - 1, 0) +#define CDNS_DP_ENHNCD (CDNS_DPTX_GLOBAL + 0x04) + + +#define to_mhdp_connector(x) container_of(x, struct cdns_mhdp_connector, base) +#define to_mhdp_bridge(x) container_of(x, struct cdns_mhdp_bridge, base) +#define mgr_to_mhdp(x) container_of(x, struct cdns_mhdp_device, mst_mgr) + +#define CDNS_MHDP_MAX_STREAMS 4 + +enum pixel_format { + PIXEL_FORMAT_RGB = 1, + PIXEL_FORMAT_YCBCR_444 = 2, + PIXEL_FORMAT_YCBCR_422 = 4, + PIXEL_FORMAT_YCBCR_420 = 8, + PIXEL_FORMAT_Y_ONLY = 16, +}; + + +int cdns_mhdp_mst_init(struct cdns_mhdp_device *mhdp); +void cdns_mhdp_mst_deinit(struct cdns_mhdp_device *mhdp); +bool cdns_mhdp_mst_probe(struct cdns_mhdp_device *mhdp); +enum pixel_format cdns_mhdp_get_pxlfmt(u32 color_formats); +u32 cdns_mhdp_get_bpp(u32 bpc, u32 color_formats); +void cdns_mhdp_configure_video(struct drm_bridge *bridge); +void cdns_mhdp_mst_enable(struct drm_bridge *bridge); +void cdns_mhdp_mst_disable(struct drm_bridge *bridge); +void cdns_mhdp_enable(struct drm_bridge *bridge); + +#endif diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 17a9e7eb2130..bd013659404f 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -8,7 +8,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o -rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o +rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index a4a45daf93f2..058bc372f02b 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -23,11 +23,10 @@ #include #include "cdn-dp-core.h" -#include "cdn-dp-reg.h" #include "rockchip_drm_vop.h" static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector) { - return container_of(connector, struct cdn_dp_device, connector); + return container_of(connector, struct cdn_dp_device, mhdp.connector.base); } @@ -62,17 +61,18 @@ MODULE_DEVICE_TABLE(of, cdn_dp_dt_ids); static int cdn_dp_grf_write(struct cdn_dp_device *dp, unsigned int reg, unsigned int val) { + struct device *dev = dp->mhdp.dev; int ret; ret = clk_prepare_enable(dp->grf_clk); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); + DRM_DEV_ERROR(dev, "Failed to prepare_enable grf clock\n"); return ret; } ret = regmap_write(dp->grf, reg, val); if (ret) { - DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); + DRM_DEV_ERROR(dev, "Could not write to GRF: %d\n", ret); clk_disable_unprepare(dp->grf_clk); return ret; } @@ -83,24 +83,25 @@ static int cdn_dp_grf_write(struct cdn_dp_device *dp, static int cdn_dp_clk_enable(struct cdn_dp_device *dp) { + struct device *dev = dp->mhdp.dev; int ret; unsigned long rate; ret = clk_prepare_enable(dp->pclk); if (ret < 0) { - DRM_DEV_ERROR(dp->dev, "cannot enable dp pclk %d\n", ret); + DRM_DEV_ERROR(dev, "cannot enable dp pclk %d\n", ret); goto err_pclk; } ret = clk_prepare_enable(dp->core_clk); if (ret < 0) { - DRM_DEV_ERROR(dp->dev, "cannot enable core_clk %d\n", ret); + DRM_DEV_ERROR(dev, "cannot enable core_clk %d\n", ret); goto err_core_clk; } - ret = pm_runtime_get_sync(dp->dev); + ret = pm_runtime_get_sync(dev); if (ret < 0) { - DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret); + DRM_DEV_ERROR(dev, "cannot get pm runtime %d\n", ret); goto err_pm_runtime_get; } @@ -113,18 +114,18 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) rate = clk_get_rate(dp->core_clk); if (!rate) { - DRM_DEV_ERROR(dp->dev, "get clk rate failed\n"); + DRM_DEV_ERROR(dev, "get clk rate failed\n"); ret = -EINVAL; goto err_set_rate; } - cdn_dp_set_fw_clk(dp, rate); - cdn_dp_clock_reset(dp); + cdns_mhdp_set_fw_clk(&dp->mhdp, rate); + cdns_mhdp_clock_reset(&dp->mhdp); return 0; err_set_rate: - pm_runtime_put(dp->dev); + pm_runtime_put(dev); err_pm_runtime_get: clk_disable_unprepare(dp->core_clk); err_core_clk: @@ -135,7 +136,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) static void cdn_dp_clk_disable(struct cdn_dp_device *dp) { - pm_runtime_put_sync(dp->dev); + pm_runtime_put_sync(dp->mhdp.dev); clk_disable_unprepare(dp->pclk); clk_disable_unprepare(dp->core_clk); } @@ -168,7 +169,7 @@ static int cdn_dp_get_sink_count(struct cdn_dp_device *dp, u8 *sink_count) u8 value; *sink_count = 0; - ret = cdn_dp_dpcd_read(dp, DP_SINK_COUNT, &value, 1); + ret = drm_dp_dpcd_read(&dp->mhdp.dp.aux, DP_SINK_COUNT, &value, 1); if (ret) return ret; @@ -192,12 +193,13 @@ static struct cdn_dp_port *cdn_dp_connected_port(struct cdn_dp_device *dp) static bool cdn_dp_check_sink_connection(struct cdn_dp_device *dp) { + struct device *dev = dp->mhdp.dev; unsigned long timeout = jiffies + msecs_to_jiffies(CDN_DPCD_TIMEOUT_MS); struct cdn_dp_port *port; u8 sink_count = 0; if (dp->active_port < 0 || dp->active_port >= dp->ports) { - DRM_DEV_ERROR(dp->dev, "active_port is wrong!\n"); + DRM_DEV_ERROR(dev, "active_port is wrong!\n"); return false; } @@ -219,7 +221,7 @@ static bool cdn_dp_check_sink_connection(struct cdn_dp_device *dp) usleep_range(5000, 10000); } - DRM_DEV_ERROR(dp->dev, "Get sink capability timed out\n"); + DRM_DEV_ERROR(dev, "Get sink capability timed out\n"); return false; } @@ -261,7 +263,8 @@ static int cdn_dp_connector_get_modes(struct drm_connector *connector) mutex_lock(&dp->lock); edid = dp->edid; if (edid) { - DRM_DEV_DEBUG_KMS(dp->dev, "got edid: width[%d] x height[%d]\n", + DRM_DEV_DEBUG_KMS(dp->mhdp.dev, + "got edid: width[%d] x height[%d]\n", edid->width_cm, edid->height_cm); dp->sink_has_audio = drm_detect_monitor_audio(edid); @@ -279,7 +282,8 @@ cdn_dp_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { struct cdn_dp_device *dp = connector_to_dp(connector); - struct drm_display_info *display_info = &dp->connector.display_info; + struct drm_display_info *display_info = + &dp->mhdp.connector.base.display_info; u32 requested, actual, rate, sink_max, source_max = 0; u8 lanes, bpc; @@ -302,11 +306,11 @@ static int cdn_dp_connector_mode_valid(struct drm_connector *connector, requested = mode->clock * bpc * 3 / 1000; source_max = dp->lanes; - sink_max = drm_dp_max_lane_count(dp->dpcd); + sink_max = drm_dp_max_lane_count(dp->mhdp.dp.dpcd); lanes = min(source_max, sink_max); - source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE); - sink_max = drm_dp_max_link_rate(dp->dpcd); + source_max = CDNS_DP_MAX_LINK_RATE; + sink_max = drm_dp_max_link_rate(dp->mhdp.dp.dpcd); rate = min(source_max, sink_max); actual = rate * lanes / 100; @@ -315,7 +319,7 @@ static int cdn_dp_connector_mode_valid(struct drm_connector *connector, actual = actual * 8 / 10; if (requested > actual) { - DRM_DEV_DEBUG_KMS(dp->dev, + DRM_DEV_DEBUG_KMS(dp->mhdp.dev, "requested=%d, actual=%d, clock=%d\n", requested, actual, mode->clock); return MODE_CLOCK_HIGH; @@ -335,59 +339,62 @@ static int cdn_dp_firmware_init(struct cdn_dp_device *dp) const u32 *iram_data, *dram_data; const struct firmware *fw = dp->fw; const struct cdn_firmware_header *hdr; + struct device *dev = dp->mhdp.dev; hdr = (struct cdn_firmware_header *)fw->data; if (fw->size != le32_to_cpu(hdr->size_bytes)) { - DRM_DEV_ERROR(dp->dev, "firmware is invalid\n"); + DRM_DEV_ERROR(dev, "firmware is invalid\n"); return -EINVAL; } iram_data = (const u32 *)(fw->data + hdr->header_size); dram_data = (const u32 *)(fw->data + hdr->header_size + hdr->iram_size); - ret = cdn_dp_load_firmware(dp, iram_data, hdr->iram_size, - dram_data, hdr->dram_size); + ret = cdns_mhdp_load_firmware(&dp->mhdp, iram_data, hdr->iram_size, + dram_data, hdr->dram_size); if (ret) return ret; - ret = cdn_dp_set_firmware_active(dp, true); + ret = cdns_mhdp_set_firmware_active(&dp->mhdp, true); if (ret) { - DRM_DEV_ERROR(dp->dev, "active ucpu failed: %d\n", ret); + DRM_DEV_ERROR(dev, "active ucpu failed: %d\n", ret); return ret; } - return cdn_dp_event_config(dp); + return cdns_mhdp_event_config(&dp->mhdp); } static int cdn_dp_get_sink_capability(struct cdn_dp_device *dp) { + struct cdns_mhdp_device *mhdp = &dp->mhdp; int ret; if (!cdn_dp_check_sink_connection(dp)) return -ENODEV; - ret = cdn_dp_dpcd_read(dp, DP_DPCD_REV, dp->dpcd, + ret = drm_dp_dpcd_read(&mhdp->dp.aux, DP_DPCD_REV, mhdp->dp.dpcd, DP_RECEIVER_CAP_SIZE); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to get caps %d\n", ret); + DRM_DEV_ERROR(mhdp->dev, "Failed to get caps %d\n", ret); return ret; } kfree(dp->edid); - dp->edid = drm_do_get_edid(&dp->connector, - cdn_dp_get_edid_block, dp); + dp->edid = drm_do_get_edid(&mhdp->connector.base, + cdns_mhdp_get_edid_block, mhdp); return 0; } static int cdn_dp_enable_phy(struct cdn_dp_device *dp, struct cdn_dp_port *port) { + struct device *dev = dp->mhdp.dev; union extcon_property_value property; int ret; if (!port->phy_enabled) { ret = phy_power_on(port->phy); if (ret) { - DRM_DEV_ERROR(dp->dev, "phy power on failed: %d\n", + DRM_DEV_ERROR(dev, "phy power on failed: %d\n", ret); goto err_phy; } @@ -397,28 +404,28 @@ static int cdn_dp_enable_phy(struct cdn_dp_device *dp, struct cdn_dp_port *port) ret = cdn_dp_grf_write(dp, GRF_SOC_CON26, DPTX_HPD_SEL_MASK | DPTX_HPD_SEL); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to write HPD_SEL %d\n", ret); + DRM_DEV_ERROR(dev, "Failed to write HPD_SEL %d\n", ret); goto err_power_on; } - ret = cdn_dp_get_hpd_status(dp); + ret = cdns_mhdp_read_hpd(&dp->mhdp); if (ret <= 0) { if (!ret) - DRM_DEV_ERROR(dp->dev, "hpd does not exist\n"); + DRM_DEV_ERROR(dev, "hpd does not exist\n"); goto err_power_on; } ret = extcon_get_property(port->extcon, EXTCON_DISP_DP, EXTCON_PROP_USB_TYPEC_POLARITY, &property); if (ret) { - DRM_DEV_ERROR(dp->dev, "get property failed\n"); + DRM_DEV_ERROR(dev, "get property failed\n"); goto err_power_on; } port->lanes = cdn_dp_get_port_lanes(port); - ret = cdn_dp_set_host_cap(dp, port->lanes, property.intval); + ret = cdns_mhdp_set_host_cap(&dp->mhdp, property.intval); if (ret) { - DRM_DEV_ERROR(dp->dev, "set host capabilities failed: %d\n", + DRM_DEV_ERROR(dev, "set host capabilities failed: %d\n", ret); goto err_power_on; } @@ -428,7 +435,7 @@ static int cdn_dp_enable_phy(struct cdn_dp_device *dp, struct cdn_dp_port *port) err_power_on: if (phy_power_off(port->phy)) - DRM_DEV_ERROR(dp->dev, "phy power off failed: %d", ret); + DRM_DEV_ERROR(dev, "phy power off failed: %d", ret); else port->phy_enabled = false; @@ -446,7 +453,8 @@ static int cdn_dp_disable_phy(struct cdn_dp_device *dp, if (port->phy_enabled) { ret = phy_power_off(port->phy); if (ret) { - DRM_DEV_ERROR(dp->dev, "phy power off failed: %d", ret); + DRM_DEV_ERROR(dp->mhdp.dev, + "phy power off failed: %d", ret); return ret; } } @@ -470,16 +478,16 @@ static int cdn_dp_disable(struct cdn_dp_device *dp) ret = cdn_dp_grf_write(dp, GRF_SOC_CON26, DPTX_HPD_SEL_MASK | DPTX_HPD_DEL); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to clear hpd sel %d\n", + DRM_DEV_ERROR(dp->mhdp.dev, "Failed to clear hpd sel %d\n", ret); return ret; } - cdn_dp_set_firmware_active(dp, false); + cdns_mhdp_set_firmware_active(&dp->mhdp, false); cdn_dp_clk_disable(dp); dp->active = false; - dp->max_lanes = 0; - dp->max_rate = 0; + dp->mhdp.dp.rate = 0; + dp->mhdp.dp.num_lanes = 0; if (!dp->connected) { kfree(dp->edid); dp->edid = NULL; @@ -492,11 +500,11 @@ static int cdn_dp_enable(struct cdn_dp_device *dp) { int ret, i, lanes; struct cdn_dp_port *port; + struct device *dev = dp->mhdp.dev; port = cdn_dp_connected_port(dp); if (!port) { - DRM_DEV_ERROR(dp->dev, - "Can't enable without connection\n"); + DRM_DEV_ERROR(dev, "Can't enable without connection\n"); return -ENODEV; } @@ -509,7 +517,7 @@ static int cdn_dp_enable(struct cdn_dp_device *dp) ret = cdn_dp_firmware_init(dp); if (ret) { - DRM_DEV_ERROR(dp->dev, "firmware init failed: %d", ret); + DRM_DEV_ERROR(dp->mhdp.dev, "firmware init failed: %d", ret); goto err_clk_disable; } @@ -543,8 +551,9 @@ static void cdn_dp_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *adjusted) { struct cdn_dp_device *dp = encoder_to_dp(encoder); - struct drm_display_info *display_info = &dp->connector.display_info; - struct video_info *video = &dp->video_info; + struct drm_display_info *display_info = + &dp->mhdp.connector.base.display_info; + struct video_info *video = &dp->mhdp.video_info; switch (display_info->bpc) { case 10: @@ -562,20 +571,20 @@ static void cdn_dp_encoder_mode_set(struct drm_encoder *encoder, video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); - drm_mode_copy(&dp->mode, adjusted); + drm_mode_copy(&dp->mhdp.mode, adjusted); } static bool cdn_dp_check_link_status(struct cdn_dp_device *dp) { u8 link_status[DP_LINK_STATUS_SIZE]; struct cdn_dp_port *port = cdn_dp_connected_port(dp); - u8 sink_lanes = drm_dp_max_lane_count(dp->dpcd); + u8 sink_lanes = drm_dp_max_lane_count(dp->mhdp.dp.dpcd); - if (!port || !dp->max_rate || !dp->max_lanes) + if (!port || !dp->mhdp.dp.rate || !dp->mhdp.dp.num_lanes) return false; - if (cdn_dp_dpcd_read(dp, DP_LANE0_1_STATUS, link_status, - DP_LINK_STATUS_SIZE)) { + if (drm_dp_dpcd_read(&dp->mhdp.dp.aux, DP_LANE0_1_STATUS, link_status, + DP_LINK_STATUS_SIZE)) { DRM_ERROR("Failed to get link status\n"); return false; } @@ -587,15 +596,16 @@ static bool cdn_dp_check_link_status(struct cdn_dp_device *dp) static void cdn_dp_encoder_enable(struct drm_encoder *encoder) { struct cdn_dp_device *dp = encoder_to_dp(encoder); + struct device *dev = dp->mhdp.dev; int ret, val; - ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); + ret = drm_of_encoder_active_endpoint_id(dev->of_node, encoder); if (ret < 0) { - DRM_DEV_ERROR(dp->dev, "Could not get vop id, %d", ret); + DRM_DEV_ERROR(dev, "Could not get vop id, %d", ret); return; } - DRM_DEV_DEBUG_KMS(dp->dev, "vop %s output to cdn-dp\n", + DRM_DEV_DEBUG_KMS(dev, "vop %s output to cdn-dp\n", (ret) ? "LIT" : "BIG"); if (ret) val = DP_SEL_VOP_LIT | (DP_SEL_VOP_LIT << 16); @@ -610,33 +620,33 @@ static void cdn_dp_encoder_enable(struct drm_encoder *encoder) ret = cdn_dp_enable(dp); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to enable encoder %d\n", + DRM_DEV_ERROR(dev, "Failed to enable encoder %d\n", ret); goto out; } if (!cdn_dp_check_link_status(dp)) { - ret = cdn_dp_train_link(dp); + ret = cdns_mhdp_train_link(&dp->mhdp); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed link train %d\n", ret); + DRM_DEV_ERROR(dev, "Failed link train %d\n", ret); goto out; } } - ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_IDLE); + ret = cdns_mhdp_set_video_status(&dp->mhdp, CONTROL_VIDEO_IDLE); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to idle video %d\n", ret); + DRM_DEV_ERROR(dev, "Failed to idle video %d\n", ret); goto out; } - ret = cdn_dp_config_video(dp); + ret = cdns_mhdp_config_video(&dp->mhdp); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to config video %d\n", ret); + DRM_DEV_ERROR(dev, "Failed to config video %d\n", ret); goto out; } - ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_VALID); + ret = cdns_mhdp_set_video_status(&dp->mhdp, CONTROL_VIDEO_VALID); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to valid video %d\n", ret); + DRM_DEV_ERROR(dev, "Failed to valid video %d\n", ret); goto out; } @@ -652,7 +662,8 @@ static void cdn_dp_encoder_disable(struct drm_encoder *encoder) if (dp->active) { ret = cdn_dp_disable(dp); if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to disable encoder %d\n", + DRM_DEV_ERROR(dp->mhdp.dev, + "Failed to disable encoder %d\n", ret); } } @@ -692,7 +703,7 @@ static const struct drm_encoder_helper_funcs cdn_dp_encoder_helper_funcs = { static int cdn_dp_parse_dt(struct cdn_dp_device *dp) { - struct device *dev = dp->dev; + struct device *dev = dp->mhdp.dev; struct device_node *np = dev->of_node; struct platform_device *pdev = to_platform_device(dev); @@ -704,10 +715,10 @@ static int cdn_dp_parse_dt(struct cdn_dp_device *dp) return PTR_ERR(dp->grf); } - dp->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(dp->regs)) { + dp->mhdp.regs_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dp->mhdp.regs_base)) { DRM_DEV_ERROR(dev, "ioremap reg failed\n"); - return PTR_ERR(dp->regs); + return PTR_ERR(dp->mhdp.regs_base); } dp->core_clk = devm_clk_get(dev, "core-clk"); @@ -722,10 +733,10 @@ static int cdn_dp_parse_dt(struct cdn_dp_device *dp) return PTR_ERR(dp->pclk); } - dp->spdif_clk = devm_clk_get(dev, "spdif"); - if (IS_ERR(dp->spdif_clk)) { + dp->mhdp.spdif_clk = devm_clk_get(dev, "spdif"); + if (IS_ERR(dp->mhdp.spdif_clk)) { DRM_DEV_ERROR(dev, "cannot get spdif_clk\n"); - return PTR_ERR(dp->spdif_clk); + return PTR_ERR(dp->mhdp.spdif_clk); } dp->grf_clk = devm_clk_get(dev, "grf"); @@ -734,10 +745,10 @@ static int cdn_dp_parse_dt(struct cdn_dp_device *dp) return PTR_ERR(dp->grf_clk); } - dp->spdif_rst = devm_reset_control_get(dev, "spdif"); - if (IS_ERR(dp->spdif_rst)) { + dp->mhdp.spdif_rst = devm_reset_control_get(dev, "spdif"); + if (IS_ERR(dp->mhdp.spdif_rst)) { DRM_DEV_ERROR(dev, "no spdif reset control found\n"); - return PTR_ERR(dp->spdif_rst); + return PTR_ERR(dp->mhdp.spdif_rst); } dp->dptx_rst = devm_reset_control_get(dev, "dptx"); @@ -784,7 +795,7 @@ static int cdn_dp_audio_hw_params(struct device *dev, void *data, audio.format = AFMT_I2S; break; case HDMI_SPDIF: - audio.format = AFMT_SPDIF; + audio.format = AFMT_SPDIF_INT; break; default: DRM_DEV_ERROR(dev, "Invalid format %d\n", daifmt->fmt); @@ -792,9 +803,9 @@ static int cdn_dp_audio_hw_params(struct device *dev, void *data, goto out; } - ret = cdn_dp_audio_config(dp, &audio); + ret = cdns_mhdp_audio_config(&dp->mhdp, &audio); if (!ret) - dp->audio_info = audio; + dp->mhdp.audio_info = audio; out: mutex_unlock(&dp->lock); @@ -810,9 +821,9 @@ static void cdn_dp_audio_shutdown(struct device *dev, void *data) if (!dp->active) goto out; - ret = cdn_dp_audio_stop(dp, &dp->audio_info); + ret = cdns_mhdp_audio_stop(&dp->mhdp, &dp->mhdp.audio_info); if (!ret) - dp->audio_info.format = AFMT_UNUSED; + dp->mhdp.audio_info.format = AFMT_UNUSED; out: mutex_unlock(&dp->lock); } @@ -829,7 +840,7 @@ static int cdn_dp_audio_mute_stream(struct device *dev, void *data, goto out; } - ret = cdn_dp_audio_mute(dp, enable); + ret = cdns_mhdp_audio_mute(&dp->mhdp, enable); out: mutex_unlock(&dp->lock); @@ -841,7 +852,8 @@ static int cdn_dp_audio_get_eld(struct device *dev, void *data, { struct cdn_dp_device *dp = dev_get_drvdata(dev); - memcpy(buf, dp->connector.eld, min(sizeof(dp->connector.eld), len)); + memcpy(buf, dp->mhdp.connector.base.eld, + min(sizeof(dp->mhdp.connector.base.eld), len)); return 0; } @@ -864,11 +876,11 @@ static int cdn_dp_audio_codec_init(struct cdn_dp_device *dp, .max_i2s_channels = 8, }; - dp->audio_pdev = platform_device_register_data( - dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, - &codec_data, sizeof(codec_data)); + dp->mhdp.audio_pdev = platform_device_register_data( + dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, + &codec_data, sizeof(codec_data)); - return PTR_ERR_OR_ZERO(dp->audio_pdev); + return PTR_ERR_OR_ZERO(dp->mhdp.audio_pdev); } static int cdn_dp_request_firmware(struct cdn_dp_device *dp) @@ -876,6 +888,7 @@ static int cdn_dp_request_firmware(struct cdn_dp_device *dp) int ret; unsigned long timeout = jiffies + msecs_to_jiffies(CDN_FW_TIMEOUT_MS); unsigned long sleep = 1000; + struct device *dev = dp->mhdp.dev; WARN_ON(!mutex_is_locked(&dp->lock)); @@ -886,13 +899,13 @@ static int cdn_dp_request_firmware(struct cdn_dp_device *dp) mutex_unlock(&dp->lock); while (time_before(jiffies, timeout)) { - ret = request_firmware(&dp->fw, CDN_DP_FIRMWARE, dp->dev); + ret = request_firmware(&dp->fw, CDN_DP_FIRMWARE, dev); if (ret == -ENOENT) { msleep(sleep); sleep *= 2; continue; } else if (ret) { - DRM_DEV_ERROR(dp->dev, + DRM_DEV_ERROR(dev, "failed to request firmware: %d\n", ret); goto out; } @@ -902,7 +915,7 @@ static int cdn_dp_request_firmware(struct cdn_dp_device *dp) goto out; } - DRM_DEV_ERROR(dp->dev, "Timed out trying to load firmware\n"); + DRM_DEV_ERROR(dev, "Timed out trying to load firmware\n"); ret = -ETIMEDOUT; out: mutex_lock(&dp->lock); @@ -913,8 +926,9 @@ static void cdn_dp_pd_event_work(struct work_struct *work) { struct cdn_dp_device *dp = container_of(work, struct cdn_dp_device, event_work); - struct drm_connector *connector = &dp->connector; + struct drm_connector *connector = &dp->mhdp.connector.base; enum drm_connector_status old_status; + struct device *dev = dp->mhdp.dev; int ret; @@ -931,44 +945,45 @@ static void cdn_dp_pd_event_work(struct work_struct *work) /* Not connected, notify userspace to disable the block */ if (!cdn_dp_connected_port(dp)) { - DRM_DEV_INFO(dp->dev, "Not connected. Disabling cdn\n"); + DRM_DEV_INFO(dev, "Not connected. Disabling cdn\n"); dp->connected = false; /* Connected but not enabled, enable the block */ } else if (!dp->active) { - DRM_DEV_INFO(dp->dev, "Connected, not enabled. Enabling cdn\n"); + DRM_DEV_INFO(dev, "Connected, not enabled. Enabling cdn\n"); ret = cdn_dp_enable(dp); if (ret) { - DRM_DEV_ERROR(dp->dev, "Enable dp failed %d\n", ret); + DRM_DEV_ERROR(dev, "Enable dp failed %d\n", ret); dp->connected = false; } /* Enabled and connected to a dongle without a sink, notify userspace */ } else if (!cdn_dp_check_sink_connection(dp)) { - DRM_DEV_INFO(dp->dev, "Connected without sink. Assert hpd\n"); + DRM_DEV_INFO(dev, "Connected without sink. Assert hpd\n"); dp->connected = false; /* Enabled and connected with a sink, re-train if requested */ } else if (!cdn_dp_check_link_status(dp)) { - unsigned int rate = dp->max_rate; - unsigned int lanes = dp->max_lanes; - struct drm_display_mode *mode = &dp->mode; + unsigned int rate = dp->mhdp.dp.rate; + unsigned int lanes = dp->mhdp.dp.num_lanes; + struct drm_display_mode *mode = &dp->mhdp.mode; - DRM_DEV_INFO(dp->dev, "Connected with sink. Re-train link\n"); - ret = cdn_dp_train_link(dp); + DRM_DEV_INFO(dev, "Connected with sink. Re-train link\n"); + ret = cdns_mhdp_train_link(&dp->mhdp); if (ret) { dp->connected = false; - DRM_DEV_ERROR(dp->dev, "Train link failed %d\n", ret); + DRM_DEV_ERROR(dev, "Train link failed %d\n", ret); goto out; } /* If training result is changed, update the video config */ if (mode->clock && - (rate != dp->max_rate || lanes != dp->max_lanes)) { - ret = cdn_dp_config_video(dp); + (rate != dp->mhdp.dp.rate || + lanes != dp->mhdp.dp.num_lanes)) { + ret = cdns_mhdp_config_video(&dp->mhdp); if (ret) { dp->connected = false; - DRM_DEV_ERROR(dp->dev, + DRM_DEV_ERROR(dev, "Failed to config video %d\n", ret); } @@ -1037,7 +1052,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data) drm_encoder_helper_add(encoder, &cdn_dp_encoder_helper_funcs); - connector = &dp->connector; + connector = &dp->mhdp.connector.base; connector->polled = DRM_CONNECTOR_POLL_HPD; connector->dpms = DRM_MODE_DPMS_OFF; @@ -1061,7 +1076,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data) port = dp->port[i]; port->event_nb.notifier_call = cdn_dp_pd_event; - ret = devm_extcon_register_notifier(dp->dev, port->extcon, + ret = devm_extcon_register_notifier(dp->mhdp.dev, port->extcon, EXTCON_DISP_DP, &port->event_nb); if (ret) { @@ -1088,7 +1103,7 @@ static void cdn_dp_unbind(struct device *dev, struct device *master, void *data) { struct cdn_dp_device *dp = dev_get_drvdata(dev); struct drm_encoder *encoder = &dp->encoder.encoder; - struct drm_connector *connector = &dp->connector; + struct drm_connector *connector = &dp->mhdp.connector.base; cancel_work_sync(&dp->event_work); cdn_dp_encoder_disable(encoder); @@ -1148,7 +1163,7 @@ static int cdn_dp_probe(struct platform_device *pdev) dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); if (!dp) return -ENOMEM; - dp->dev = dev; + dp->mhdp.dev = dev; match = of_match_node(cdn_dp_dt_ids, pdev->dev.of_node); dp_data = (struct cdn_dp_data *)match->data; @@ -1192,8 +1207,8 @@ static int cdn_dp_remove(struct platform_device *pdev) { struct cdn_dp_device *dp = platform_get_drvdata(pdev); - platform_device_unregister(dp->audio_pdev); - cdn_dp_suspend(dp->dev); + platform_device_unregister(dp->mhdp.audio_pdev); + cdn_dp_suspend(dp->mhdp.dev); component_del(&pdev->dev, &cdn_dp_component_ops); return 0; @@ -1203,7 +1218,7 @@ static void cdn_dp_shutdown(struct platform_device *pdev) { struct cdn_dp_device *dp = platform_get_drvdata(pdev); - cdn_dp_suspend(dp->dev); + cdn_dp_suspend(dp->mhdp.dev); } static const struct dev_pm_ops cdn_dp_pm_ops = { diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h index 81ac9b658a70..8b1b15b92503 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.h +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h @@ -7,6 +7,7 @@ #ifndef _CDN_DP_CORE_H #define _CDN_DP_CORE_H +#include #include #include #include @@ -15,35 +16,6 @@ #define MAX_PHY 2 -enum audio_format { - AFMT_I2S = 0, - AFMT_SPDIF = 1, - AFMT_UNUSED, -}; - -struct audio_info { - enum audio_format format; - int sample_rate; - int channels; - int sample_width; -}; - -enum vic_pxl_encoding_format { - PXL_RGB = 0x1, - YCBCR_4_4_4 = 0x2, - YCBCR_4_2_2 = 0x4, - YCBCR_4_2_0 = 0x8, - Y_ONLY = 0x10, -}; - -struct video_info { - bool h_sync_polarity; - bool v_sync_polarity; - bool interlaced; - int color_depth; - enum vic_pxl_encoding_format color_fmt; -}; - struct cdn_firmware_header { u32 size_bytes; /* size of the entire header+image(s) in bytes */ u32 header_size; /* size of just the header in bytes */ @@ -62,12 +34,9 @@ struct cdn_dp_port { }; struct cdn_dp_device { - struct device *dev; + struct cdns_mhdp_device mhdp; struct drm_device *drm_dev; - struct drm_connector connector; struct rockchip_encoder encoder; - struct drm_display_mode mode; - struct platform_device *audio_pdev; struct work_struct event_work; struct edid *edid; @@ -77,29 +46,20 @@ struct cdn_dp_device { bool suspended; const struct firmware *fw; /* cdn dp firmware */ - unsigned int fw_version; /* cdn fw version */ bool fw_loaded; - void __iomem *regs; struct regmap *grf; struct clk *core_clk; struct clk *pclk; - struct clk *spdif_clk; struct clk *grf_clk; - struct reset_control *spdif_rst; struct reset_control *dptx_rst; struct reset_control *apb_rst; struct reset_control *core_rst; - struct audio_info audio_info; - struct video_info video_info; struct cdn_dp_port *port[MAX_PHY]; u8 ports; - u8 max_lanes; - unsigned int max_rate; u8 lanes; int active_port; - u8 dpcd[DP_RECEIVER_CAP_SIZE]; bool sink_has_audio; hdmi_codec_plugged_cb plugged_cb; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c b/drivers/gpu/drm/rockchip/cdn-dp-reg.c deleted file mode 100644 index 9d2163ef4d6e..000000000000 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.c +++ /dev/null @@ -1,960 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd - * Author: Chris Zhong - */ - -#include -#include -#include -#include -#include -#include - -#include "cdn-dp-core.h" -#include "cdn-dp-reg.h" - -#define CDN_DP_SPDIF_CLK 200000000 -#define FW_ALIVE_TIMEOUT_US 1000000 -#define MAILBOX_RETRY_US 1000 -#define MAILBOX_TIMEOUT_US 5000000 -#define LINK_TRAINING_RETRY_MS 20 -#define LINK_TRAINING_TIMEOUT_MS 500 - -void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk) -{ - writel(clk / 1000000, dp->regs + SW_CLK_H); -} - -void cdn_dp_clock_reset(struct cdn_dp_device *dp) -{ - u32 val; - - val = DPTX_FRMR_DATA_CLK_RSTN_EN | - DPTX_FRMR_DATA_CLK_EN | - DPTX_PHY_DATA_RSTN_EN | - DPTX_PHY_DATA_CLK_EN | - DPTX_PHY_CHAR_RSTN_EN | - DPTX_PHY_CHAR_CLK_EN | - SOURCE_AUX_SYS_CLK_RSTN_EN | - SOURCE_AUX_SYS_CLK_EN | - DPTX_SYS_CLK_RSTN_EN | - DPTX_SYS_CLK_EN | - CFG_DPTX_VIF_CLK_RSTN_EN | - CFG_DPTX_VIF_CLK_EN; - writel(val, dp->regs + SOURCE_DPTX_CAR); - - val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; - writel(val, dp->regs + SOURCE_PHY_CAR); - - val = SOURCE_PKT_SYS_RSTN_EN | - SOURCE_PKT_SYS_CLK_EN | - SOURCE_PKT_DATA_RSTN_EN | - SOURCE_PKT_DATA_CLK_EN; - writel(val, dp->regs + SOURCE_PKT_CAR); - - val = SPDIF_CDR_CLK_RSTN_EN | - SPDIF_CDR_CLK_EN | - SOURCE_AIF_SYS_RSTN_EN | - SOURCE_AIF_SYS_CLK_EN | - SOURCE_AIF_CLK_RSTN_EN | - SOURCE_AIF_CLK_EN; - writel(val, dp->regs + SOURCE_AIF_CAR); - - val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | - SOURCE_CIPHER_SYS_CLK_EN | - SOURCE_CIPHER_CHAR_CLK_RSTN_EN | - SOURCE_CIPHER_CHAR_CLK_EN; - writel(val, dp->regs + SOURCE_CIPHER_CAR); - - val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN | - SOURCE_CRYPTO_SYS_CLK_EN; - writel(val, dp->regs + SOURCE_CRYPTO_CAR); - - /* enable Mailbox and PIF interrupt */ - writel(0, dp->regs + APB_INT_MASK); -} - -static int cdn_dp_mailbox_read(struct cdn_dp_device *dp) -{ - int val, ret; - - ret = readx_poll_timeout(readl, dp->regs + MAILBOX_EMPTY_ADDR, - val, !val, MAILBOX_RETRY_US, - MAILBOX_TIMEOUT_US); - if (ret < 0) - return ret; - - return readl(dp->regs + MAILBOX0_RD_DATA) & 0xff; -} - -static int cdp_dp_mailbox_write(struct cdn_dp_device *dp, u8 val) -{ - int ret, full; - - ret = readx_poll_timeout(readl, dp->regs + MAILBOX_FULL_ADDR, - full, !full, MAILBOX_RETRY_US, - MAILBOX_TIMEOUT_US); - if (ret < 0) - return ret; - - writel(val, dp->regs + MAILBOX0_WR_DATA); - - return 0; -} - -static int cdn_dp_mailbox_validate_receive(struct cdn_dp_device *dp, - u8 module_id, u8 opcode, - u16 req_size) -{ - u32 mbox_size, i; - u8 header[4]; - int ret; - - /* read the header of the message */ - for (i = 0; i < 4; i++) { - ret = cdn_dp_mailbox_read(dp); - if (ret < 0) - return ret; - - header[i] = ret; - } - - mbox_size = (header[2] << 8) | header[3]; - - if (opcode != header[0] || module_id != header[1] || - req_size != mbox_size) { - /* - * If the message in mailbox is not what we want, we need to - * clear the mailbox by reading its contents. - */ - for (i = 0; i < mbox_size; i++) - if (cdn_dp_mailbox_read(dp) < 0) - break; - - return -EINVAL; - } - - return 0; -} - -static int cdn_dp_mailbox_read_receive(struct cdn_dp_device *dp, - u8 *buff, u16 buff_size) -{ - u32 i; - int ret; - - for (i = 0; i < buff_size; i++) { - ret = cdn_dp_mailbox_read(dp); - if (ret < 0) - return ret; - - buff[i] = ret; - } - - return 0; -} - -static int cdn_dp_mailbox_send(struct cdn_dp_device *dp, u8 module_id, - u8 opcode, u16 size, u8 *message) -{ - u8 header[4]; - int ret, i; - - header[0] = opcode; - header[1] = module_id; - header[2] = (size >> 8) & 0xff; - header[3] = size & 0xff; - - for (i = 0; i < 4; i++) { - ret = cdp_dp_mailbox_write(dp, header[i]); - if (ret) - return ret; - } - - for (i = 0; i < size; i++) { - ret = cdp_dp_mailbox_write(dp, message[i]); - if (ret) - return ret; - } - - return 0; -} - -static int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val) -{ - u8 msg[6]; - - msg[0] = (addr >> 8) & 0xff; - msg[1] = addr & 0xff; - msg[2] = (val >> 24) & 0xff; - msg[3] = (val >> 16) & 0xff; - msg[4] = (val >> 8) & 0xff; - msg[5] = val & 0xff; - return cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_REGISTER, - sizeof(msg), msg); -} - -static int cdn_dp_reg_write_bit(struct cdn_dp_device *dp, u16 addr, - u8 start_bit, u8 bits_no, u32 val) -{ - u8 field[8]; - - field[0] = (addr >> 8) & 0xff; - field[1] = addr & 0xff; - field[2] = start_bit; - field[3] = bits_no; - field[4] = (val >> 24) & 0xff; - field[5] = (val >> 16) & 0xff; - field[6] = (val >> 8) & 0xff; - field[7] = val & 0xff; - - return cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_FIELD, - sizeof(field), field); -} - -int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len) -{ - u8 msg[5], reg[5]; - int ret; - - msg[0] = (len >> 8) & 0xff; - msg[1] = len & 0xff; - msg[2] = (addr >> 16) & 0xff; - msg[3] = (addr >> 8) & 0xff; - msg[4] = addr & 0xff; - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_READ_DPCD, - sizeof(msg), msg); - if (ret) - goto err_dpcd_read; - - ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX, - DPTX_READ_DPCD, - sizeof(reg) + len); - if (ret) - goto err_dpcd_read; - - ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg)); - if (ret) - goto err_dpcd_read; - - ret = cdn_dp_mailbox_read_receive(dp, data, len); - -err_dpcd_read: - return ret; -} - -int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value) -{ - u8 msg[6], reg[5]; - int ret; - - msg[0] = 0; - msg[1] = 1; - msg[2] = (addr >> 16) & 0xff; - msg[3] = (addr >> 8) & 0xff; - msg[4] = addr & 0xff; - msg[5] = value; - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_DPCD, - sizeof(msg), msg); - if (ret) - goto err_dpcd_write; - - ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX, - DPTX_WRITE_DPCD, sizeof(reg)); - if (ret) - goto err_dpcd_write; - - ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg)); - if (ret) - goto err_dpcd_write; - - if (addr != (reg[2] << 16 | reg[3] << 8 | reg[4])) - ret = -EINVAL; - -err_dpcd_write: - if (ret) - DRM_DEV_ERROR(dp->dev, "dpcd write failed: %d\n", ret); - return ret; -} - -int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem, - u32 i_size, const u32 *d_mem, u32 d_size) -{ - u32 reg; - int i, ret; - - /* reset ucpu before load firmware*/ - writel(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET, - dp->regs + APB_CTRL); - - for (i = 0; i < i_size; i += 4) - writel(*i_mem++, dp->regs + ADDR_IMEM + i); - - for (i = 0; i < d_size; i += 4) - writel(*d_mem++, dp->regs + ADDR_DMEM + i); - - /* un-reset ucpu */ - writel(0, dp->regs + APB_CTRL); - - /* check the keep alive register to make sure fw working */ - ret = readx_poll_timeout(readl, dp->regs + KEEP_ALIVE, - reg, reg, 2000, FW_ALIVE_TIMEOUT_US); - if (ret < 0) { - DRM_DEV_ERROR(dp->dev, "failed to loaded the FW reg = %x\n", - reg); - return -EINVAL; - } - - reg = readl(dp->regs + VER_L) & 0xff; - dp->fw_version = reg; - reg = readl(dp->regs + VER_H) & 0xff; - dp->fw_version |= reg << 8; - reg = readl(dp->regs + VER_LIB_L_ADDR) & 0xff; - dp->fw_version |= reg << 16; - reg = readl(dp->regs + VER_LIB_H_ADDR) & 0xff; - dp->fw_version |= reg << 24; - - DRM_DEV_DEBUG(dp->dev, "firmware version: %x\n", dp->fw_version); - - return 0; -} - -int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable) -{ - u8 msg[5]; - int ret, i; - - msg[0] = GENERAL_MAIN_CONTROL; - msg[1] = MB_MODULE_ID_GENERAL; - msg[2] = 0; - msg[3] = 1; - msg[4] = enable ? FW_ACTIVE : FW_STANDBY; - - for (i = 0; i < sizeof(msg); i++) { - ret = cdp_dp_mailbox_write(dp, msg[i]); - if (ret) - goto err_set_firmware_active; - } - - /* read the firmware state */ - for (i = 0; i < sizeof(msg); i++) { - ret = cdn_dp_mailbox_read(dp); - if (ret < 0) - goto err_set_firmware_active; - - msg[i] = ret; - } - - ret = 0; - -err_set_firmware_active: - if (ret < 0) - DRM_DEV_ERROR(dp->dev, "set firmware active failed\n"); - return ret; -} - -int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip) -{ - u8 msg[8]; - int ret; - - msg[0] = CDN_DP_MAX_LINK_RATE; - msg[1] = lanes | SCRAMBLER_EN; - msg[2] = VOLTAGE_LEVEL_2; - msg[3] = PRE_EMPHASIS_LEVEL_3; - msg[4] = PTS1 | PTS2 | PTS3 | PTS4; - msg[5] = FAST_LT_NOT_SUPPORT; - msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL; - msg[7] = ENHANCED; - - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, - DPTX_SET_HOST_CAPABILITIES, - sizeof(msg), msg); - if (ret) - goto err_set_host_cap; - - ret = cdn_dp_reg_write(dp, DP_AUX_SWAP_INVERSION_CONTROL, - AUX_HOST_INVERT); - -err_set_host_cap: - if (ret) - DRM_DEV_ERROR(dp->dev, "set host cap failed: %d\n", ret); - return ret; -} - -int cdn_dp_event_config(struct cdn_dp_device *dp) -{ - u8 msg[5]; - int ret; - - memset(msg, 0, sizeof(msg)); - - msg[0] = DPTX_EVENT_ENABLE_HPD | DPTX_EVENT_ENABLE_TRAINING; - - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_ENABLE_EVENT, - sizeof(msg), msg); - if (ret) - DRM_DEV_ERROR(dp->dev, "set event config failed: %d\n", ret); - - return ret; -} - -u32 cdn_dp_get_event(struct cdn_dp_device *dp) -{ - return readl(dp->regs + SW_EVENTS0); -} - -int cdn_dp_get_hpd_status(struct cdn_dp_device *dp) -{ - u8 status; - int ret; - - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_HPD_STATE, - 0, NULL); - if (ret) - goto err_get_hpd; - - ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX, - DPTX_HPD_STATE, sizeof(status)); - if (ret) - goto err_get_hpd; - - ret = cdn_dp_mailbox_read_receive(dp, &status, sizeof(status)); - if (ret) - goto err_get_hpd; - - return status; - -err_get_hpd: - DRM_DEV_ERROR(dp->dev, "get hpd status failed: %d\n", ret); - return ret; -} - -int cdn_dp_get_edid_block(void *data, u8 *edid, - unsigned int block, size_t length) -{ - struct cdn_dp_device *dp = data; - u8 msg[2], reg[2], i; - int ret; - - for (i = 0; i < 4; i++) { - msg[0] = block / 2; - msg[1] = block % 2; - - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_GET_EDID, - sizeof(msg), msg); - if (ret) - continue; - - ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX, - DPTX_GET_EDID, - sizeof(reg) + length); - if (ret) - continue; - - ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg)); - if (ret) - continue; - - ret = cdn_dp_mailbox_read_receive(dp, edid, length); - if (ret) - continue; - - if (reg[0] == length && reg[1] == block / 2) - break; - } - - if (ret) - DRM_DEV_ERROR(dp->dev, "get block[%d] edid failed: %d\n", block, - ret); - - return ret; -} - -static int cdn_dp_training_start(struct cdn_dp_device *dp) -{ - unsigned long timeout; - u8 msg, event[2]; - int ret; - - msg = LINK_TRAINING_RUN; - - /* start training */ - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_TRAINING_CONTROL, - sizeof(msg), &msg); - if (ret) - goto err_training_start; - - timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS); - while (time_before(jiffies, timeout)) { - msleep(LINK_TRAINING_RETRY_MS); - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, - DPTX_READ_EVENT, 0, NULL); - if (ret) - goto err_training_start; - - ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX, - DPTX_READ_EVENT, - sizeof(event)); - if (ret) - goto err_training_start; - - ret = cdn_dp_mailbox_read_receive(dp, event, sizeof(event)); - if (ret) - goto err_training_start; - - if (event[1] & EQ_PHASE_FINISHED) - return 0; - } - - ret = -ETIMEDOUT; - -err_training_start: - DRM_DEV_ERROR(dp->dev, "training failed: %d\n", ret); - return ret; -} - -static int cdn_dp_get_training_status(struct cdn_dp_device *dp) -{ - u8 status[10]; - int ret; - - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_READ_LINK_STAT, - 0, NULL); - if (ret) - goto err_get_training_status; - - ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX, - DPTX_READ_LINK_STAT, - sizeof(status)); - if (ret) - goto err_get_training_status; - - ret = cdn_dp_mailbox_read_receive(dp, status, sizeof(status)); - if (ret) - goto err_get_training_status; - - dp->max_rate = drm_dp_bw_code_to_link_rate(status[0]); - dp->max_lanes = status[1]; - -err_get_training_status: - if (ret) - DRM_DEV_ERROR(dp->dev, "get training status failed: %d\n", ret); - return ret; -} - -int cdn_dp_train_link(struct cdn_dp_device *dp) -{ - int ret; - - ret = cdn_dp_training_start(dp); - if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to start training %d\n", ret); - return ret; - } - - ret = cdn_dp_get_training_status(dp); - if (ret) { - DRM_DEV_ERROR(dp->dev, "Failed to get training stat %d\n", ret); - return ret; - } - - DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->max_rate, - dp->max_lanes); - return ret; -} - -int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active) -{ - u8 msg; - int ret; - - msg = !!active; - - ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_SET_VIDEO, - sizeof(msg), &msg); - if (ret) - DRM_DEV_ERROR(dp->dev, "set video status failed: %d\n", ret); - - return ret; -} - -static int cdn_dp_get_msa_misc(struct video_info *video, - struct drm_display_mode *mode) -{ - u32 msa_misc; - u8 val[2] = {0}; - - switch (video->color_fmt) { - case PXL_RGB: - case Y_ONLY: - val[0] = 0; - break; - /* set YUV default color space conversion to BT601 */ - case YCBCR_4_4_4: - val[0] = 6 + BT_601 * 8; - break; - case YCBCR_4_2_2: - val[0] = 5 + BT_601 * 8; - break; - case YCBCR_4_2_0: - val[0] = 5; - break; - } - - switch (video->color_depth) { - case 6: - val[1] = 0; - break; - case 8: - val[1] = 1; - break; - case 10: - val[1] = 2; - break; - case 12: - val[1] = 3; - break; - case 16: - val[1] = 4; - break; - } - - msa_misc = 2 * val[0] + 32 * val[1] + - ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0); - - return msa_misc; -} - -int cdn_dp_config_video(struct cdn_dp_device *dp) -{ - struct video_info *video = &dp->video_info; - struct drm_display_mode *mode = &dp->mode; - u64 symbol; - u32 val, link_rate, rem; - u8 bit_per_pix, tu_size_reg = TU_SIZE; - int ret; - - bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? - (video->color_depth * 2) : (video->color_depth * 3); - - link_rate = dp->max_rate / 1000; - - ret = cdn_dp_reg_write(dp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE); - if (ret) - goto err_config_video; - - ret = cdn_dp_reg_write(dp, HSYNC2VSYNC_POL_CTRL, 0); - if (ret) - goto err_config_video; - - /* - * get a best tu_size and valid symbol: - * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32 - * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes) - * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set - * TU += 2 and repeat 2nd step. - */ - do { - tu_size_reg += 2; - symbol = (u64)tu_size_reg * mode->clock * bit_per_pix; - do_div(symbol, dp->max_lanes * link_rate * 8); - rem = do_div(symbol, 1000); - if (tu_size_reg > 64) { - ret = -EINVAL; - DRM_DEV_ERROR(dp->dev, - "tu error, clk:%d, lanes:%d, rate:%d\n", - mode->clock, dp->max_lanes, link_rate); - goto err_config_video; - } - } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || - (rem > 850) || (rem < 100)); - - val = symbol + (tu_size_reg << 8); - val |= TU_CNT_RST_EN; - ret = cdn_dp_reg_write(dp, DP_FRAMER_TU, val); - if (ret) - goto err_config_video; - - /* set the FIFO Buffer size */ - val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; - val /= (dp->max_lanes * link_rate); - val = div_u64(8 * (symbol + 1), bit_per_pix) - val; - val += 2; - ret = cdn_dp_reg_write(dp, DP_VC_TABLE(15), val); - - switch (video->color_depth) { - case 6: - val = BCS_6; - break; - case 8: - val = BCS_8; - break; - case 10: - val = BCS_10; - break; - case 12: - val = BCS_12; - break; - case 16: - val = BCS_16; - break; - } - - val += video->color_fmt << 8; - ret = cdn_dp_reg_write(dp, DP_FRAMER_PXL_REPR, val); - if (ret) - goto err_config_video; - - val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; - val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; - ret = cdn_dp_reg_write(dp, DP_FRAMER_SP, val); - if (ret) - goto err_config_video; - - val = (mode->hsync_start - mode->hdisplay) << 16; - val |= mode->htotal - mode->hsync_end; - ret = cdn_dp_reg_write(dp, DP_FRONT_BACK_PORCH, val); - if (ret) - goto err_config_video; - - val = mode->hdisplay * bit_per_pix / 8; - ret = cdn_dp_reg_write(dp, DP_BYTE_COUNT, val); - if (ret) - goto err_config_video; - - val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); - ret = cdn_dp_reg_write(dp, MSA_HORIZONTAL_0, val); - if (ret) - goto err_config_video; - - val = mode->hsync_end - mode->hsync_start; - val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); - ret = cdn_dp_reg_write(dp, MSA_HORIZONTAL_1, val); - if (ret) - goto err_config_video; - - val = mode->vtotal; - val |= (mode->vtotal - mode->vsync_start) << 16; - ret = cdn_dp_reg_write(dp, MSA_VERTICAL_0, val); - if (ret) - goto err_config_video; - - val = mode->vsync_end - mode->vsync_start; - val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); - ret = cdn_dp_reg_write(dp, MSA_VERTICAL_1, val); - if (ret) - goto err_config_video; - - val = cdn_dp_get_msa_misc(video, mode); - ret = cdn_dp_reg_write(dp, MSA_MISC, val); - if (ret) - goto err_config_video; - - ret = cdn_dp_reg_write(dp, STREAM_CONFIG, 1); - if (ret) - goto err_config_video; - - val = mode->hsync_end - mode->hsync_start; - val |= mode->hdisplay << 16; - ret = cdn_dp_reg_write(dp, DP_HORIZONTAL, val); - if (ret) - goto err_config_video; - - val = mode->vdisplay; - val |= (mode->vtotal - mode->vsync_start) << 16; - ret = cdn_dp_reg_write(dp, DP_VERTICAL_0, val); - if (ret) - goto err_config_video; - - val = mode->vtotal; - ret = cdn_dp_reg_write(dp, DP_VERTICAL_1, val); - if (ret) - goto err_config_video; - - ret = cdn_dp_reg_write_bit(dp, DP_VB_ID, 2, 1, 0); - -err_config_video: - if (ret) - DRM_DEV_ERROR(dp->dev, "config video failed: %d\n", ret); - return ret; -} - -int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio) -{ - int ret; - - ret = cdn_dp_reg_write(dp, AUDIO_PACK_CONTROL, 0); - if (ret) { - DRM_DEV_ERROR(dp->dev, "audio stop failed: %d\n", ret); - return ret; - } - - writel(0, dp->regs + SPDIF_CTRL_ADDR); - - /* clearn the audio config and reset */ - writel(0, dp->regs + AUDIO_SRC_CNTL); - writel(0, dp->regs + AUDIO_SRC_CNFG); - writel(AUDIO_SW_RST, dp->regs + AUDIO_SRC_CNTL); - writel(0, dp->regs + AUDIO_SRC_CNTL); - - /* reset smpl2pckt component */ - writel(0, dp->regs + SMPL2PKT_CNTL); - writel(AUDIO_SW_RST, dp->regs + SMPL2PKT_CNTL); - writel(0, dp->regs + SMPL2PKT_CNTL); - - /* reset FIFO */ - writel(AUDIO_SW_RST, dp->regs + FIFO_CNTL); - writel(0, dp->regs + FIFO_CNTL); - - if (audio->format == AFMT_SPDIF) - clk_disable_unprepare(dp->spdif_clk); - - return 0; -} - -int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable) -{ - int ret; - - ret = cdn_dp_reg_write_bit(dp, DP_VB_ID, 4, 1, enable); - if (ret) - DRM_DEV_ERROR(dp->dev, "audio mute failed: %d\n", ret); - - return ret; -} - -static void cdn_dp_audio_config_i2s(struct cdn_dp_device *dp, - struct audio_info *audio) -{ - int sub_pckt_num = 1, i2s_port_en_val = 0xf, i; - u32 val; - - if (audio->channels == 2) { - if (dp->max_lanes == 1) - sub_pckt_num = 2; - else - sub_pckt_num = 4; - - i2s_port_en_val = 1; - } else if (audio->channels == 4) { - i2s_port_en_val = 3; - } - - writel(0x0, dp->regs + SPDIF_CTRL_ADDR); - - writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL); - - val = MAX_NUM_CH(audio->channels); - val |= NUM_OF_I2S_PORTS(audio->channels); - val |= AUDIO_TYPE_LPCM; - val |= CFG_SUB_PCKT_NUM(sub_pckt_num); - writel(val, dp->regs + SMPL2PKT_CNFG); - - if (audio->sample_width == 16) - val = 0; - else if (audio->sample_width == 24) - val = 1 << 9; - else - val = 2 << 9; - - val |= AUDIO_CH_NUM(audio->channels); - val |= I2S_DEC_PORT_EN(i2s_port_en_val); - val |= TRANS_SMPL_WIDTH_32; - writel(val, dp->regs + AUDIO_SRC_CNFG); - - for (i = 0; i < (audio->channels + 1) / 2; i++) { - if (audio->sample_width == 16) - val = (0x02 << 8) | (0x02 << 20); - else if (audio->sample_width == 24) - val = (0x0b << 8) | (0x0b << 20); - - val |= ((2 * i) << 4) | ((2 * i + 1) << 16); - writel(val, dp->regs + STTS_BIT_CH(i)); - } - - switch (audio->sample_rate) { - case 32000: - val = SAMPLING_FREQ(3) | - ORIGINAL_SAMP_FREQ(0xc); - break; - case 44100: - val = SAMPLING_FREQ(0) | - ORIGINAL_SAMP_FREQ(0xf); - break; - case 48000: - val = SAMPLING_FREQ(2) | - ORIGINAL_SAMP_FREQ(0xd); - break; - case 88200: - val = SAMPLING_FREQ(8) | - ORIGINAL_SAMP_FREQ(0x7); - break; - case 96000: - val = SAMPLING_FREQ(0xa) | - ORIGINAL_SAMP_FREQ(5); - break; - case 176400: - val = SAMPLING_FREQ(0xc) | - ORIGINAL_SAMP_FREQ(3); - break; - case 192000: - val = SAMPLING_FREQ(0xe) | - ORIGINAL_SAMP_FREQ(1); - break; - } - val |= 4; - writel(val, dp->regs + COM_CH_STTS_BITS); - - writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL); - writel(I2S_DEC_START, dp->regs + AUDIO_SRC_CNTL); -} - -static void cdn_dp_audio_config_spdif(struct cdn_dp_device *dp) -{ - u32 val; - - writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL); - - val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4); - writel(val, dp->regs + SMPL2PKT_CNFG); - writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL); - - val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS; - writel(val, dp->regs + SPDIF_CTRL_ADDR); - - clk_prepare_enable(dp->spdif_clk); - clk_set_rate(dp->spdif_clk, CDN_DP_SPDIF_CLK); -} - -int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio) -{ - int ret; - - /* reset the spdif clk before config */ - if (audio->format == AFMT_SPDIF) { - reset_control_assert(dp->spdif_rst); - reset_control_deassert(dp->spdif_rst); - } - - ret = cdn_dp_reg_write(dp, CM_LANE_CTRL, LANE_REF_CYC); - if (ret) - goto err_audio_config; - - ret = cdn_dp_reg_write(dp, CM_CTRL, 0); - if (ret) - goto err_audio_config; - - if (audio->format == AFMT_I2S) - cdn_dp_audio_config_i2s(dp, audio); - else if (audio->format == AFMT_SPDIF) - cdn_dp_audio_config_spdif(dp); - - ret = cdn_dp_reg_write(dp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN); - -err_audio_config: - if (ret) - DRM_DEV_ERROR(dp->dev, "audio config failed: %d\n", ret); - return ret; -} diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h b/include/drm/bridge/cdns-mhdp.h similarity index 53% rename from drivers/gpu/drm/rockchip/cdn-dp-reg.h rename to include/drm/bridge/cdns-mhdp.h index 441248b7a79e..d76716d4edc6 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.h +++ b/include/drm/bridge/cdns-mhdp.h @@ -1,16 +1,31 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author: Chris Zhong + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ -#ifndef _CDN_DP_REG_H -#define _CDN_DP_REG_H +#ifndef CDNS_MHDP_H_ +#define CDNS_MHDP_H_ +#include +#include +#include +#include +#include #include #define ADDR_IMEM 0x10000 #define ADDR_DMEM 0x20000 +#define ADDR_PHY_AFE 0x80000 /* APB CFG addr */ #define APB_CTRL 0 @@ -78,6 +93,10 @@ #define SOURCE_PIF_SW_RESET 0x30834 /* bellow registers need access by mailbox */ +/* source phy comp */ +#define PHY_DATA_SEL 0x0818 +#define LANES_CONFIG 0x0814 + /* source car addr */ #define SOURCE_HDTX_CAR 0x0900 #define SOURCE_DPTX_CAR 0x0904 @@ -89,6 +108,17 @@ #define SOURCE_CIPHER_CAR 0x0920 #define SOURCE_CRYPTO_CAR 0x0924 +/* mhdp tx_top_comp */ +#define SCHEDULER_H_SIZE 0x1000 +#define SCHEDULER_V_SIZE 0x1004 +#define HDTX_SIGNAL_FRONT_WIDTH 0x100c +#define HDTX_SIGNAL_SYNC_WIDTH 0x1010 +#define HDTX_SIGNAL_BACK_WIDTH 0x1014 +#define HDTX_CONTROLLER 0x1018 +#define HDTX_HPD 0x1020 +#define HDTX_CLOCK_REG_0 0x1024 +#define HDTX_CLOCK_REG_1 0x1028 + /* clock meters addr */ #define CM_CTRL 0x0a00 #define CM_I2S_CTRL 0x0a04 @@ -308,18 +338,24 @@ #define MB_SIZE_LSB_ID 3 #define MB_DATA_ID 4 -#define MB_MODULE_ID_DP_TX 0x01 +#define MB_MODULE_ID_DP_TX 0x01 +#define MB_MODULE_ID_HDMI_TX 0x03 #define MB_MODULE_ID_HDCP_TX 0x07 #define MB_MODULE_ID_HDCP_RX 0x08 #define MB_MODULE_ID_HDCP_GENERAL 0x09 -#define MB_MODULE_ID_GENERAL 0x0a +#define MB_MODULE_ID_GENERAL 0x0A /* general opcode */ #define GENERAL_MAIN_CONTROL 0x01 #define GENERAL_TEST_ECHO 0x02 #define GENERAL_BUS_SETTINGS 0x03 #define GENERAL_TEST_ACCESS 0x04 +#define GENERAL_WRITE_REGISTER 0x05 +#define GENERAL_WRITE_FIELD 0x06 +#define GENERAL_READ_REGISTER 0x07 +#define GENERAL_GET_HPD_STATE 0x11 +/* DPTX opcode */ #define DPTX_SET_POWER_MNG 0x00 #define DPTX_SET_HOST_CAPABILITIES 0x01 #define DPTX_GET_EDID 0x02 @@ -338,12 +374,24 @@ #define DPTX_SET_LINK_BREAK_POINT 0x0f #define DPTX_FORCE_LANES 0x10 #define DPTX_HPD_STATE 0x11 +#define DPTX_ADJUST_LT 0x12 + +/* HDMI TX opcode */ +#define HDMI_TX_READ 0x00 +#define HDMI_TX_WRITE 0x01 +#define HDMI_TX_UPDATE_READ 0x02 +#define HDMI_TX_EDID 0x03 +#define HDMI_TX_EVENTS 0x04 +#define HDMI_TX_HPD_STATUS 0x05 +#define HDMI_TX_DEBUG_ECHO 0xAA +#define HDMI_TX_TEST 0xBB +#define HDMI_TX_EDID_INTERNAL 0xF0 #define FW_STANDBY 0 #define FW_ACTIVE 1 -#define DPTX_EVENT_ENABLE_HPD BIT(0) -#define DPTX_EVENT_ENABLE_TRAINING BIT(1) +#define MHDP_EVENT_ENABLE_HPD BIT(0) +#define MHDP_EVENT_ENABLE_TRAINING BIT(1) #define LINK_TRAINING_NOT_ACTIVE 0 #define LINK_TRAINING_RUN 1 @@ -387,7 +435,35 @@ #define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7) #define TU_SIZE 30 -#define CDN_DP_MAX_LINK_RATE DP_LINK_BW_5_4 +#define CDNS_DP_MAX_LINK_RATE 540000 + +#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16) +#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15) +#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18) +#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7) +#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11) +#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3) +#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0) +#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12) +#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19) +#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4) +#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6) +#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21) +#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22) +#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17) +#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_DATA_WR(x) (x) +#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16) +#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8) /* audio */ #define AUDIO_PACK_EN BIT(8) @@ -416,6 +492,24 @@ /* Reference cycles when using lane clock as reference */ #define LANE_REF_CYC 0x8000 +#define HOTPLUG_DEBOUNCE_MS 200 + +#define IRQ_IN 0 +#define IRQ_OUT 1 +#define IRQ_NUM 2 + +#define cdns_mhdp_plat_call(mhdp, operation) \ + (!(mhdp) ? -ENODEV : (((mhdp)->plat_data && (mhdp)->plat_data->operation) ? \ + (mhdp)->plat_data->operation(mhdp) : ENOIOCTLCMD)) + +/* bus access type */ +enum { + BUS_TYPE_NORMAL_APB = 0, + BUS_TYPE_NORMAL_SAPB = 1, + BUS_TYPE_LOW4K_APB = 2, + BUS_TYPE_LOW4K_SAPB = 3, +}; + enum voltage_swing_level { VOLTAGE_LEVEL_0, VOLTAGE_LEVEL_1, @@ -451,24 +545,261 @@ enum vic_bt_type { BT_709 = 0x1, }; -void cdn_dp_clock_reset(struct cdn_dp_device *dp); +enum audio_format { + AFMT_I2S = 0, + AFMT_SPDIF_INT = 1, + AFMT_SPDIF_EXT = 2, + AFMT_UNUSED, +}; + +enum { + MODE_DVI, + MODE_HDMI_1_4, + MODE_HDMI_2_0, +}; + +struct audio_info { + enum audio_format format; + int sample_rate; + int channels; + int sample_width; + int connector_type; +}; + +enum vic_pxl_encoding_format { + PXL_RGB = 0x1, + YCBCR_4_4_4 = 0x2, + YCBCR_4_2_2 = 0x4, + YCBCR_4_2_0 = 0x8, + Y_ONLY = 0x10, +}; + +struct video_info { + bool h_sync_polarity; + bool v_sync_polarity; + bool interlaced; + int color_depth; + enum vic_pxl_encoding_format color_fmt; +}; + +struct cdns_mhdp_host { + unsigned int link_rate; + u8 lanes_cnt; + u8 volt_swing; + u8 pre_emphasis; + u8 pattern_supp; + u8 fast_link; + u8 lane_mapping; + u8 enhanced; +}; + +struct cdns_mhdp_sink { + unsigned int link_rate; + u8 lanes_cnt; + u8 pattern_supp; + u8 fast_link; + u8 enhanced; +}; + +struct cdns_mhdp_bridge; +struct cdns_mhdp_connector; + +struct cdns_mhdp_bridge { + struct cdns_mhdp_device *mhdp; + struct drm_bridge base; + int pbn; + int8_t stream_id; + struct cdns_mhdp_connector *connector; + bool is_active; +}; + +struct cdns_mhdp_connector { + struct drm_connector base; + bool is_mst_connector; + struct drm_dp_mst_port *port; + struct cdns_mhdp_bridge *bridge; +}; + +struct cdns_mhdp_cec { + struct cec_adapter *adap; + struct device *dev; + struct mutex lock; + + struct cec_msg msg; + struct task_struct *cec_worker; +}; + +struct cdns_plat_data { + /* Vendor PHY support */ + int (*bind)(struct platform_device *pdev, + struct drm_encoder *encoder, + struct cdns_mhdp_device *mhdp); + void (*unbind)(struct device *dev); + + void (*plat_init)(struct cdns_mhdp_device *mhdp); + void (*plat_deinit)(struct cdns_mhdp_device *mhdp); + + int (*phy_set)(struct cdns_mhdp_device *mhdp); + bool (*phy_video_valid)(struct cdns_mhdp_device *mhdp); + int (*firmware_init)(struct cdns_mhdp_device *mhdp); + void (*pclk_rate)(struct cdns_mhdp_device *mhdp); + + int (*suspend)(struct cdns_mhdp_device *mhdp); + int (*resume)(struct cdns_mhdp_device *mhdp); + + int (*power_on)(struct cdns_mhdp_device *mhdp); + int (*power_off)(struct cdns_mhdp_device *mhdp); + + int bus_type; + int video_format; + char is_dp; + char *plat_name; +}; + +struct cdns_mhdp_device { + void __iomem *regs_base; + void __iomem *regs_sec; + + int bus_type; + + struct device *dev; + + struct cdns_mhdp_connector connector; + struct clk *spdif_clk; + struct reset_control *spdif_rst; + + struct platform_device *audio_pdev; + struct audio_info audio_info; + + struct cdns_mhdp_bridge bridge; + struct phy *phy; + + struct video_info video_info; + struct drm_display_mode mode; + const struct drm_display_mode *valid_mode; + unsigned int fw_version; + + struct drm_dp_mst_topology_mgr mst_mgr; + struct delayed_work hotplug_work; + + u32 lane_mapping; + bool link_up; + bool power_up; + bool plugged; + bool force_mode_set; + bool is_hpd; + bool is_ls1028a; + struct mutex lock; + struct mutex iolock; + + int irq[IRQ_NUM]; + + union { + struct _dp_data { + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + u32 rate; + u8 num_lanes; + struct drm_dp_aux aux; + struct cdns_mhdp_host host; + struct cdns_mhdp_sink sink; + bool is_mst; + bool can_mst; + } dp; + struct _hdmi_data { + struct cdns_mhdp_cec cec; + u32 char_rate; + u32 hdmi_type; + } hdmi; + }; + const struct cdns_plat_data *plat_data; + +}; + +u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset); +void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset); +void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp); +void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk); +u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp); +int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem, + u32 i_size, const u32 *d_mem, u32 d_size); +int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable); +int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip); +int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp); +u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp); +int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value); +int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, + u32 addr, u8 *data, u16 len); +int cdns_mhdp_get_edid_block(void *mhdp, u8 *edid, + unsigned int block, size_t length); +int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp); +int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active); +int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp); + +/* Audio */ +int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp, + struct audio_info *audio); +int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable); +int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp, + struct audio_info *audio); +int cdns_mhdp_register_audio_driver(struct device *dev); +void cdns_mhdp_unregister_audio_driver(struct device *dev); + +int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr); +int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val); +int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr, + u8 start_bit, u8 bits_no, u32 val); +int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp, u8 nlanes, + u16 udelay, u8 *lanes_data, + u8 *dpcd); + +int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp); +u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr); +int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val); +int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, + u8 opcode, u16 size, u8 *message); +int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, + u8 *buff, u16 buff_size); +int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, + u8 module_id, u8 opcode, + u16 req_size); +int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp); + +void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp, + u8 entry_id, u8 packet_len, u8 *packet, u8 packet_type); +int cdns_hdmi_get_edid_block(void *data, u8 *edid, u32 block, size_t length); +int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data); +int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value); +int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, int protocol, u32 char_rate); +int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, struct drm_display_mode *mode, + struct video_info *video_info); +int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp); +int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp); + +bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp); + +/* HDMI */ +int cdns_hdmi_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp); +void cdns_hdmi_remove(struct platform_device *pdev); +void cdns_hdmi_unbind(struct device *dev); +int cdns_hdmi_bind(struct platform_device *pdev, + struct drm_encoder *encoder, struct cdns_mhdp_device *mhdp); +void cdns_hdmi_set_sample_rate(struct cdns_mhdp_device *mhdp, unsigned int rate); +void cdns_hdmi_audio_enable(struct cdns_mhdp_device *mhdp); +void cdns_hdmi_audio_disable(struct cdns_mhdp_device *mhdp); + +/* DP */ +int cdns_dp_probe(struct platform_device *pdev, + struct cdns_mhdp_device *mhdp); +void cdns_dp_remove(struct platform_device *pdev); +void cdns_dp_unbind(struct device *dev); +int cdns_dp_bind(struct platform_device *pdev, + struct drm_encoder *encoder, struct cdns_mhdp_device *mhdp); + +/* CEC */ +#ifdef CONFIG_DRM_CDNS_HDMI_CEC +int cdns_mhdp_register_cec_driver(struct device *dev); +int cdns_mhdp_unregister_cec_driver(struct device *dev); +#endif -void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk); -int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem, - u32 i_size, const u32 *d_mem, u32 d_size); -int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable); -int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip); -int cdn_dp_event_config(struct cdn_dp_device *dp); -u32 cdn_dp_get_event(struct cdn_dp_device *dp); -int cdn_dp_get_hpd_status(struct cdn_dp_device *dp); -int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value); -int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len); -int cdn_dp_get_edid_block(void *dp, u8 *edid, - unsigned int block, size_t length); -int cdn_dp_train_link(struct cdn_dp_device *dp); -int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active); -int cdn_dp_config_video(struct cdn_dp_device *dp); -int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio); -int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable); -int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio); -#endif /* _CDN_DP_REG_H */ +#endif /* CDNS_MHDP_H_ */ -- 2.29.2