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u-boot (RK3328): BACKPORT: Set efuse auto mode and timing control
Backport commit[1] that enables efuse and fixes a bug related to video resolutions <=720p
1. 5708e8eeae
This commit is contained in:
Michele Zuccala
parent
93d721d857
commit
6053033169
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@ -0,0 +1,102 @@
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From 5708e8eeae53ad8ce605afdf61e5a83162dc5131 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sun, 7 Jan 2024 18:18:33 +0000
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Subject: [PATCH] rockchip: rk3328: Set efuse auto mode and timing control
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Reading from efuse return zero when mainline TF-A is used.
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=> dump_efuse
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00000000: 00 00 00 00 ....
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00000004: 00 00 00 00 ....
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00000008: 00 00 00 00 ....
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0000000c: 00 00 00 00 ....
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00000010: 00 00 00 00 ....
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00000014: 00 00 00 00 ....
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00000018: 00 00 00 00 ....
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0000001c: 00 00 00 00 ....
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However, when vendor TF-A blobs is used reading from efuse works.
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Change to use auto mode, enable finish and auto access err interrupts
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and set timing control using same values that vendor TF-A blob use to
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fix this.
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With this efuse can be read when either of mainline TF-A or vendor blob
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is used.
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=> dump_efuse
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00000000: 52 4b 33 82 RK3.
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00000004: 00 fe 21 55 ..!U
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00000008: 52 4b 57 34 RKW4
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0000000c: 35 30 32 39 5029
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00000010: 00 00 00 00 ....
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00000014: 08 25 0c 0f .%..
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00000018: 02 0d 08 00 ....
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0000001c: 00 00 f0 00 ....
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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---
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arch/arm/mach-rockchip/rk3328/rk3328.c | 38 ++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
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index de17b886827..ca623c0d3d0 100644
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--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
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+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
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@@ -19,6 +19,23 @@ DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0xFF100000
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#define UART2_BASE 0xFF130000
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#define FW_DDR_CON_REG 0xFF7C0040
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+#define EFUSE_NS_BASE 0xFF260000
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+
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+#define EFUSE_MOD 0x0000
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+#define EFUSE_INT_CON 0x0014
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+#define EFUSE_T_CSB_P 0x0028
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+#define EFUSE_T_PGENB_P 0x002C
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+#define EFUSE_T_LOAD_P 0x0030
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+#define EFUSE_T_ADDR_P 0x0034
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+#define EFUSE_T_STROBE_P 0x0038
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+#define EFUSE_T_CSB_R 0x003C
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+#define EFUSE_T_PGENB_R 0x0040
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+#define EFUSE_T_LOAD_R 0x0044
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+#define EFUSE_T_ADDR_R 0x0048
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+#define EFUSE_T_STROBE_R 0x004C
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+
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+#define EFUSE_USER_MODE 0x1
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+#define EFUSE_TIMING(s, l) (((s) << 16) | (l))
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
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@@ -50,10 +67,31 @@ struct mm_region *mem_map = rk3328_mem_map;
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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+ u32 reg;
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+
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/* We do some SoC one time setting here. */
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/* Disable the ddr secure region setting to make it non-secure */
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rk_setreg(FW_DDR_CON_REG, 0x200);
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+
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+ /* Use efuse auto mode */
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+ reg = readl(EFUSE_NS_BASE + EFUSE_MOD);
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+ writel(reg & ~EFUSE_USER_MODE, EFUSE_NS_BASE + EFUSE_MOD);
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+
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+ /* Enable efuse finish and auto access err interrupt */
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+ writel(0x07, EFUSE_NS_BASE + EFUSE_INT_CON);
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+
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+ /* Set efuse timing control */
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+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_CSB_P);
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+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_PGENB_P);
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+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_LOAD_P);
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+ writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_ADDR_P);
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+ writel(EFUSE_TIMING(2, 240), EFUSE_NS_BASE + EFUSE_T_STROBE_P);
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+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_CSB_R);
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+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_PGENB_R);
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+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R);
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+ writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R);
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+ writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R);
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#endif
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return 0;
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}
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@ -18,19 +18,19 @@ diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3
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index de17b88682..58300bdf3f 100644
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--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
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+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
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@@ -19,6 +19,8 @@ DECLARE_GLOBAL_DATA_PTR;
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@@ -16,6 +16,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0xFF100000
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#define UART2_BASE 0xFF130000
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#define FW_DDR_CON_REG 0xFF7C0040
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+#define QOS_VOP_OFFSET 0xFF760080
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+#define QOS_VOP_PRIORITY 0x8
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#define EFUSE_NS_BASE 0xFF260000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
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#define EFUSE_MOD 0x0000
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@@ -54,6 +56,9 @@ int arch_cpu_init(void)
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/* Disable the ddr secure region setting to make it non-secure */
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rk_setreg(FW_DDR_CON_REG, 0x200);
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writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R);
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writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R);
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writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R);
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+#else
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+ printf("Setting VOP QoS\n");
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+ rk_setreg(QOS_VOP_OFFSET + QOS_VOP_PRIORITY, 0xF);
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