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Kaizen/external/capstone/tests/details/tricore.yaml

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test_cases:
-
input:
bytes: [ 0x09, 0xcf, 0xbc, 0xf5, 0x09, 0xf4, 0x01, 0x00, 0x89, 0xfb, 0x8f, 0x74, 0x89, 0xfe, 0x48, 0x01, 0x29, 0x00, 0x19, 0x25, 0x29, 0x03, 0x09, 0xf4, 0x85, 0xf9, 0x68, 0x0f, 0x16, 0x01 ]
arch: "tricore"
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
-
asm_text: "ld.a a15, [+a12]#-4"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: a15
-
type: TRICORE_OP_MEM
mem_base: a12
mem_disp: -4
-
asm_text: "ld.b d4, [a15+]#1"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: d4
-
type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0x1
-
asm_text: "st.h [+a15]#0x1cf, d11"
details:
tricore:
operands:
-
type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0x1cf
-
type: TRICORE_OP_REG
reg: d11
-
asm_text: "st.d [a15+]#8, e14"
details:
tricore:
operands:
-
type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0x8
-
type: TRICORE_OP_REG
reg: e14
-
asm_text: "ld.w d0, [p0+c]#0x99"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: d0
-
type: TRICORE_OP_MEM
mem_base: p0
mem_disp: 0x99
-
asm_text: "ld.b d3, [p0+c]#-0x37"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: d3
-
type: TRICORE_OP_MEM
mem_base: p0
mem_disp: -0x37
-
asm_text: "ld.da p8, #0xf0003428"
details:
tricore:
operands:
-
type: TRICORE_OP_REG
reg: p8
-
type: TRICORE_OP_IMM
imm: 0xf0003428
-
asm_text: "and d15, #1"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
-
type: TRICORE_OP_IMM
imm: 0x1
- input:
bytes: [ 0x12, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "add d0, d15, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0x1a, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "add d15, d0, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0xaa, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "cmov d0, d15, #0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- type: TRICORE_OP_IMM
imm: 0
access: CS_AC_READ
- input:
bytes: [ 0x2a, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "cmov d0, d15, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0xea, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "cmovn d0, d15, #0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- type: TRICORE_OP_IMM
imm: 0
access: CS_AC_READ
- input:
bytes: [ 0x6a, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "cmovn d0, d15, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0xee, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "jnz d15, #0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE # fixme: should be read
- type: TRICORE_OP_IMM
imm: 0
access: CS_AC_READ
- input:
bytes: [ 0x6e, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "jz d15, #0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE # fixme: should be read
- type: TRICORE_OP_IMM
imm: 0
access: CS_AC_READ
- input:
bytes: [ 0xd8, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.a a15, [sp]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: a15
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: sp
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0xc8, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.a a0, [a15]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: a0
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0xcc, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.a a15, [a0]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: a15
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0x08, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.bu d0, [a15]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0x0c, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.bu d15, [a0]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0x88, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.h d0, [a15]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0x8c, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.h d15, [a0]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0x58, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.w d15, [sp]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: sp
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0x48, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.w d0, [a15]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0x4c, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ld.w d15, [a0]#0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ
- input:
bytes: [ 0xf8, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.a [sp]#0, a15"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: sp
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: a15
access: CS_AC_READ
- input:
bytes: [ 0xec, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.a [a0]#0, a15"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: a15
access: CS_AC_READ
- input:
bytes: [ 0xe8, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.a [a15]#0, a0"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: a0
access: CS_AC_READ
- input:
bytes: [ 0x2c, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.b [a0]#0, d15"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- input:
bytes: [ 0x28, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.b [a15]#0, d0"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0xac, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.h [a0]#0, d15"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- input:
bytes: [ 0xa8, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.h [a15]#0, d0"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0x78, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.w [sp]#0, d15"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: sp
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- input:
bytes: [ 0x6c, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.w [a0]#0, d15"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a0
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- input:
bytes: [ 0x68, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "st.w [a15]#0, d0"
details:
tricore:
operands:
- type: TRICORE_OP_MEM
mem_base: a15
mem_disp: 0
access: CS_AC_READ # fixme: should be write
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0x52, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "sub d0, d15, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0x5a, 0x0 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "sub d15, d0, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d15
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
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