mirror of
https://github.com/SimoneN64/Kaizen.git
synced 2025-04-02 10:41:53 -04:00
269 lines
No EOL
6.5 KiB
YAML
269 lines
No EOL
6.5 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R5, CS_MODE_BIG_ENDIAN ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "jal 0x40025c"
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details:
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mips:
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operands:
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type: MIPS_OP_IMM
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imm: 0x40025c
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asm_text: "nop"
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asm_text: "addiu $v0, $zero, 0xc"
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details:
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mips:
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operands:
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-
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type: MIPS_OP_REG
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reg: v0
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type: MIPS_OP_REG
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reg: zero
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type: MIPS_OP_IMM
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imm: 0xc
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asm_text: "lw $v0, 0($sp)"
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details:
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mips:
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operands:
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type: MIPS_OP_REG
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reg: v0
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type: MIPS_OP_MEM
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mem_base: sp
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asm_text: "ori $at, $at, 0x3456"
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details:
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mips:
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operands:
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type: MIPS_OP_REG
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reg: at
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type: MIPS_OP_REG
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reg: at
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type: MIPS_OP_IMM
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imm: 0x3456
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input:
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bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ]
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address: 0x0
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expected:
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insns:
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asm_text: "ori $at, $at, 0x3456"
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details:
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mips:
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operands:
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-
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type: MIPS_OP_REG
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reg: at
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type: MIPS_OP_REG
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reg: at
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type: MIPS_OP_IMM
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imm: 0x3456
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asm_text: "srl $v0, $at, 0x1f"
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details:
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mips:
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operands:
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type: MIPS_OP_REG
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reg: v0
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type: MIPS_OP_REG
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reg: at
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type: MIPS_OP_IMM
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imm: 0x1f
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input:
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bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "break 7, 0"
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details:
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mips:
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operands:
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type: MIPS_OP_IMM
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imm: 0x7
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type: MIPS_OP_IMM
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imm: 0x0
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asm_text: "wait 0x11"
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details:
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mips:
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operands:
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type: MIPS_OP_IMM
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imm: 0x11
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asm_text: "syscall 0x18c"
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details:
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mips:
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operands:
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type: MIPS_OP_IMM
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imm: 0x18c
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asm_text: "rotrv $t1, $a2, $a3"
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details:
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mips:
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operands:
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-
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type: MIPS_OP_REG
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reg: t1
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type: MIPS_OP_REG
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reg: a2
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type: MIPS_OP_REG
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reg: a3
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input:
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bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "lapc $a0, 0x64"
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details:
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mips:
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operands:
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-
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type: MIPS_OP_REG
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reg: a0
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type: MIPS_OP_IMM
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imm: 0x64
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asm_text: "align $a0, $v0, $v1, 2"
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details:
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mips:
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operands:
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-
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type: MIPS_OP_REG
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reg: a0
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type: MIPS_OP_REG
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reg: v0
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type: MIPS_OP_REG
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reg: v1
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type: MIPS_OP_IMM
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imm: 0x2
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input:
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bytes: [ 0x70, 0x00, 0xb2, 0xff ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "sdc3 $18, 0x70($sp)"
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details:
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mips:
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operands:
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-
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type: MIPS_OP_REG
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reg: "18"
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type: MIPS_OP_MEM
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mem_base: sp
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mem_disp: 0x70
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input:
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bytes: [ 0x70, 0x00, 0xb2, 0xff ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN]
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address: 0x0
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expected:
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insns:
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asm_text: "sd $s2, 0x70($sp)"
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details:
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mips:
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operands:
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type: MIPS_OP_REG
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reg: s2
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type: MIPS_OP_MEM
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mem_base: sp
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mem_disp: 0x70
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skip: true
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skip_reason: "Capstone python bindings do not handle CS_OPT_DETAIL_REAL."
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input:
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bytes: [ 0x00, 0x00, 0x00, 0x00 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_OPT_DETAIL, CS_OPT_DETAIL_REAL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
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address: 0x0
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expected:
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insns:
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asm_text: "nop"
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details:
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mips:
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operands:
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type: MIPS_OP_REG
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reg: zero
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type: MIPS_OP_REG
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reg: zero
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type: MIPS_OP_IMM
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imm: 0
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skip: true
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skip_reason: "Capstone python bindings do not handle CS_OPT_DETAIL_REAL."
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input:
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bytes: [ 0x38,0xf0,0x20,0x46 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_OPT_DETAIL, CS_OPT_DETAIL_REAL, CS_MODE_LITTLE_ENDIAN, CS_MODE_MIPS1 ]
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address: 0x0
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expected:
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insns:
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asm_text: "c.sf.d $f30, $f0"
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details:
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mips:
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operands:
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-
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type: MIPS_OP_REG
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reg: fcc0
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type: MIPS_OP_REG
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reg: f30
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type: MIPS_OP_REG
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reg: f0 |