/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM

enum {
  Xtensa_FeatureATOMCTL = 0,
  Xtensa_FeatureBoolean = 1,
  Xtensa_FeatureCLAMPS = 2,
  Xtensa_FeatureCoprocessor = 3,
  Xtensa_FeatureDFPAccel = 4,
  Xtensa_FeatureDebug = 5,
  Xtensa_FeatureDensity = 6,
  Xtensa_FeatureDiv32 = 7,
  Xtensa_FeatureESP32S2Ops = 8,
  Xtensa_FeatureESP32S3Ops = 9,
  Xtensa_FeatureException = 10,
  Xtensa_FeatureExtendedL32R = 11,
  Xtensa_FeatureForcedAtomics = 12,
  Xtensa_FeatureHIFI3 = 13,
  Xtensa_FeatureHighPriInterrupts = 14,
  Xtensa_FeatureInterrupt = 15,
  Xtensa_FeatureLoop = 16,
  Xtensa_FeatureMAC16 = 17,
  Xtensa_FeatureMEMCTL = 18,
  Xtensa_FeatureMINMAX = 19,
  Xtensa_FeatureMiscSR = 20,
  Xtensa_FeatureMul16 = 21,
  Xtensa_FeatureMul32 = 22,
  Xtensa_FeatureMul32High = 23,
  Xtensa_FeatureNSA = 24,
  Xtensa_FeaturePRID = 25,
  Xtensa_FeatureRegionProtection = 26,
  Xtensa_FeatureRelocatableVector = 27,
  Xtensa_FeatureS32C1I = 28,
  Xtensa_FeatureSEXT = 29,
  Xtensa_FeatureSingleFloat = 30,
  Xtensa_FeatureTHREADPTR = 31,
  Xtensa_FeatureTimerInt = 32,
  Xtensa_FeatureWindowed = 33,
  Xtensa_NumSubtargetFeatures = 34
};
#endif // GET_SUBTARGETINFO_ENUM