/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

{ XTENSA_FEATURE_HASDENSITY, "HasDensity" },
{ XTENSA_FEATURE_HASSINGLEFLOAT, "HasSingleFloat" },
{ XTENSA_FEATURE_HASWINDOWED, "HasWindowed" },
{ XTENSA_FEATURE_HASBOOLEAN, "HasBoolean" },
{ XTENSA_FEATURE_HASLOOP, "HasLoop" },
{ XTENSA_FEATURE_HASSEXT, "HasSEXT" },
{ XTENSA_FEATURE_HASCLAMPS, "HasCLAMPS" },
{ XTENSA_FEATURE_HASNSA, "HasNSA" },
{ XTENSA_FEATURE_HASMINMAX, "HasMINMAX" },
{ XTENSA_FEATURE_HASMUL16, "HasMul16" },
{ XTENSA_FEATURE_HASMUL32, "HasMul32" },
{ XTENSA_FEATURE_HASMUL32HIGH, "HasMul32High" },
{ XTENSA_FEATURE_HASDIV32, "HasDiv32" },
{ XTENSA_FEATURE_HASMAC16, "HasMAC16" },
{ XTENSA_FEATURE_HASDFPACCEL, "HasDFPAccel" },
{ XTENSA_FEATURE_HASS32C1I, "HasS32C1I" },
{ XTENSA_FEATURE_HASTHREADPTR, "HasTHREADPTR" },
{ XTENSA_FEATURE_HASEXTENDEDL32R, "HasExtendedL32R" },
{ XTENSA_FEATURE_HASATOMCTL, "HasATOMCTL" },
{ XTENSA_FEATURE_HASMEMCTL, "HasMEMCTL" },
{ XTENSA_FEATURE_HASDEBUG, "HasDebug" },
{ XTENSA_FEATURE_HASEXCEPTION, "HasException" },
{ XTENSA_FEATURE_HASHIGHPRIINTERRUPTS, "HasHighPriInterrupts" },
{ XTENSA_FEATURE_HASCOPROCESSOR, "HasCoprocessor" },
{ XTENSA_FEATURE_HASINTERRUPT, "HasInterrupt" },
{ XTENSA_FEATURE_HASRELOCATABLEVECTOR, "HasRelocatableVector" },
{ XTENSA_FEATURE_HASTIMERINT, "HasTimerInt" },
{ XTENSA_FEATURE_HASPRID, "HasPRID" },
{ XTENSA_FEATURE_HASREGIONPROTECTION, "HasRegionProtection" },
{ XTENSA_FEATURE_HASMISCSR, "HasMiscSR" },
{ XTENSA_FEATURE_HASESP32S2OPS, "HasESP32S2Ops" },
{ XTENSA_FEATURE_HASESP32S3OPS, "HasESP32S3Ops" },
{ XTENSA_FEATURE_HASHIFI3, "HasHIFI3" },
{ XTENSA_FEATURE_HASFORCEDATOMICS, "HasForcedAtomics" },